148 lines
5.4 KiB
C
Executable File
148 lines
5.4 KiB
C
Executable File
// Copyright (c) 2018-2019, XMOS Ltd, All rights reserved
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#ifndef _XMOS_SOC_EMBD_H_
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#define _XMOS_SOC_EMBD_H_
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/*=============================================*/
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/* The lines below are automatically generated */
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/*=============================================*/
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enum ap_control_ids {
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AP_STAGE_A_CONTROL_ID,
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AP_STAGE_B_CONTROL_ID,
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AP_STAGE_C_CONTROL_ID,
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AP_CONTROL_NUM_IDS
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};
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enum ap_control_resids {
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AP_STAGE_A_RESID = (AP_STAGE_A_CONTROL_ID + 1) << 4,
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AEC_RESID,
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AP_STAGE_B_RESID = (AP_STAGE_B_CONTROL_ID + 1) << 4,
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IC_RESID,
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VAD_RESID,
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AP_STAGE_C_RESID = (AP_STAGE_C_CONTROL_ID + 1) << 4,
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AGC_RESID,
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SUP_RESID,
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AP_CONTROL_RESID = 0xf0
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};
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#define AEC_CMD_GET_ADAPTION_CONFIG 0x84
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#define AEC_CMD_GET_BYPASS 0x80
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#define AEC_CMD_GET_COEFFICIENT_INDEX 0x90
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#define AEC_CMD_GET_ERLE_CH0 0x88
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#define AEC_CMD_GET_ERLE_CH1 0x89
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#define AEC_CMD_GET_F_BIN_COUNT 0x8E
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#define AEC_CMD_GET_FILTER_COEFFICIENTS 0x8F
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#define AEC_CMD_GET_FORCED_MU_VALUE 0x83
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#define AEC_CMD_GET_FRAME_ADVANCE 0x8A
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#define AEC_CMD_GET_MU_LIMITS 0x86
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#define AEC_CMD_GET_MU_SCALAR 0x85
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#define AEC_CMD_GET_X_CHANNEL_PHASES 0x8D
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#define AEC_CMD_GET_X_CHANNELS 0x8C
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#define AEC_CMD_GET_Y_CHANNELS 0x8B
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#define AEC_CMD_RESET_FILTER 0x09
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#define AEC_CMD_SET_ADAPTION_CONFIG 0x04
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#define AEC_CMD_SET_BYPASS 0x00
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#define AEC_CMD_SET_COEFFICIENT_INDEX 0x08
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#define AEC_CMD_SET_FORCED_MU_VALUE 0x03
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#define AEC_CMD_SET_MU_LIMITS 0x06
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#define AEC_CMD_SET_MU_SCALAR 0x05
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#define AP_CONTROL_CMD_GET_DELAY_SAMPLES 0x82
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#define AP_CONTROL_CMD_GET_STATUS 0x80
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#define AP_CONTROL_CMD_GET_VERSION 0x81
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#define AP_CONTROL_CMD_SET_DELAY_SAMPLES 0x00
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#define AP_STAGE_A_CMD_GET_ADEC_ENABLED 0x8E
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#define AP_STAGE_A_CMD_GET_ADEC_MODE 0x8F
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#define AP_STAGE_A_CMD_GET_DELAY_DIRECTION 0x8A
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#define AP_STAGE_A_CMD_GET_DELAY_ESTIMATE 0x8B
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#define AP_STAGE_A_CMD_GET_DELAY_ESTIMATOR_ENABLED 0x8C
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#define AP_STAGE_A_CMD_GET_MIC_SHIFT_SATURATE 0x8D
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#define AP_STAGE_A_CMD_SET_ADEC_ENABLED 0x04
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#define AP_STAGE_A_CMD_SET_DELAY_DIRECTION 0x01
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#define AP_STAGE_A_CMD_SET_DELAY_ESTIMATOR_ENABLED 0x02
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#define AP_STAGE_A_CMD_SET_MANUAL_ADEC_CYCLE_TRIGGER 0x05
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#define AP_STAGE_A_CMD_SET_MIC_SHIFT_SATURATE 0x03
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#define AP_STAGE_C_CMD_GET_AGC_ADAPT 0x8C
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#define AP_STAGE_C_CMD_GET_AGC_GAIN 0x8A
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#define AP_STAGE_C_CMD_GET_ASR_ALL_CHANNELS 0x91
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#define AP_STAGE_C_CMD_GET_REF_OUT 0x92
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#define AP_STAGE_C_CMD_SET_AGC_ADAPT 0x02
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#define AP_STAGE_C_CMD_SET_AGC_GAIN 0x00
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#define AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS 0x07
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#define AP_STAGE_C_CMD_SET_REF_OUT 0x08
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#define IC_CMD_GET_ADAPTION_CONFIG 0x84
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#define IC_CMD_GET_BYPASS 0x80
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#define IC_CMD_GET_COEFFICIENT_INDEX 0x8A
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#define IC_CMD_GET_FILTER_COEFFICIENTS 0x89
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#define IC_CMD_GET_PHASES 0x87
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#define IC_CMD_GET_PROC_FRAME_BINS 0x88
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#define IC_CMD_RESET_FILTER 0x09
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#define IC_CMD_SET_ADAPTION_CONFIG 0x04
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#define IC_CMD_SET_BYPASS 0x00
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#define IC_CMD_SET_COEFFICIENT_INDEX 0x08
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#define SUP_CMD_GET_BYPASS 0x80
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#define SUP_CMD_GET_ECHO_SUPPRESSION_ENABLED 0x81
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#define SUP_CMD_GET_NOISE_SUPPRESSION_ENABLED 0x82
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#define SUP_CMD_SET_BYPASS 0x00
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#define SUP_CMD_SET_ECHO_SUPPRESSION_ENABLED 0x01
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#define SUP_CMD_SET_NOISE_SUPPRESSION_ENABLED 0x02
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typedef struct _XMOS_COMMAND_MAP{
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unsigned char request_id;
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unsigned char command_id;
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unsigned int playload_len;
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}XMOS_COMMAND_MAP;
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XMOS_COMMAND_MAP xmos_command_map[]=
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{
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{AP_CONTROL_RESID , AP_CONTROL_CMD_SET_DELAY_SAMPLES , 4},
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{AP_CONTROL_RESID , AP_CONTROL_CMD_GET_VERSION , 5},
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{AP_CONTROL_RESID , AP_CONTROL_CMD_GET_DELAY_SAMPLES , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_SET_DELAY_DIRECTION , 4},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_GET_DELAY_DIRECTION , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_GET_DELAY_ESTIMATE , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_GET_ADEC_ENABLED , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_SET_ADEC_ENABLED , 4},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_GET_ADEC_MODE , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_GET_MIC_SHIFT_SATURATE , 5},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_SET_MIC_SHIFT_SATURATE , 4},
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{AP_CONTROL_RESID , AP_STAGE_A_CMD_SET_MANUAL_ADEC_CYCLE_TRIGGER , 4},
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{AEC_RESID , AEC_CMD_SET_BYPASS , 4},
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{AEC_RESID , AEC_CMD_GET_BYPASS , 5},
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{AEC_RESID , AEC_CMD_SET_ADAPTION_CONFIG , 4},
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{AEC_RESID , AEC_CMD_GET_ADAPTION_CONFIG , 5},
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{AEC_RESID , AEC_CMD_GET_FILTER_COEFFICIENTS , 15},
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{AEC_RESID , AEC_CMD_SET_FORCED_MU_VALUE , 4},
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{AEC_RESID , AEC_CMD_GET_FORCED_MU_VALUE , 5},
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{AEC_RESID , AEC_CMD_SET_MU_SCALAR , 4},
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{AEC_RESID , AEC_CMD_GET_MU_SCALAR , 5},
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{AEC_RESID , AEC_CMD_SET_MU_LIMITS , 8},
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{AEC_RESID , AEC_CMD_GET_MU_LIMITS , 9},
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{AEC_RESID , AEC_CMD_GET_ERLE_CH0 , 5},
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{AEC_RESID , AEC_CMD_GET_ERLE_CH1 , 5},
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{AEC_RESID , AEC_CMD_RESET_FILTER , 1},
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{IC_RESID , IC_CMD_SET_BYPASS , 4},
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{IC_RESID , IC_CMD_GET_BYPASS , 5},
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{IC_RESID , IC_CMD_SET_ADAPTION_CONFIG , 4},
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{IC_RESID , IC_CMD_GET_ADAPTION_CONFIG , 5},
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{IC_RESID , IC_CMD_RESET_FILTER , 4},
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{IC_RESID , IC_CMD_GET_FILTER_COEFFICIENTS , 15},
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{SUP_RESID , SUP_CMD_SET_BYPASS , 4},
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{SUP_RESID , SUP_CMD_GET_BYPASS , 5},
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{SUP_RESID , SUP_CMD_SET_NOISE_SUPPRESSION_ENABLED , 4},
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{SUP_RESID , SUP_CMD_GET_NOISE_SUPPRESSION_ENABLED , 5},
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{AP_STAGE_C_RESID , AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS , 4},
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{AP_STAGE_C_RESID , AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS , 5}
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};
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#endif /* _XMOS_SOC_EMBD_H_ */
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