// Copyright (c) 2018-2019, XMOS Ltd, All rights reserved
#ifndef _XMOS_SOC_EMBD_H_
#define _XMOS_SOC_EMBD_H_




/*=============================================*/
/* The lines below are automatically generated */
/*=============================================*/


enum ap_control_ids {
    AP_STAGE_A_CONTROL_ID,
    AP_STAGE_B_CONTROL_ID,
    AP_STAGE_C_CONTROL_ID,
    AP_CONTROL_NUM_IDS
};

enum ap_control_resids {
    AP_STAGE_A_RESID = (AP_STAGE_A_CONTROL_ID + 1) << 4,
    AEC_RESID,
    AP_STAGE_B_RESID = (AP_STAGE_B_CONTROL_ID + 1) << 4,
    IC_RESID,
    VAD_RESID,
    AP_STAGE_C_RESID = (AP_STAGE_C_CONTROL_ID + 1) << 4,
    AGC_RESID,
    SUP_RESID,
    AP_CONTROL_RESID = 0xf0
};

#define AEC_CMD_GET_ADAPTION_CONFIG 0x84
#define AEC_CMD_GET_BYPASS 0x80
#define AEC_CMD_GET_COEFFICIENT_INDEX 0x90
#define AEC_CMD_GET_ERLE_CH0 0x88
#define AEC_CMD_GET_ERLE_CH1 0x89
#define AEC_CMD_GET_F_BIN_COUNT 0x8E
#define AEC_CMD_GET_FILTER_COEFFICIENTS 0x8F
#define AEC_CMD_GET_FORCED_MU_VALUE 0x83
#define AEC_CMD_GET_FRAME_ADVANCE 0x8A
#define AEC_CMD_GET_MU_LIMITS 0x86
#define AEC_CMD_GET_MU_SCALAR 0x85
#define AEC_CMD_GET_X_CHANNEL_PHASES 0x8D
#define AEC_CMD_GET_X_CHANNELS 0x8C
#define AEC_CMD_GET_Y_CHANNELS 0x8B
#define AEC_CMD_RESET_FILTER 0x09
#define AEC_CMD_SET_ADAPTION_CONFIG 0x04
#define AEC_CMD_SET_BYPASS 0x00
#define AEC_CMD_SET_COEFFICIENT_INDEX 0x08
#define AEC_CMD_SET_FORCED_MU_VALUE 0x03
#define AEC_CMD_SET_MU_LIMITS 0x06
#define AEC_CMD_SET_MU_SCALAR 0x05
#define AP_CONTROL_CMD_GET_DELAY_SAMPLES 0x82
#define AP_CONTROL_CMD_GET_STATUS 0x80
#define AP_CONTROL_CMD_GET_VERSION 0x81
#define AP_CONTROL_CMD_SET_DELAY_SAMPLES 0x00
#define AP_STAGE_A_CMD_GET_ADEC_ENABLED 0x8E
#define AP_STAGE_A_CMD_GET_ADEC_MODE 0x8F
#define AP_STAGE_A_CMD_GET_DELAY_DIRECTION 0x8A
#define AP_STAGE_A_CMD_GET_DELAY_ESTIMATE 0x8B
#define AP_STAGE_A_CMD_GET_DELAY_ESTIMATOR_ENABLED 0x8C
#define AP_STAGE_A_CMD_GET_MIC_SHIFT_SATURATE 0x8D
#define AP_STAGE_A_CMD_SET_ADEC_ENABLED 0x04
#define AP_STAGE_A_CMD_SET_DELAY_DIRECTION 0x01
#define AP_STAGE_A_CMD_SET_DELAY_ESTIMATOR_ENABLED 0x02
#define AP_STAGE_A_CMD_SET_MANUAL_ADEC_CYCLE_TRIGGER 0x05
#define AP_STAGE_A_CMD_SET_MIC_SHIFT_SATURATE 0x03
#define AP_STAGE_C_CMD_GET_AGC_ADAPT 0x8C
#define AP_STAGE_C_CMD_GET_AGC_GAIN 0x8A
#define AP_STAGE_C_CMD_GET_ASR_ALL_CHANNELS 0x91
#define AP_STAGE_C_CMD_GET_REF_OUT 0x92
#define AP_STAGE_C_CMD_SET_AGC_ADAPT 0x02
#define AP_STAGE_C_CMD_SET_AGC_GAIN 0x00
#define AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS 0x07
#define AP_STAGE_C_CMD_SET_REF_OUT 0x08
#define IC_CMD_GET_ADAPTION_CONFIG 0x84
#define IC_CMD_GET_BYPASS 0x80
#define IC_CMD_GET_COEFFICIENT_INDEX 0x8A
#define IC_CMD_GET_FILTER_COEFFICIENTS 0x89
#define IC_CMD_GET_PHASES 0x87
#define IC_CMD_GET_PROC_FRAME_BINS 0x88
#define IC_CMD_RESET_FILTER 0x09
#define IC_CMD_SET_ADAPTION_CONFIG 0x04
#define IC_CMD_SET_BYPASS 0x00
#define IC_CMD_SET_COEFFICIENT_INDEX 0x08
#define SUP_CMD_GET_BYPASS 0x80
#define SUP_CMD_GET_ECHO_SUPPRESSION_ENABLED 0x81
#define SUP_CMD_GET_NOISE_SUPPRESSION_ENABLED 0x82
#define SUP_CMD_SET_BYPASS 0x00
#define SUP_CMD_SET_ECHO_SUPPRESSION_ENABLED 0x01
#define SUP_CMD_SET_NOISE_SUPPRESSION_ENABLED 0x02


typedef struct _XMOS_COMMAND_MAP{

	unsigned char request_id;
	unsigned char command_id;
	unsigned int  playload_len;

}XMOS_COMMAND_MAP;


XMOS_COMMAND_MAP xmos_command_map[]=
{
	{AP_CONTROL_RESID	, AP_CONTROL_CMD_SET_DELAY_SAMPLES				, 4},
	{AP_CONTROL_RESID	, AP_CONTROL_CMD_GET_VERSION					, 5},
	{AP_CONTROL_RESID	, AP_CONTROL_CMD_GET_DELAY_SAMPLES				, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_SET_DELAY_DIRECTION			, 4},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_GET_DELAY_DIRECTION			, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_GET_DELAY_ESTIMATE				, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_GET_ADEC_ENABLED				, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_SET_ADEC_ENABLED				, 4},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_GET_ADEC_MODE					, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_GET_MIC_SHIFT_SATURATE			, 5},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_SET_MIC_SHIFT_SATURATE			, 4},
	{AP_CONTROL_RESID	, AP_STAGE_A_CMD_SET_MANUAL_ADEC_CYCLE_TRIGGER	, 4},
	{AEC_RESID			, AEC_CMD_SET_BYPASS							, 4},
	{AEC_RESID			, AEC_CMD_GET_BYPASS							, 5},
	{AEC_RESID			, AEC_CMD_SET_ADAPTION_CONFIG					, 4},
	{AEC_RESID			, AEC_CMD_GET_ADAPTION_CONFIG					, 5},
	{AEC_RESID			, AEC_CMD_GET_FILTER_COEFFICIENTS				, 15},
	{AEC_RESID			, AEC_CMD_SET_FORCED_MU_VALUE					, 4},
	{AEC_RESID			, AEC_CMD_GET_FORCED_MU_VALUE					, 5},
	{AEC_RESID			, AEC_CMD_SET_MU_SCALAR							, 4},
	{AEC_RESID			, AEC_CMD_GET_MU_SCALAR							, 5},
	{AEC_RESID			, AEC_CMD_SET_MU_LIMITS							, 8},
	{AEC_RESID			, AEC_CMD_GET_MU_LIMITS							, 9},
	{AEC_RESID			, AEC_CMD_GET_ERLE_CH0							, 5},
	{AEC_RESID			, AEC_CMD_GET_ERLE_CH1							, 5},
	{AEC_RESID			, AEC_CMD_RESET_FILTER							, 1},
	{IC_RESID			, IC_CMD_SET_BYPASS								, 4},
	{IC_RESID			, IC_CMD_GET_BYPASS								, 5},
	{IC_RESID			, IC_CMD_SET_ADAPTION_CONFIG					, 4},
	{IC_RESID			, IC_CMD_GET_ADAPTION_CONFIG					, 5},
	{IC_RESID			, IC_CMD_RESET_FILTER							, 4},
	{IC_RESID			, IC_CMD_GET_FILTER_COEFFICIENTS				, 15},
	{SUP_RESID			, SUP_CMD_SET_BYPASS							, 4},
	{SUP_RESID			, SUP_CMD_GET_BYPASS							, 5},
	{SUP_RESID			, SUP_CMD_SET_NOISE_SUPPRESSION_ENABLED			, 4},
	{SUP_RESID			, SUP_CMD_GET_NOISE_SUPPRESSION_ENABLED			, 5},
	{AP_STAGE_C_RESID	, AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS			, 4},
	{AP_STAGE_C_RESID	, AP_STAGE_C_CMD_SET_ASR_ALL_CHANNELS			, 5}

};


#endif /* _XMOS_SOC_EMBD_H_ */