1.增加loader代码；2.修复wifi断流问题；3.优化触发速度;4.更新iq；5.修改拍照时间间隔

code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h

@@ -917,8 +917,8 @@
 #define DZOOM_FUNC                      ENABLE
 #define HUNTING_MCU_I2C				    DISABLE
 #define HUNTING_MCU_UART				ENABLE
-#define HUNTING_IR_LED_940				DISABLE
+#define HUNTING_IR_LED_940				ENABLE//DISABLE
-#define SF_BASE_VERSION				"7MD4RCwD3T6"
+#define SF_BASE_VERSION				"7MD4RCwD3T8"
 #define HW_S530 1
 #define DCF_DIR_NAME					"MEDIA" /* 100HUNTI */
 #define DCF_FILE_NAME					"SYFW"  /* IMAG0001.JPG */

code/application/source/cardv/SrcCode/System/SysStrg_Exe.c

@@ -851,6 +851,7 @@ INT32 System_OnStrgAttach(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 			DCF_ScanObj();
 //		}
 #endif
+		FileSys_GetDiskInfo(FST_INFO_DISK_SIZE);
 		System_SetState(SYS_STATE_FS, FS_INIT_OK);
 
 #if defined(__FREERTOS)

code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c

@@ -34,8 +34,8 @@
 #define VDO_MAIN_SIZE_W             2560
 #define VDO_MAIN_SIZE_H             1440
 
-#define VDO_CLONE_SIZE_W            848
+#define VDO_CLONE_SIZE_W            1920
-#define VDO_CLONE_SIZE_H            480
+#define VDO_CLONE_SIZE_H            1080
 
 #endif
 
@@ -183,7 +183,7 @@ void Movie_CommPoolInit(void)
 		mem_cfg.pool_info[id].blk_cnt = 4;
 		#endif
 	#else
-	mem_cfg.pool_info[id].blk_cnt = 6;
+	mem_cfg.pool_info[id].blk_cnt = 4;
 	#endif
 	mem_cfg.pool_info[id].ddr_id = DDR_ID0;
 #endif

code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_Exe.c

@@ -244,7 +244,7 @@ INT32 Set_Cur_Day_Night_Status(BOOL OnOff, UINT8 isSnapVideo)
 
 		vendor_isp_set_iq(IQT_ITEM_NIGHT_MODE, &night_mode);
 if (OnOff){
-	vos_util_delay_ms(100);
+	vos_util_delay_ms(330);
 }
 	if ((hd_ret = vendor_isp_uninit()) != HD_OK) {
 		DBG_ERR("vendor_isp_uninit() fail(%d)\r\n", hd_ret);
@@ -1328,11 +1328,11 @@ static void MovieExe_UserEventCb(UINT32 id, MOVIE_USER_CB_EVENT event_id, UINT32
 //		DCF_AddDBfile(info->path);
 //		DBG_DUMP("%s added to DCF\r\n", info->path);
 #if HUNTING_CAMERA_MCU == ENABLE
-        DBG_IND(" ===== MOVIE_USER_CB_EVENT_CLOSE_FILE_COMPLETED ===== \r\n");
+        DBG_IND(" ===== MOVIE_USER_CB_EVENT_CLOSE_FILE_COMPLETED ===== id:%d \r\n", id);
 		UIMenuStoreInfo *puiPara = sf_ui_para_get();
-        if(SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode)
+        if((SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode) && (id == _CFG_REC_ID_1))
         {
-            sf_share_mem_file_down(0);
+            sf_share_mem_file_down(0, 0);
         }
 #endif
 
@@ -1855,7 +1855,11 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 		MovieExe_SetIMECrop(i);
 		#endif
 	}
-    MovieMapping_GetStreamInfo(UI_GetData(FL_MOVIE_SIZE), (UINT32) &gMovie_Strm_Info);
+    
+	MovieMapping_GetStreamInfo(UI_GetData(FL_MOVIE_SIZE), (UINT32) &gMovie_Strm_Info);
+
+	DBG_DUMP("****** gMovie_Strm_Info {%lu, %lu}", gMovie_Strm_Info.size.w, gMovie_Strm_Info.size.h);
+
 	ImageApp_MovieMulti_Config(MOVIE_CONFIG_STREAM_INFO, (UINT32)&gMovie_Strm_Info);
 	ImageApp_MovieMulti_Config(MOVIE_CONFIG_AUDIO_INFO, (UINT32)&gMovie_Audio_Info);
 	ImageApp_MovieMulti_Config(MOVIE_CONFIG_DISP_INFO, (UINT32)&gMovie_Disp_Info);
@@ -1867,7 +1871,7 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 	ImageApp_MovieMulti_RegUserCB(MovieExe_UserEventCb);
 
 	//ImageApp_MovieMulti_SetParam(_CFG_DISP_ID_1, MOVIEMULTI_PARAM_DISP_REG_CB, (UINT32)MovieExe_DispCB);
-	//ImageApp_MovieMulti_SetParam(_CFG_STRM_ID_1, MOVIEMULTI_PARAM_WIFI_REG_CB, (UINT32)MovieExe_WifiCB);
+	ImageApp_MovieMulti_SetParam(_CFG_STRM_ID_1, MOVIEMULTI_PARAM_WIFI_REG_CB, (UINT32)MovieExe_WifiCB);
 	ImageApp_MovieMulti_SetParam(_CFG_DISP_ID_1, MOVIEMULTI_PARAM_DISP_REG_CB, (UINT32)MovieExe_PipCB);
 
 #if (MOVIE_DIRECT_FUNC == ENABLE)
@@ -2065,10 +2069,14 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 	#endif
 #endif
 #if(WIFI_AP_FUNC==ENABLE)
-    if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) {
+    // if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) {
-    	Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id);
+    // 	Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id);
-        Ux_PostEvent(NVTEVT_WIFI_EXE_MODE_DONE,1,E_OK);
+    //     Ux_PostEvent(NVTEVT_WIFI_EXE_MODE_DONE,1,E_OK);
-    }
+    // }
+
+	DBG_DUMP("****NVTEVT_EXE_MOVIE_STRM_START");
+	Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id);
+
 #endif
 #if MOVIE_UVAC_FUNC
 	Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_UVAC_START, 0);
@@ -2281,9 +2289,9 @@ INT32 MovieExe_OnClose(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 #endif
 
 #if(WIFI_AP_FUNC==ENABLE)
-    if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) {
+    // if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) {
     	Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_STOP, 1,gMovie_Strm_Info.strm_id);
-    }
+    // }
 #endif
 
 	ImageApp_MovieMulti_Close();

code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c

@@ -106,7 +106,7 @@ MOVIE_RECODE_INFO gMovie_Clone_Info[SENSOR_MAX_NUM] = {
 #endif
 		30,						//MOVIE_CFG_FRAME_RATE
 		250 * 1024,				//MOVIE_CFG_TARGET_RATE
-		_CFG_CODEC_H264,		//MOVIE_CFG_CODEC
+		_CFG_CODEC_H265,		//MOVIE_CFG_CODEC
 		_CFG_AUD_CODEC_AAC,		//MOVIE_CFG_AUD_CODEC
 		_CFG_REC_TYPE_AV,		//MOVIE_CFG_REC_MODE
 		#if (defined(_NVT_ETHREARCAM_TX_))

code/application/source/cardv/SrcCode/UIApp/MovieStamp/MovieStamp.c

@@ -601,11 +601,13 @@ void MovieStamp_Setup(UINT32 uiVEncOutPortId, UINT32 uiFlag, UINT32 uiImageWidth
         break;
     }
 
-#endif
+#if MOVIE_ISP_LOG
-
-#if 0//MOVIE_ISP_LOG
         g_VsFontIn[uiVEncOutPortId].pFont=(FONT *)gDateStampFontTbl12x20;
 #endif
+
+#endif
+
+
 /* do water logo scaling*/
 #if defined (WATERLOGO_FUNCTION) && (WATERLOGO_FUNCTION == ENABLE)
 	{

code/application/source/cardv/SrcCode/UIApp/Network/UIAppNetwork.c

@@ -1527,8 +1527,8 @@ INT32 UINet_WifiInit(UINT32 mode, UINT32 security)
 #if _TODO
 		WiFiIpc_interface_config("wlan0", gCurrIP, "255.255.255.0");
 #else
-		//WiFiIpc_interface_up("wlan0");
+		WiFiIpc_interface_up("wlan0");
-        sf_wifi_hw_init();
+        //sf_wifi_hw_init();
 
 #endif
 		if (_g_bFirstWifi) {
@@ -1660,7 +1660,7 @@ INT32 sf_net_wifi_uninit(UINT32 mode)
 	//WifiCmd_UninstallID();
 
 	//UINet_RtspUnInit();
-    ImageApp_Common_RtspStop(0);
+    // ImageApp_Common_RtspStop(0);
 
 	return ret;
 }

code/application/source/cardv/SrcCode/UIApp/Photo/UIAppPhoto_Exe.c

@@ -6127,7 +6127,7 @@ INT32 PhotoExe_Preview_SliceEncode_CB2(void* user_data)
 		}
 
 		/* thumbnail date stamp */
-		if(PhotoExe_Preview_SliceEncode_DateStamp(&video_frame_out_thumbnail, CAP_DS_EVENT_THUMB) != E_OK){
+		if(PhotoExe_Preview_SliceEncode_DateStamp(&video_frame_out_thumbnail, CAP_DS_EVENT_QV) != E_OK){
 			goto EXIT;
 		}		
 
@@ -6325,11 +6325,11 @@ INT32 PhotoExe_Preview_SliceEncode_CB3(void* user_data)
 #if HUNTING_CAMERA_MCU == ENABLE
 			char folder[4], number[5];
 
-			strncpy(folder, file_path + length - 21, 3);  // 复制到目标数组
+			strncpy(folder, file_path + length - 21, 3);
-			folder[3] = '\0';             // 添加结尾符
+			folder[3] = '\0';
 
-			strncpy(number, file_path + length - 8, 4);       // 复制到目标数组
+			strncpy(number, file_path + length - 8, 4);
-			number[4] = '\0';          // 添加结尾符
+			number[4] = '\0';
 
 			snprintf(tmp, sizeof(tmp), "%sW%s%s.JPG", PHOTO_THUMB_PATH, folder, number); /* DCF 8.3 naming rule */
 
@@ -6354,7 +6354,7 @@ INT32 PhotoExe_Preview_SliceEncode_CB3(void* user_data)
             UIMenuStoreInfo *puiPara = sf_ui_para_get();
             if(SF_CAM_MODE_PHOTO == puiPara->CamMode)
             {
-                sf_share_mem_file_down(0);
+                sf_share_mem_file_down(0, 0);
             }
 #endif
 		}

code/application/source/cardv/SrcCode/UIApp/Setup/UISetup_Exe.c

@@ -944,7 +944,7 @@ INT32 SetupExe_OnWifiStop(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray)
 	}
 
 	// stop live555 service
-	ImageApp_Common_RtspStop(0);
+	// ImageApp_Common_RtspStop(0);
 
 	UINet_WifiUnInit(UI_GetData(FL_NetWorkMode));
 #if ONVIF_FUNC

code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIFlowLVGL/UIFlowWifiLinkOK/UIFlowWifiLinkOKEventCallback.c

@@ -46,12 +46,12 @@ static void UIFlowWiFiLinkOK_DHCP_REQ(lv_obj_t* obj, const LV_USER_EVENT_NVTMSG_
 
 static void UIFlowWiFiLinkOK_DEAUTHENTICATED(lv_obj_t* obj, const LV_USER_EVENT_NVTMSG_DATA* msg)
 {
-UINT32 Live555_rtcp_support;
+// UINT32 Live555_rtcp_support;
 
 	// stop live555 service
-	ImageApp_Common_GetParam(0,IACOMMON_PARAM_SUPPORT_RTCP,&Live555_rtcp_support);
+	// ImageApp_Common_GetParam(0,IACOMMON_PARAM_SUPPORT_RTCP,&Live555_rtcp_support);
-	if (Live555_rtcp_support==0)
+	// if (Live555_rtcp_support==0)
-		ImageApp_Common_RtspStop(0);
+	// 	ImageApp_Common_RtspStop(0);
 
 //#NT#2016/03/23#Isiah Chang -begin
 //#NT#add new Wi-Fi UI flow.

code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h

@@ -220,5 +220,6 @@
 #define DEFAULT_TIMESEND3_SWITCH   SF_OFF
 #define DEFAULT_TIMESEND4_SWITCH   SF_OFF
 #define DEFAULT_FTP_SWITCH   SF_FTP_ON
+#define DEFAULT_MULTISHOT_INTEVEL SF_MULTISHOT_INTEVEL_1S
 
 #endif

code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c

@@ -1705,6 +1705,7 @@ void SysResetFlag(void)
 	puiPara->GpsAntiTheftSwitch = DEFAULT_GPS_ANTI_THEFT_SWITCH; 
 	puiPara->BatteryLogSwitch = DEFAULT_BATTRERY_LOG_SWITCH; 
 	puiPara->FtpSwitch = DEFAULT_FTP_SWITCH;
+	puiPara->MultiShotIntevel = DEFAULT_MULTISHOT_INTEVEL;
 
 	memset(puiPara ->FtpIp,'\0', sizeof(puiPara ->FtpIp));
 	memset(puiPara ->FtpPort, '\0', sizeof(puiPara ->FtpPort));

code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h

@@ -1979,6 +1979,13 @@ typedef enum
 	SF_FTP_MAX,
 } SF_FTP;
 
+typedef enum {
+	SF_MULTISHOT_INTEVEL_0S  = 0, 
+	SF_MULTISHOT_INTEVEL_1S,         
+	SF_MULTISHOT_INTEVEL_2S,
+	SF_MULTISHOT_INTEVEL_MAX,
+} SF_MULTISHOT_INTEVEL_e;
+
 extern void     Load_SysInfo(void);
 extern void     Save_SysInfo(void);
 extern void     Init_SysInfo(void);

code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIMovieMapping.c

@@ -62,7 +62,7 @@ typedef struct {
 #if (_BOARD_DRAM_SIZE_ == 0x04000000 || (defined(_NVT_ETHREARCAM_RX_) && ETH_REARCAM_CAPS_COUNT >=2))
 #define MOVIE_SIZE_WIFI_STREAMING	MOVIE_SIZE_640x360P30//MOVIE_SIZE_848x480P30_WIFI	// always use 848x480 for WiFi streaming temporarily
 #else
-#define MOVIE_SIZE_WIFI_STREAMING	MOVIE_SIZE_848x480P30	// always use 848x480 for WiFi streaming temporarily
+#define MOVIE_SIZE_WIFI_STREAMING	MOVIE_SIZE_640x480P30	// always use 848x480 for WiFi streaming temporarily
 #endif
 
 typedef struct {
@@ -195,9 +195,9 @@ static MOVIE_SIZE_ITEM g_MovieSizeTable[] = {
 	},
 
 	[MOVIE_SIZE_640x480P30] = {
-		{ 640, 480, 30, 150 * 1024, MEDIAREC_DAR_DEFAULT, IMAGERATIO_4_3},
+		{ 640, 480, 30, 200 * 1024, MEDIAREC_DAR_DEFAULT, IMAGERATIO_4_3},
 		{1, 3, 36, 8, -8, 0},
-		{1, 4, 30, 150 * 1024, 30, 26, 15, 45, 26, 15, 45, 0, 1, 8, 4},
+		{1, 4, 30, 200 * 1024, 30, 26, 15, 45, 26, 15, 45, 0, 1, 8, 4},
 	},
 
 	[MOVIE_SIZE_320x240P30] = {

code/application/source/sf_app/code/include/sf_commMng.h

@@ -20,8 +20,7 @@ SINT32 sf_sem_up(SINT32 semid, SINT32 who);
 SINT32 sf_sem_deinit(SINT32 semid);
 
 SINT32 sf_share_mem_file_init(void);
-SINT32 sf_share_mem_file_down(UINT32 to);
+SINT32 sf_share_mem_file_down(UINT32 to, SINT32 param);
-
 SINT32 sf_share_mem_file_deinit(void);
 
 SINT32 sf_share_mem_customer_update(void);

code/application/source/sf_app/code/include/sf_wifi_svr.h

@@ -940,6 +940,7 @@ void sf_get_wifi_ssid(char *ssid);
 int sf_is_ip_in_list(char *macbuf);
 UINT8 sf_get_wifi_type(void);
 void sf_wifi_app_start(void);
+UINT8 sf_wifi_server_stop_shoot_respond(UINT8 errCode);
 
 
 

code/application/source/sf_app/code/source/app/sf_service.c

@@ -996,9 +996,9 @@ static SINT16 app_file_transfer_Error_return_server(SF_FN_PARAM_S *pfnParam)
 	return s32ret;
 }
 
-static SINT16 app_file_transfer(SF_FN_PARAM_S *pfnParam)
+static SINT32 app_file_transfer(SF_FN_PARAM_S *pfnParam)
 {
-    SINT16 s32ret = 0;
+    SINT32 s32ret = 0;
 	SF_MESSAGE_BUF_S stMessageBuf = {0};
 	UIMenuStoreInfo *pCustomerParam = pfnParam->pstParam;
 	SF_PDT_PARAM_STATISTICS_S *pStaticParam = pfnParam->pstaticParam;
@@ -1087,7 +1087,7 @@ static SINT16 app_file_transfer(SF_FN_PARAM_S *pfnParam)
 
 SINT32 app_FileSend_thread(void)
 {
-	SINT16 s32ret = 0;
+	SINT32 s32ret = 0;
 	SF_FN_PARAM_S stpfncallback = { 0 };
 	stpfncallback.pstParam = sf_customer_param_get();
     stpfncallback.pstaticParam = sf_app_ui_para_get();
@@ -1104,7 +1104,7 @@ SINT32 app_FileSend_thread(void)
 		MLOGE("ERROR:%#x\n", s32ret);
 		ThumbSend.IsRun = 0;
         sf_file_thumb_cfg_clear();
-        sf_share_mem_file_down(1);
+        sf_share_mem_file_down(1, s32ret);
 		return s32ret;
 	}
 
@@ -1113,7 +1113,7 @@ SINT32 app_FileSend_thread(void)
 	//	app_file_transfer_Error_return_server(&stpfncallback);
 	ThumbSend.IsRun = 0;
     sf_file_thumb_cfg_clear();
-    sf_share_mem_file_down(1);
+    sf_share_mem_file_down(1, s32ret);
 	return s32ret;
 	
 	

code/application/source/sf_app/code/source/commMng/sf_share_mem.c

@@ -188,7 +188,7 @@ SINT32 sf_share_mem_file_init(void)
 }
 
 
-SINT32 sf_share_mem_file_down(UINT32 to)
+SINT32 sf_share_mem_file_down(UINT32 to, SINT32 param)
 {
 	SF_SRCFILE_ATTR_S *pThumbFileCfg = sf_file_thumb_cfg_get();
 
@@ -202,6 +202,7 @@ SINT32 sf_share_mem_file_down(UINT32 to)
         //sf_file_thumb_cfg_set_down(pThumbFileCfg);
         shmdt(pThumbFileCfg);
         SF_MESSAGE_BUF_S stMessageBuf = {0};
+        stMessageBuf.arg2 = param;
         stMessageBuf.arg1 = SF_PARA_CMD_UPDATE;
         stMessageBuf.cmdId = CMD_FILE;
         if(to)//to cardv

code/application/source/sf_app/code/source/wifi/sf_wifi_svr.c

@@ -575,7 +575,7 @@ void appsvr_getFileList(UINT8 *dirPath, UINT8 *startFileKey)
                 //printf("[appsvr_getFileList]nFileNums:%d, idx:%d, %s %d\n",nFileNums,idx,fname,gDevFileListNums);
                 //   printf("[appsvr_getFileList]nFileNums:%d, %d\n",nFileNums,gDevFileListNums);
                 strcpy((char *)gDevFileList[nFileNums + gDevFileListNums].fileNameString, (char *)ptr->d_name);
-                gDevFileList[nFileNums + gDevFileListNums].srcFileType = ptr->d_name[3] - '0';
+                gDevFileList[nFileNums + gDevFileListNums].srcFileType = (ptr->d_name[0] == 'W' ? 0 : (ptr->d_name[0] == 'S' ? 1 : 1));//ptr->d_name[3] - '0';
                 //printf("%s\n", g3g75DevFileList[nFileNums - idx + gDevFileListNums].fileName);
                 nFileNums ++ ;
                 //printf("[appsvr_getFileList]%d,%s\n",nFileNums - idx, gDevFileList[nFileNums - idx].fileName);
@@ -927,7 +927,7 @@ void sf_app_Get_Camera_Para(MSG_DEV_Param_Get_Rsp_T *CamPara)
 	
     //CamPara->imageSize  = puiPara->ImgSize;
 	
-    CamPara->multiShot  = puiPara->Multishot-1;
+    CamPara->multiShot  = puiPara->Multishot;
     CamPara->multiInterval  = puiPara->MultiShotIntevel;
     CamPara->sendMulti      = puiPara->SendMulti;
     CamPara->PirSensitivity = puiPara->PirSensitivity;
@@ -1764,7 +1764,7 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8  *pAppData, UINT16 dataLen)
                                         DCF_DIR_FREE_CHAR,
                                         DCF_FILE_FREE_CHAR,
                                         tempbuf+4,
-                                        (tempbuf[3] == '0' ? ".JPG" : (tempbuf[3] == '1' ? ".MP4" : ".MP4")));
+                                        (tempbuf[0] == 'W' ? ".JPG" : (tempbuf[0] == 'S' ? ".MP4" : ".MP4")));
                             }
                             else
                             {
@@ -1788,7 +1788,7 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8  *pAppData, UINT16 dataLen)
                             memcpy((char *)&msgParse.msgBuf.rctrlFileTransferInfo.filePath[0], (char *)fileName, strlen((char *)fileName)-12);
                             //msgParse.msgBuf.rctrlFileTransferInfo.fileName[13]=0;
                             //  msgParse.msgBuf.rctrlFileTransferInfo.filePath[13]=0;
-                            msgParse.msgBuf.rctrlFileTransferInfo.type = (tempbuf[3] == '0' ? 0 : (tempbuf[3] == '1' ? 1 : 1));
+                            msgParse.msgBuf.rctrlFileTransferInfo.type = (tempbuf[0] == 'W' ? 0 : (tempbuf[0] == 'S' ? 1 : 1));
                         }
                         //   printf("Send File:%s,function:%d,len:%d\n",msgParse.msgBuf.rctrlFileTransferInfo.fileName,function,strlen((char *)msgParse.msgBuf.rctrlFileTransferInfo.fileName));
                         if(function == 2)//download
@@ -2079,6 +2079,41 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8  *pAppData, UINT16 dataLen)
     return ntohs(pMsgStruct->cmd);
 }
 
+
+void appSvrResponseSocketSet(SINT32 socket)
+{
+	//printf("appSvrResponseSocketSet socket=%d\n", socket);
+	gSendSocket = socket;
+}
+
+UINT8 sf_wifi_server_stop_shoot_respond(UINT8 errCode)
+{
+    APP_SVR_PACKET_T   msgParse;
+    UINT32 tmp = 0;
+	printf("sf_wifi_server_StopShootRespond errCode = %d gSendSocket=%d\n", errCode,gSendSocket);
+	
+	if(gSendSocket > 0)
+	{
+    	//if(respFlag == 2)
+    	{
+    		//appUIParaSave();
+			msgParse.msgBuf.rctrlReset.cmdRet = 0;//errCode;
+			msgParse.msgBuf.rctrlReset.suffix = htons(MSG_END_FIX);
+            msgParse.msglen = htons(sizeof(MSG_DEV_Reset_Ctrl_RSP_T) + 2*sizeof(UINT16) );
+    	}
+    	
+        /* used for response */
+        msgParse.magicNum = htons(MSG_PRE_FIX);
+        msgParse.cmd = htons(CurrentWifiCmd);
+        msgParse.rsp = htons(MSG_WIFI_2_APP);
+        /* add the magic + len total 2*2 bytes; */
+        tmp=ntohs(msgParse.msglen);
+        send( gSendSocket,(void *)(&msgParse),  (tmp + sizeof(UINT16)*2), 0);
+    }
+	
+	return 0;
+}
+
 static int connectNum=0;
 static char clientMacList[24]={0};
 #if 0
@@ -2262,7 +2297,7 @@ void *sf_server_accept_thread(void *pData)
             }
 
             pClient = pClientContextHead ;
-            //appSvrResponseSocketSet(pClient->socket); //bad method it will error at socket over one---oliver
+            appSvrResponseSocketSet(pClient->socket); //bad method it will error at socket over one---oliver
 
             while(pClient != NULL)
             {

code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi

@@ -7,7 +7,7 @@
 		version-info = [00 01 00 01];
 		ae_expect_lum {
 			size = [b0 00 00 00];
-			data = [3c 00 00 00 3c 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 44 00 00 00 44 00 00 00 44 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00];
+			data = [3c 00 00 00 3c 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 27 00 00 00 2c 00 00 00 32 00 00 00 3a 00 00 00 44 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00];
 		};
 		ae_la_clamp {
 			size = [50 01 00 00];

code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi

@@ -15,7 +15,7 @@
 		};
 		awb_ct_weight {
 			size = [78 00 00 00];
-			data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 05 00 00 00 10 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00];
+			data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 04 00 00 00 08 00 00 00 09 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00];
 		};
 		awb_target {
 			size = [24 00 00 00];

code/lib/source/sifar/code/source/common/sf_battery.c

@@ -159,7 +159,7 @@ UINT32 sf_adc_value_get(UINT32 mux, UINT32 *pval)
         gpio_set_value(P_GPIO_1, 1);//adc_muxb
     }
 
-    vos_util_delay_us(1000);
+    vos_util_delay_ms(3);
 
     *pval = adc_readData(0);
     //printf("[%s:%d] *pval:%d\n", __FUNCTION__, __LINE__,*pval);
@@ -479,7 +479,7 @@ signed int sf_battery_adc_value_get(void)
 
 	if((sf_get_mode_flag() == 0) || (needCheckFirst == TRUE))
 	{
-		//printf("[%s:%d]ConfigureModeFlag=%d,needCheckFirst=%d\n",__FUNCTION__,__LINE__,ConfigureModeFlag,needCheckFirst);
+		printf("[%s:%d]ConfigureModeFlag=%d,needCheckFirst=%d\n",__FUNCTION__,__LINE__,sf_get_mode_flag(),needCheckFirst);
 		needCheckFirst = FALSE;
 
 		for(readBatCnt = 0; readBatCnt < 5;) //get max value of 5 times.
@@ -763,6 +763,7 @@ THREAD_RETTYPE sf_battery_check_thread(void *arg)
 {
 	THREAD_ENTRY();
     printf("[%s:%d] s\n", __FUNCTION__, __LINE__);
+    sf_battery_check_init();
 
 	while(sf_while_flag())
 	{

code/lib/source/sifar/code/source/common/sf_common.c

@@ -59,6 +59,7 @@
 #include <sf_keymng.h>
 #include <sf_param_struct.h>
 #include "UIAppNetwork.h"
+#include <sf_wifi_svr.h>
 
 BOOL isGoing2PowerOff = FALSE;
 UINT16 AutoOfftime = 0;
@@ -1121,14 +1122,14 @@ UINT32 sf_set_pir_sensitivity(UINT8 pirs)
     puiPara->DigitPirCnt = digPirCount[pirs];
     puiPara->DigitPirWindowTime = 0;
 
-	if(puiPara->PirSensitivity)
+	/*if(puiPara->PirSensitivity)
 	{
         puiPara->TimelapseSwitch = SF_OFF;
         puiPara->TimelapseTime.Hour = 0;
         puiPara->TimelapseTime.Min = 0;
         puiPara->TimelapseTime.Sec = 0;
         //Save_MenuInfo();
-	}
+	}*/
 	
 	return SUCCESS;
 }
@@ -1401,6 +1402,27 @@ static SINT32 sf_cardv_proccess_cmd_wifi(SF_MESSAGE_BUF_S *pMessageBuf)
 	return SF_SUCCESS;
 }
 
+static SINT32 sf_cardv_proccess_cmd_file(SF_MESSAGE_BUF_S *pMessageBuf)
+{
+    printf("[%s:%d] ID = %#x\n", __FUNCTION__, __LINE__,pMessageBuf->arg1);
+    //UIMenuStoreInfo *puiPara = sf_ui_para_get();
+
+	switch(pMessageBuf->arg1)
+	{
+		case SF_PARA_CMD_UPDATE:
+            sf_share_mem_file_init();
+            //if(SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode)
+            {
+                sf_wifi_server_stop_shoot_respond((UINT8)pMessageBuf->arg2);
+            }
+			break;
+
+		default:
+			break;
+	}
+	return SF_SUCCESS;
+}
+
 void* sf_cardv_message_thread(void *argv)
 {
 	SINT32 ret = 0;
@@ -1412,7 +1434,7 @@ void* sf_cardv_message_thread(void *argv)
 		{
 			continue;
 		}
-		printf("cmdId:%#x,paramBuf[%d]\n",stMessagebuf.cmdId,stMessagebuf.arg1);
+		printf("[%s:%d]cmdId:%#x,paramBuf[%d]\n", __FUNCTION__, __LINE__,stMessagebuf.cmdId,stMessagebuf.arg1);
 		switch(stMessagebuf.cmdId)
 		{
 			case CMD_MCU:
@@ -1428,7 +1450,7 @@ void* sf_cardv_message_thread(void *argv)
 				//sf_cardv_proccess_cmd_gprs(&stMessagebuf);
 				break;
             case CMD_FILE:
-                sf_share_mem_file_init();
+                sf_cardv_proccess_cmd_file(&stMessagebuf);
                 break;
             case CMD_WIFI:
                 sf_cardv_proccess_cmd_wifi(&stMessagebuf);

code/na51089_linux_sdk_app_filelist.txt

@@ -1,6 +1,6 @@
 ; Source Insight Project File List
 ; Project Name: s530_app
-; Generated by Source Insight 4.00.0107 at 2023/5/22 16:12:40
+; Generated by Source Insight 4.00.0107 at 2023/5/29 17:59:28
 ; Version=4.00.0107
 ;
 ; Each line should contain either a file name, a wildcard, or a sub-directory name.
@@ -604,9 +604,7 @@ application\source\sf_app\code\include\sf_system.h
 application\source\sf_app\code\include\sf_systemMng.h
 application\source\sf_app\code\include\sf_transdata1.h
 application\source\sf_app\code\include\sf_type.h
-application\source\sf_app\code\include\sf_wifi_data_transfer.h
 application\source\sf_app\code\include\sf_wifi_svr.h
-application\source\sf_app\code\include\sf_wifi_svr_send.h
 application\source\sf_app\code\include\sha256.h
 application\source\sf_app\code\include\split.h
 application\source\sf_app\code\source\4gMng\sf_4G_auto_operation.c
@@ -670,9 +668,7 @@ application\source\sf_app\code\source\utils\sf_qrutils.c
 application\source\sf_app\code\source\wifi\sf_data_transfer.c
 application\source\sf_app\code\source\wifi\sf_getapinfo.c
 application\source\sf_app\code\source\wifi\sf_svr_send.c
-application\source\sf_app\code\source\wifi\sf_wifi_data_transfer.c
 application\source\sf_app\code\source\wifi\sf_wifi_svr.c
-application\source\sf_app\code\source\wifi\sf_wifi_svr_send.c
 application\source\sf_app\component\liveMng\inc\exports\aiot_authorize_api.h
 application\source\sf_app\component\liveMng\inc\exports\iot_export_awss.h
 application\source\sf_app\component\liveMng\inc\exports\iot_export_coap.h

configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/ModelConfig.mk

@@ -1,63 +0,0 @@
-#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-#!automatically-generated file. do not edit!!
-#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-
-BOARD_DRAM_ADDR = 0x00000000
-BOARD_DRAM_SIZE = 0x08000000
-BOARD_SHMEM_ADDR = 0x00007E00
-BOARD_SHMEM_SIZE = 0x00000200
-BOARD_LOADER_ADDR = 0x01000000
-BOARD_LOADER_SIZE = 0x00080000
-BOARD_FDT_ADDR = 0x01800000
-BOARD_FDT_SIZE = 0x00040000
-BOARD_RTOS_ADDR = 0x01840000
-BOARD_RTOS_SIZE = 0x00FC0000
-BOARD_LINUXTMP_ADDR = 0x02800000
-BOARD_LINUXTMP_SIZE = 0x04000000
-BOARD_UBOOT_ADDR = 0x06800000
-BOARD_UBOOT_SIZE = 0x01640000
-BOARD_LOGO-FB_ADDR = 0x07E40000
-BOARD_LOGO-FB_SIZE = 0x001C0000
-BOARD_LINUX_ADDR = 0x00000000
-BOARD_LINUX_SIZE = 0x01800000
-BOARD_LINUX_MAXBLK_ADDR = 0x00000000
-BOARD_LINUX_MAXBLK_SIZE = 0x01800000
-BOARD_MEDIA_ADDR = 0x03600000
-BOARD_MEDIA_SIZE = 0x04A00000
-BIN_NAME = FW98565A
-BIN_NAME_T = FW98565T
-RTOS_APP_MAIN = cardv
-EMBMEM_BLK_SIZE = 0x10000
-EMBMEM = EMBMEM_SPI_NOR
-FW_TYPE = FW_TYPE_PARTIAL
-UI_STYLE = UI_STYLE_LVGL
-NVT_CFG_APP_EXTERNAL = hostapd wireless_tool iperf-3 wpa_supplicant dhd_priv
-NVT_CFG_APP = mem cardv memcpy isp_demon sf_app
-NVT_ROOTFS_ETC = 
-NVT_BINARY_FILE_STRIP = yes
-NVT_CFG_KERNEL_CFG = na51089_evb_cardv_defconfig_release
-NVT_MAKE_POST = make_post.sh
-NVT_SAMPLES_INSTALL = DISABLE
-NVT_CFG_UBOOT_CFG = 
-NVT_LINUX_SMP = NVT_LINUX_SMP_OFF
-NVT_CHIP_ID = CHIP_NA51089
-NVT_LINUX_COMPRESS = NVT_LINUX_COMPRESS_GZ
-NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP
-NVT_ROOTFS_TYPE = NVT_ROOTFS_TYPE_RAMDISK
-LCD1 = disp_if8b_lcd1_psd200_st7789v
-SENSOR1 = sen_os05b10
-SENSOR1_CFG = sen_os05b10_565
-SENSOR2 = sen_off
-SENSOR2_CFG = sen_off
-NVT_ROOTFS_RW_PART_EN = NVT_ROOTFS_RW_PART_EN_ON
-NVT_ETHERNET = NVT_ETHERNET_NONE
-NVT_SDIO_WIFI = NVT_SDIO_WIFI_RTK
-NVT_USB_WIFI = NVT_USB_WIFI_NONE
-NVT_USB_4G = NVT_USB_4G_NONE
-WIFI_RTK_MDL = WIFI_RTK_MDL_8189
-WIFI_BRCM_MDL = WIFI_BRCM_MDL_43456c5_ampk6256c5
-WIFI_NVT_MDL = WIFI_NVT_MDL_18211
-NVT_CURL_SSL = NVT_CURL_SSL_OPENSSL
-NVT_UBOOT_ENV_IN_STORG_SUPPORT = NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF
-TOUCH = TOUCH_OFF
-UBOOT_ONLY_LOAD_LINUX = UBOOT_ONLY_LOAD_LINUX_ON

configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-i2c.dtsi

@@ -6,7 +6,7 @@
  */
 
 / {
-	i2c0: i2c@f0220000 {  compatible = "nvt,nvt_i2c"; reg = <0xf0220000 0x100>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; id = <0>; /*gsr = <2>;*/ /* tsr = <1>; */};
+	i2c0: i2c@f0220000 {  compatible = "nvt,nvt_i2c"; reg = <0xf0220000 0x100>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <1000000>; id = <0>; /*gsr = <2>;*/ /* tsr = <1>; */};
-	i2c1: i2c2@f0350000 { compatible = "nvt,nvt_i2c"; reg = <0xf0350000 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; id = <1>; /*gsr = <2>;*/ /* tsr = <1>; */};
+	i2c1: i2c2@f0350000 { compatible = "nvt,nvt_i2c"; reg = <0xf0350000 0x100>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <1000000>; id = <1>; /*gsr = <2>;*/ /* tsr = <1>; */};
 	i2c2: i2c3@f03a0000 { compatible = "nvt,nvt_i2c"; reg = <0xf03a0000 0x100>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <50000>; id = <2>; /*gsr = <2>;*/ /* tsr = <1>; */};
 };

configs/cfg_gen

@@ -1 +0,0 @@
-Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530

loader/.cproject

@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.786836233">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.786836233" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" description="" id="0.786836233" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.786836233." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1785085171" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1785085171.1068320500" name=""/>
+							<builder id="org.eclipse.cdt.build.core.settings.default.builder.2136169777" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1899091908" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1523619429" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.10253812" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.575176451" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1732809992" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.261651992" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.2084996330" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="na51089_loader_hunting.null.716610661" name="na51089_loader_hunting"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.786836233">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="0.250310382">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="0.1921625747">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>

loader/.project

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>na51089_loader_cardv</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

loader/Document/autodoc/BuildDoc.bat

@@ -0,0 +1,39 @@
+@echo off
+
+if not exist General.cfg (
+echo.
+echo -----------------------------------------------------------------
+echo Missing General.cfg
+echo -----------------------------------------------------------------
+echo.
+goto quit
+)
+
+call RemoveBuildDoc.bat
+
+echo.
+echo -----------------------------------------------------------------
+echo Start to build document
+echo -----------------------------------------------------------------
+echo.
+
+md Library
+md CHM
+
+if exist DriverDoc.cfg (
+doxygen DriverDoc.cfg
+)
+
+echo.
+echo -----------------------------------------------------------------
+echo Done.
+echo -----------------------------------------------------------------
+goto quit
+
+echo.
+echo -----------------------------------------------------------------
+echo Done.
+echo Go to Cygwin to run MakePDF.sh to create PDF version.
+echo -----------------------------------------------------------------
+
+:quit

loader/Document/autodoc/DoxygenLayout.xml

@@ -0,0 +1,185 @@
+<doxygenlayout version="1.0">
+  <!-- Navigation index tabs for HTML output -->
+  <navindex>
+    <tab type="mainpage" visible="yes" title=""/>
+    <tab type="pages" visible="yes" title="" intro=""/>
+    <tab type="modules" visible="yes" title="" intro=""/>
+    <tab type="namespaces" visible="yes" title="">
+      <tab type="namespaces" visible="yes" title="" intro=""/>
+      <tab type="namespacemembers" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="classes" visible="yes" title="">
+      <tab type="classes" visible="yes" title="" intro=""/>
+      <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/>
+      <tab type="hierarchy" visible="yes" title="" intro=""/>
+      <tab type="classmembers" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="files" visible="yes" title="">
+      <tab type="files" visible="yes" title="" intro=""/>
+      <tab type="globals" visible="yes" title="" intro=""/>
+    </tab>
+    <tab type="dirs" visible="yes" title="" intro=""/>
+    <tab type="examples" visible="yes" title="" intro=""/>
+  </navindex>
+
+  <!-- Layout definition for a class page -->
+  <class>
+    <briefdescription visible="yes"/>
+    <detaileddescription title=""/>
+    <includes visible="$SHOW_INCLUDE_FILES"/>
+    <inheritancegraph visible="$CLASS_GRAPH"/>
+    <collaborationgraph visible="$COLLABORATION_GRAPH"/>
+    <allmemberslink visible="yes"/>
+    <memberdecl>
+      <nestedclasses visible="yes" title=""/>
+      <publictypes title=""/>
+      <publicslots title=""/>
+      <signals title=""/>
+      <publicmethods title=""/>
+      <publicstaticmethods title=""/>
+      <publicattributes title=""/>
+      <publicstaticattributes title=""/>
+      <protectedtypes title=""/>
+      <protectedslots title=""/>
+      <protectedmethods title=""/>
+      <protectedstaticmethods title=""/>
+      <protectedattributes title=""/>
+      <protectedstaticattributes title=""/>
+      <packagetypes title=""/>
+      <packagemethods title=""/>
+      <packagestaticmethods title=""/>
+      <packageattributes title=""/>
+      <packagestaticattributes title=""/>
+      <properties title=""/>
+      <events title=""/>
+      <privatetypes title=""/>
+      <privateslots title=""/>
+      <privatemethods title=""/>
+      <privatestaticmethods title=""/>
+      <privateattributes title=""/>
+      <privatestaticattributes title=""/>
+      <friends title=""/>
+      <related title="" subtitle=""/>
+      <membergroups visible="yes"/>
+    </memberdecl>
+    <memberdef>
+      <typedefs title=""/>
+      <enums title=""/>
+      <constructors title=""/>
+      <functions title=""/>
+      <related title=""/>
+      <variables title=""/>
+      <properties title=""/>
+      <events title=""/>
+    </memberdef>
+    <usedfiles visible="$SHOW_USED_FILES"/>
+    <authorsection visible="yes"/>
+  </class>
+
+  <!-- Layout definition for a namespace page -->
+  <namespace>
+    <briefdescription visible="yes"/>
+    <detaileddescription title=""/>
+    <memberdecl>
+      <nestednamespaces visible="yes" title=""/>
+      <classes visible="yes" title=""/>
+      <typedefs title=""/>
+      <enums title=""/>
+      <functions title=""/>
+      <variables title=""/>
+      <membergroups visible="yes"/>
+    </memberdecl>
+    <memberdef>
+      <typedefs title=""/>
+      <enums title=""/>
+      <functions title=""/>
+      <variables title=""/>
+    </memberdef>
+    <authorsection visible="yes"/>
+  </namespace>
+
+  <!-- Layout definition for a file page -->
+  <file>
+    <briefdescription visible="yes"/>
+    <detaileddescription title=""/>
+    <includes visible="$SHOW_INCLUDE_FILES"/>
+    <includegraph visible="$INCLUDE_GRAPH"/>
+    <includedbygraph visible="$INCLUDED_BY_GRAPH"/>
+    <sourcelink visible="yes"/>
+    <memberdecl>
+      <classes visible="yes" title=""/>
+      <namespaces visible="yes" title=""/>
+      <defines title=""/>
+      <typedefs title=""/>
+      <enums title=""/>
+      <functions title=""/>
+      <variables title=""/>
+      <membergroups visible="yes"/>
+    </memberdecl>
+    <memberdef>
+      <defines title=""/>
+      <typedefs title=""/>
+      <enums title=""/>
+      <functions title=""/>
+      <variables title=""/>
+    </memberdef>
+    <authorsection/>
+  </file>
+
+  <!-- Layout definition for a group page -->
+  <group>
+    <briefdescription visible="yes"/>
+    <detaileddescription title=""/>
+    <groupgraph visible="$GROUP_GRAPHS"/>
+    <memberdecl>
+      <files visible="yes" title=""/>
+      <classes visible="yes" title=""/>
+      <namespaces visible="yes" title=""/>
+      <dirs visible="yes" title=""/>
+      <nestedgroups visible="yes" title=""/>
+      <defines title=""/>
+      <typedefs title=""/>
+      <enums title=""/>
+      <enumvalues title=""/>
+      <functions title=""/>
+      <variables title=""/>
+      <signals title=""/>
+      <publicslots title=""/>
+      <protectedslots title=""/>
+      <privateslots title=""/>
+      <events title=""/>
+      <properties title=""/>
+      <friends title=""/>
+      <membergroups visible="yes"/>
+    </memberdecl>
+    <memberdef>
+      <pagedocs/>
+      <inlineclasses title=""/>
+      <defines title=""/>
+      <typedefs title=""/>
+      <enums title=""/>
+      <enumvalues title=""/>
+      <functions title=""/>
+      <variables title=""/>
+      <signals title=""/>
+      <publicslots title=""/>
+      <protectedslots title=""/>
+      <privateslots title=""/>
+      <events title=""/>
+      <properties title=""/>
+      <friends title=""/>
+    </memberdef>
+    <authorsection visible="yes"/>
+  </group>
+
+  <!-- Layout definition for a directory page -->
+  <directory>
+    <briefdescription visible="yes"/>
+    <detaileddescription title=""/>
+    <directorygraph visible="yes"/>
+    <memberdecl>
+      <dirs visible="yes"/>
+      <files visible="yes"/>
+    </memberdecl>
+  </directory>
+</doxygenlayout>

loader/Document/autodoc/DriverDoc.cfg

@@ -0,0 +1,31 @@
+# Doxyfile 1.7.4
+
+@INCLUDE = General.cfg
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME           = "NT96650 SDK Loader Library"
+PROJECT_NUMBER         =
+OUTPUT_DIRECTORY       = ./Library/Loader
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+WARN_LOGFILE           = Log_DriverDoc.txt
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+INCLUDE_PATH           = ../../Include \
+                         ../../LIB/LIB_Src
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = ../../Include/Driver650 \
+                         ../../Include \
+                         ../../LIB/LIB_Src
+EXCLUDE                =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+# related to OUTPUT_DIRECTORY/html
+CHM_FILE               = "../../../CHM/NT96650 SDK Loader Library.chm"

loader/Document/autodoc/General.cfg

@@ -0,0 +1,330 @@
+# Doxyfile 1.7.4
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING      = UTF-8
+CREATE_SUBDIRS         = YES
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = NO
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 4
+ALIASES                =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = NO
+DISTRIBUTE_GROUP_DOC   = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+TYPEDEF_HIDES_STRUCT   = NO
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = NO
+EXTRACT_PRIVATE        = NO
+EXTRACT_STATIC         = NO
+EXTRACT_LOCAL_CLASSES  = NO
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = YES
+HIDE_UNDOC_CLASSES     = YES
+HIDE_FRIEND_COMPOUNDS  = YES
+HIDE_IN_BODY_DOCS      = YES
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = NO
+HIDE_SCOPE_NAMES       = NO
+SHOW_INCLUDE_FILES     = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = NO
+GENERATE_TESTLIST      = NO
+GENERATE_BUGLIST       = NO
+GENERATE_DEPRECATEDLIST= NO
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = NO
+SHOW_DIRECTORIES       = NO
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = NO
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            = DoxygenLayout.xml
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = NO
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_FORMAT            = "$file:$line: $text"
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.cpp \
+                         *.c++ \
+                         *.d \
+                         *.java \
+                         *.ii \
+                         *.ixx \
+                         *.ipp \
+                         *.i++ \
+                         *.inl \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++ \
+                         *.idl \
+                         *.odl \
+                         *.cs \
+                         *.php \
+                         *.php3 \
+                         *.inc \
+                         *.m \
+                         *.mm \
+                         *.dox \
+                         *.py \
+                         *.f90 \
+                         *.f \
+                         *.for \
+                         *.vhd \
+                         *.vhdl
+RECURSIVE              = YES
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       = *
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = NO
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION    = NO
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
+HTML_COLORSTYLE_GAMMA  = 80
+HTML_TIMESTAMP         = YES
+HTML_ALIGN_MEMBERS     = YES
+HTML_DYNAMIC_SECTIONS  = YES
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = YES
+#---------------------------------------------------------------------------
+# Set HHC_LOCATION to empty to disable chm file generation
+#---------------------------------------------------------------------------
+#HHC_LOCATION           =
+HHC_LOCATION           = "C:/Program Files/HTML Help Workshop/hhc.exe"
+GENERATE_CHI           = NO
+CHM_INDEX_ENCODING     =
+BINARY_TOC             = NO
+TOC_EXPAND             = YES
+GENERATE_QHP           = NO
+QCH_FILE               =
+QHP_NAMESPACE          = org.doxygen.Project
+QHP_VIRTUAL_FOLDER     = doc
+QHP_CUST_FILTER_NAME   =
+QHP_CUST_FILTER_ATTRS  =
+QHP_SECT_FILTER_ATTRS  =
+QHG_LOCATION           =
+GENERATE_ECLIPSEHELP   = NO
+ECLIPSE_DOC_ID         = org.doxygen.Project
+DISABLE_INDEX          = NO
+ENUM_VALUES_PER_LINE   = 0
+GENERATE_TREEVIEW      = YES
+USE_INLINE_TREES       = NO
+TREEVIEW_WIDTH         = 250
+EXT_LINKS_IN_WINDOW    = NO
+FORMULA_FONTSIZE       = 10
+FORMULA_TRANSPARENT    = YES
+USE_MATHJAX            = NO
+MATHJAX_RELPATH        = http://www.mathjax.org/mathjax
+SEARCHENGINE           = YES
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+LATEX_FOOTER           =
+PDF_HYPERLINKS         = YES
+USE_PDFLATEX           = YES
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_SCHEMA             =
+XML_DTD                =
+XML_PROGRAMLISTING     = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = NO
+EXPAND_ONLY_PREDEF     = NO
+SEARCH_INCLUDES        = YES
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             =
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+HIDE_UNDOC_RELATIONS   = YES
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = NO
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = NO
+CALLER_GRAPH           = NO
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = NO
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES

loader/Document/autodoc/RemoveBuildDoc.bat

@@ -0,0 +1,11 @@
+@echo off
+
+echo.
+echo -----------------------------------------------------------------
+echo Remove build directory
+echo -----------------------------------------------------------------
+echo.
+
+del Log_*.txt /f/q
+rd /s/q Library
+rd /s/q CHM

loader/Document/loader_build_option.txt

@@ -0,0 +1,73 @@
+.Loader package with
+├── admin
+│   ├─────────────────────────────In house auto build
+├── ARC
+│   └─────────────────────────────Library
+├── Document
+│   └─────────────────────────────Document
+├── Include
+├── LibExt
+│   ├── LIBExt_src
+│   │   └── Ctrl_Flow
+│   │       ├── bl_func.c ────────Main flow
+│   │       ├── bl_func.h
+│   │       ├── main.c
+│   │       ├── main.h
+│   │       └── Makefile
+│   └── Makefile
+├── MakeCommon
+│   ├── dump_tmp
+│   ├── InputSource.txt
+│   ├── make_combo_loader.sh────+─Build combination Loader(52x+528)<------------------------------------------------+
+│   ├── MakeCommon.txt			│																					|
+│   ├── Makefile				│																					|
+│   ├── MakeOption.txt			│																					|
+│   ├── OutputImg.txt			│																					|
+│   └── OutputLib.txt			│																					|
+├── output<─────────────────────└───>Combination loader will copy here												|
+│																													|
+├── Project																											|
+│   └── Model																										|
+│       ├── Debug_R.bat																								|
+│       ├── IceMode_R.bat																							|
+│       ├── IceMode.ttl																								|
+│       ├── init.gdb																								|
+│       ├── init_IceMode.gdb																						|
+│       ├── LDS_LZ_528.lds																							|
+│       ├── LDS_LZ.lds																								|
+│       ├── LDS_NM.lds																								|
+│       ├── LoadCode.ttl																							|
+│       ├── MakeConfig.txt																							|
+│       ├── Makefile																								|
+│		│																											|
+│       ├── ModelConfig_EMU_EVB_528.txt──────────────────────────────────(2)[CHIP=528's configuration]				|
+│       ├── ModelConfig_EMU_EVB.txt ─────────────────────────────────────(1)[CHIP=52x's configuration]				|
+│		│																											|
+│       ├── ModelConfig.txt───────────Choose which model want to build(1) or (2) <<<<<								|
+│		│			├─────────────────> MODEL = EMU_EVB ─────────(1)												|
+│		│  			└─────────────────> MODEL = EMU_EVB_528 ─────(2)												|
+│		│								└─>After choose -> entry MakeCommon folder 									|
+│		│								└─>type -> make release or ---use shell script to generate combo loader-----+
+│       ├── Run_R.bat
+│       └── Src
+│           ├── prj_main.c
+│           └── prj_main.h
+├── sdk-maker.sh
+├── Tools
+│   ├── Bin
+│   └── ConfigRam────────────────────Dram parameter
+
+Example
+1. Compiler stand-alone loader 52x	-----------------------------------------------------> Configuration [1]
+	[1]. ModelConfig.txt ----> MODEL = EMU_EVB
+	[2]. Modify configuration of CHIP 52x @ ModelConfig_EMU_EVB.txt──────────────────────────────────────(1)
+	[3]. Entry MakeCommon folder and type >>> make release
+
+2. Compiler stand-alone loader 528  -----------------------------------------------------> Configuration [2]
+	[1]. ModelConfig.txt ----> MODEL = EMU_EVB_528
+	[2]. Modify configuration of CHIP 528 @ ModelConfig_EMU_EVB_528.txt──────────────────────────────────(2)
+	[3]. Entry MakeCommon folder and type >>> make release
+
+3. Compiler combination loader 52x + 528
+	[1]. Configured chip 52x & 528 respectively.(Configuration [1] & Configuration [2] for example
+	[2]. Entry MakeCommon folder and type > ./make_combo_loader.sh  -> choose 3(make combo loader)

loader/History.txt

@@ -0,0 +1,14 @@
+I. History
+(+) -> New
+(*) -> Modified
+(@) -> TODO(wait to find out)
+[2021/06/02]
+    (+) Add exFAT ON/OFF option configure at ModelConfig_EMU.txt(default OFF)
+    
+[2018/03/30]
+	(+) Add L2 cache operation
+	
+[2018/03/23]
+    (+) Add 1st loader for NT98520, 
+	(-) rename of makefile to _Makefile for temporarily disable(eMMC/usb/ethernet)
+

loader/Include/CMacro.h

@@ -0,0 +1,35 @@
+/*++
+
+Copyright (c) 2005  Novatek Microelectronics Corporation
+
+Module Name:
+    StdCMac.h
+
+Abstract:
+    Standard C Macros for shared header file of ARM ASM and C
+    You should include this file first and then include the shared header file
+    For more information, please refer to http://www.arm.com/support/faqdev/1208.html
+
+Environment:
+    For nt96610
+
+Notes:
+    Copyright (c) 2005 Novatek Microelectronics Corporation.  All Rights Reserved.
+
+Revision History:
+    ??/??/??: Created by ARM
+    03/17/05: Modify by Chris Hsu for NT96610 uITRON project
+--*/
+
+#ifndef __C_MACRO_H
+#define __C_MACRO_H
+
+
+/* Comment */
+#define COMMENT
+
+/* end */
+#define END
+
+#endif  // __C_MACRO_H
+

loader/Include/Driver/CC.h

@@ -0,0 +1,41 @@
+/**
+    Header file for CC (Core Communicator) module.
+
+    This file is the header file that define the API and data type
+    for CC module.
+
+    @file       CC.h
+    @ingroup    mIDrvSys_CC
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2015.  All rights reserved.
+*/
+
+#ifndef _CC_H
+#define _CC_H
+
+#define ENUM_DUMMY4WORD(name)   E_##name = 0x10000000
+
+#define CC_CORE_CA53_CORE1  0
+#define CC_CORE_CA53_CORE2  1
+#define CC_CORE_DSP         2
+#define CC_CORE_DSP2        3
+
+typedef enum
+{
+    DMA_ID_1,                           ///< DMA Controller
+    DMA_ID_2,                           ///< DMA Controller 2
+
+    DMA_ID_COUNT,                       //< DMA controller count
+
+    ENUM_DUMMY4WORD(DMA_ID)
+} DMA_ID;
+
+extern void     cc_setCore2Base(UINT32 uiBaseAddr);
+extern ER       cc_startCore(UINT32 uiCoreID);
+extern void     cc_stopCore(UINT32 uiCoreID);
+extern UINT32 	dma_get_dram_capacity(DMA_ID id);
+
+
+
+#endif

loader/Include/Driver/Cache.h

@@ -0,0 +1,511 @@
+/**
+    CPU module driver.
+
+    This file is the driver of CPU module.
+
+    @file       Cache.h
+    @ingroup    mIHALCore
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2005.  All rights reserved.
+*/
+
+#ifndef _CACHE_H
+#define _CACHE_H
+#include "constant.h"
+
+
+/*
+     csselrcache level & type selection
+
+     Detailed reference to [trm p4-177 CSSELR]
+*/
+typedef enum _CACHE_LV_TYPE_
+{
+    LEVEL_1_DCACHE = 0x0,   //< Level 1 data cache
+    LEVEL_1_ICACHE,         //< Level 1 instruction cache
+    LEVEL_2_DCACHE,         //< Level 2 data cache
+} CACHE_LV_TYPE;
+
+
+/*
+     Values for Ctype fields in CLIDR
+*/
+
+typedef enum _CLIDR_CTYPE_
+{
+    CLIDR_CTYPE_NO_CACHE        = 0x0,
+    CLIDR_CTYPE_INSTRUCTION_ONLY= 0x1,
+    CLIDR_CTYPE_DATA_ONLY       = 0x2,
+    CLIDR_CTYPE_INSTRUCTION_DATA= 0x3,
+    CLIDR_CTYPE_UNIFIED         = 0x4,
+}CLIDR_CTYPE;
+
+
+//Instruction Synchronization Barrier.
+#define _ISB() \
+	__asm__ __volatile__("isb\n\t")
+
+//Data Synchronization Barrier
+#define _DSB() \
+	__asm__ __volatile__("dsb\n\t")
+
+//Data Memory Barrier
+#define _DMB() \
+	__asm__ __volatile__("dmb\n\t")
+
+
+/*
+ ************************************************************************
+ *    		Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0)       	*
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |W|W|R|W|NumSets			 			 |Associativity      |L    |
+ * |T|B|A|A|                             |                   |S    |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_DC_SETS	8
+#define S_DC_W		2
+#define S_DC_LS		5
+
+#define _DC_SETS	(1 << S_DC_SETS)	/* 256 sets */
+#define _DC_W 		(1 << S_DC_W)		/* 4 way */
+#define _DC_LS 		(1 << S_DC_LS)		/* 32 byte line size */
+
+#define S_IC_SETS	8
+#define S_IC_W		2
+#define S_IC_LS		5
+
+#define _IC_SETS	(1 << S_IC_SETS)	/* 256 sets */
+#define _IC_W 		(1 << S_IC_W)		/* 4 way */
+#define _IC_LS 		(1 << S_IC_LS)		/* 32 byte line size */
+
+#define S_DC_W_L2	4                   /* L2 way shift*/
+
+#define S_SC_SETS	9
+#define S_SC_W		3
+#define S_SC_LS		5
+
+#define _SC_SETS	(1 << S_SC_SETS)	/* 512 sets */
+#define _SC_W 		(1 << S_SC_W)		/* 8 way */
+#define _SC_LS 		(1 << S_SC_LS)		/* 32 byte line size */
+
+
+#define S_CCSIDR_WT		31
+#define M_CCSIDR_WT		(0x1  << S_CCSIDR_WT)		/* Support write-through */
+#define S_CCSIDR_WB		30
+#define M_CCSIDR_WB		(0x1  << S_CCSIDR_WB)		/* Support write-back */
+#define S_CCSIDR_RA		29
+#define M_CCSIDR_RA		(0x1  << S_CCSIDR_RA)		/* Support read-allocation */
+#define S_CCSIDR_WA		28
+#define M_CCSIDR_WA		(0x1  << S_CCSIDR_WA)		/* Support write-allocation */
+#define S_CCSIDR_SETS	13
+#define M_CCSIDR_SETS	(0x7fff  << S_CCSIDR_SETS)	/* Number of sets */
+#define S_CCSIDR_A		3
+#define M_CCSIDR_A		(0x3ff  << S_CCSIDR_A)		/* Number of associatiovity */
+#define S_CCSIDR_LS		0
+#define M_CCSIDR_LS		(0x7  << S_CCSIDR_LS)		/* Cache line size */
+
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+#define SCTLR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__( \
+		 "mrc p15, 0, %0, c1, c0, 0\n\t" \
+		 : "=r" (val)); \
+	 val; \
+	 })
+
+#define LEVEL_1 (1 - 1)
+#define LEVEL_2 (2 - 1)
+
+#define CCSIDR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__( \
+		 "mrc p15, 1, %0, c0, c0, 0\n\t" \
+		 : "=r" (val)); \
+	 val; \
+	 })
+
+
+#define sel_CSSELR(InD) \
+	__asm__ __volatile__(	\
+			"mcr p15, 2, %0, c0, c0, 0\n\t" \
+			: \
+			: "r"(InD));
+
+#define _ICACHE_INV_ALL() _ICIALLU() \
+                        _BPIALL()
+
+/*
+    ICIALLU, Instruction Cache Invalidate All to PoU
+    The ICIALLU characteristics are:
+
+        Invalidate all instruction caches to PoU. If branch predictors are
+        architecturally visible, also flush branch predictors.
+
+        This register is part of the Cache maintenance instructions functional group.
+
+    Usage constraints
+    If EL3 is implemented and is using AArch32, this operation can be performed at the following
+    exception levels:
+*/
+#define _ICIALLU() \
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+
+/*
+    Branch Predictor Invalidate All
+    The BPIALL characteristics are:
+
+        Invalidate all entries from branch predictors.
+        This register is part of the Cache maintenance instructions functional group.
+    Usage constraints
+    If EL3 is implemented and is using AArch32, this operation can be performed at the following
+    exception levels:
+*/
+#define _BPIALL() \
+    __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+
+
+/*
+     ICIMVAU : Instruction Cache line Invalidate by VA to PoU
+*/
+#define _ICACHE_INV_MVAU(addr) _ICIMVAU(addr)
+#define _ICIMVAU(addr) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7, c5, 1\n\t" \
+			: \
+			: "r"(addr));
+
+#define _DCACHE_INV_MVAC(addr) _DCIMVAC(addr)
+#define _DCIMVAC(addr) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7, c6, 1\n\t" \
+			: \
+			: "r"(addr));
+
+//DCCMVAC Clean data cache line by VA to PoC
+#define _DCACHE_WBACK_MVAC(addr) _DCCMVAC(addr)
+#define _DCCMVAC(addr) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7, c10, 1\n\t" \
+			: \
+			: "r"(addr));
+
+//_DCCIMVAC Clean and invalidate data cache line by VA to PoC
+#define _DCACHE_WBACK_INV_MVAC(addr) _DCCIMVAC(addr)
+#define _DCCIMVAC(addr) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7, c14, 1\n\t" \
+			: \
+			: "r"(addr));
+
+//DCCISW Clean and invalidate data cache line by set/way
+#define _DCCISW(way_set) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7 ,c14, 2\n\t"  \
+			:	\
+			: "r"(way_set));
+
+//DCISW Invalidate data cache line by set/way
+/*
+    The DCISW input value bit assignments are:
+
+    |31......................4 | 3...1 | 0 |
+     Setway                      level  rsv
+     bit[3..1] = 0x0 = Level 1
+     bit[3..1] = 0x1 = Level 2
+     ...
+*/
+#define _DCISW(way_set) \
+	__asm__ __volatile__(	\
+			"mcr p15, 0, %0, c7 ,c6, 2\n\t"  \
+			:	\
+			: "r"(way_set));
+
+
+//DCCSW Clean data cache line by set/way
+/*
+    The DCCSW input value bit assignments are:
+
+    |31......................4 | 3...1 | 0 |
+     Setway                      level  rsv
+     bit[3..1] = 0x0 = Level 1
+     bit[3..1] = 0x1 = Level 2
+     ...
+*/
+#define _DCCSW(way_set) \
+	__asm__ __volatile__(   \
+							"mcr p15, 0, %0, c7 ,c10, 2\n\t"  \
+							:   \
+							: "r"(way_set))
+
+
+
+
+/* Cache dirty register () */
+#define read_CDSR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__(\
+		 "mrc p15, 0, %0, c7, c10, 6\n\t" \
+		 : "=r"(val) \
+		 );\
+	 val;\
+	 })
+
+/* Get CPU ID */
+#define read_MPIDR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__(\
+		 "mrc p15, 0, %0, c0, c0, 5\n\t" \
+		 : "=r"(val) \
+		 );\
+	 val;\
+	 })
+
+/* ead current CP15 Cache Level ID Register */
+#define read_CLIDR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__(\
+		 "mrc p15, 1, %0, c0, c0, 1\n\t" \
+		 : "=r"(val) \
+		 );\
+	 val;\
+	 })
+
+#define change_property() \
+	({ \
+	 __asm__ __volatile__( \
+		 ".arch_extension sec\n\t" \
+		 "smc #123\n\t" \
+		 : \
+		 : \
+		 ); \
+	 })
+
+#define CLEAR_MMU()	\
+	__asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0\n\t");
+
+
+#define DISABLE_MMU()	\
+   ({ \
+	 unsigned long val = 0; \
+	__asm__ __volatile__( \
+		"mrc p15, 0, %0, c1, c0, 0\n\t" \
+		"bic %0, %0, #0x1\n\t" \
+		"mcr p15, 0, %0, c1, c0, 0\n\t" \
+		: \
+		: "r" (val) \
+		); \
+	})
+
+#define DISABLE_DCACHE()	\
+   ({ \
+	 unsigned long val = 0; \
+	__asm__ __volatile__( \
+		"mrc p15, 0, %0, c1, c0, 0\n\t" \
+		"bic %0, %0, #0x4\n\t" \
+		"mcr p15, 0, %0, c1, c0, 0\n\t" \
+		: \
+		: "r" (val) \
+		); \
+	})
+
+#define DISABLE_ICACHE()	\
+   ({ \
+	 unsigned long val = 0; \
+	__asm__ __volatile__( \
+		"mrc p15, 0, %0, c1, c0, 0\n\t" \
+		"bic %0, %0, #0x1000\n\t" \
+		"mcr p15, 0, %0, c1, c0, 0\n\t" \
+		: \
+		: "r" (val) \
+		); \
+	})
+
+#define SETUP_TTBR0(val)	\
+	({	\
+	 __asm__ __volatile__(	\
+		 "mcr p15, 0, %0, c2, c0, 0\n\t"	\
+		 : \
+		 :	"r" (val) \
+		 ); \
+	 })
+/* Cache dirty register () */
+#define read_CDSR() \
+	({ \
+	 unsigned long val; \
+	 __asm__ __volatile__(\
+		 "mrc p15, 0, %0, c7, c10, 6\n\t" \
+		 : "=r"(val) \
+		 );\
+	 val;\
+	 })
+/**
+    @addtogroup mIHALCore
+*/
+//@{
+
+/**
+    @name CPU clean invalidate all DCache
+
+    Clean and invalidate all data cache
+
+    @return void
+*/
+//@{
+#define CPUCleanInvalidateDCacheAll()       cpu_cleanInvalidateDCacheAll()          ///< clean invalidate all DCache
+//@}
+
+/**
+    @name CPU clean invalidate DCache
+
+    Clean and invalidate data cache
+    Cache line associated with input address will be clean and invalidated
+
+    @param[in] addr     data address to be clean and invalidated
+
+    @return void
+*/
+//@{
+#define CPUCleanInvalidateDCache(addr)      cpu_cleanInvalidateDCache(addr)         ///< clean invalidate DCache
+//@}
+
+/**
+    @name CPU clean invalidate DCache block
+
+    Clean and invalidate data cache block
+    Cache line associated with input region will be clean and invalidated
+
+    @param[in] m        starting data address to be clean and invalidated
+    @param[in] n        end data address to be clean and invalidated
+
+    @return void
+*/
+//@{
+#define CPUCleanInvalidateDCacheBlock(m,n)  cpu_cleanInvalidateDCacheBlock(m, n)    ///< clean invalidate DCache block
+//@}
+
+/**
+    @name CPU invalidate DCache
+
+    Invalidate data cache
+    Cache line associated with input address will be invalidated
+
+    @param[in] addr     data address to be invalidated
+
+    @return void
+*/
+//@{
+#define CPUInvalidateDCache(m)              cpu_invalidateDCache(m)                 ///< invalidate DCache
+//@}
+
+/**
+    @name CPU invalidate DCache block
+
+    Invalidate data cache block
+    Cache line associated with input region will be invalidated
+
+    @param[in] m        starting data address to be invalidated
+    @param[in] n        end data address to be invalidated
+
+    @return void
+*/
+//@{
+#define CPUInvalidateDCacheBlock(m,n)       cpu_invalidateDCacheBlock(m,n)          ///< invalidate DCache block
+//@}
+
+/**
+    @name CPU clean DCache
+
+    Clean data cache
+    Cache line associated with input address will be clean
+
+    @param[in] addr     data address to be clean
+
+    @return void
+*/
+//@{
+#define CPUCleanDCache(m)                   cpu_cleanDCache(m)                      ///< clean DCache
+//@}
+
+/**
+    @name CPU clean DCache block
+
+    Clean data cache block
+    Cache line associated with input region will be clean
+
+    @param[in] m        starting data address to be clean
+    @param[in] n        end data address to be clean
+
+    @return void
+*/
+//@{
+#define CPUCleanDCacheBlock(m, n)           cpu_cleanDCacheBlock(m, n)              ///< clean DCache block
+//@}
+
+/**
+    @name CPU invalidate all DCache
+
+    Invalidate all data cache
+
+    @return void
+*/
+//@{
+#define CPUInvalidateDCacheAll()            cpu_invalidateDCacheAll()               ///< invalidate all DCache
+//@}
+
+
+extern BOOL     CPUChkDCacheEnabled(UINT32 addr);
+extern void     CPUInvalidateICacheAll(void) __attribute__ ((section (".part1")));
+//extern void     CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"), far));
+//extern void     CPUInvalidateICache(UINT32 addr);
+extern void     CPUInvalidateICacheBlock(UINT32 start, UINT32 end);
+
+#if 0
+extern void     CPUInvalidateDCacheAll(void);
+extern void     CPUInvalidateDCache(UINT32 addr);
+extern void     CPUInvalidateDCacheBlock(UINT32 start, UINT32 end);
+#endif
+extern void     cpu_invalidateDCacheBlock(UINT32 start, UINT32 end);
+extern void     cpu_invalidateDCache(UINT32 addr);
+extern void     cpu_invalidateDCacheAll(void)__attribute__ ((section (".part1")));
+extern void     cpu_cleanDCache(UINT32 addr);
+extern void     cpu_cleanDCacheBlock(UINT32 start, UINT32 end);
+extern void     _cache_clean_d_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1")));
+extern void     _cache_invalidate_data_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1")));
+extern void     _cache_clean_invalidate_d_cache_All(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1")));
+
+
+
+extern void     cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1")));
+//extern void     cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"), far));
+extern void     cpu_cleanInvalidateDCache(UINT32 addr);
+extern void     cpu_cleanInvalidateDCacheBlock(UINT32 start, UINT32 end);
+
+extern void     CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength);
+extern void     CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength);
+
+
+
+#endif
+
+//@}

loader/Include/Driver/Clock.h

@@ -0,0 +1,26 @@
+/**
+    System Clock APIs header file
+
+    System Clock APIs header.
+
+    @file       clock.h
+    @ingroup    mIHALSysCG
+    @note       Nothing
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef __CLOCK_H
+#define __CLOCK_H
+
+#include "IOReg.h"
+
+/** \addtogroup mIHALSysCG */
+//@{
+
+
+
+
+//@}
+
+#endif  // __CLOCK_H

loader/Include/Driver/GPIO.h

@@ -0,0 +1,316 @@
+/**
+    General Purpose I/O controller header file
+
+    General Purpose I/O controller header file
+
+    @file       GPIO.h
+    @ingroup    mIIOGPIO
+    @note       Nothing
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _GPIO_H
+#define _GPIO_H
+
+#include "IOReg.h"
+
+#define ENUM_DUMMY4WORD(name)   E_##name = 0x10000000
+
+/**
+    @addtogroup mIDrvIO_GPIO
+*/
+//@{
+
+/**
+    GPIO direction
+
+    GPIO direction definition for gpio_setDir() and gpio_getDir()
+*/
+typedef enum {
+	GPIO_DIR_INPUT =            0,      ///< GPIO is input direction
+	GPIO_DIR_OUTPUT =           1,      ///< GPIO is output direction
+
+	ENUM_DUMMY4WORD(GPIO_DIR)
+} GPIO_DIR;
+
+/**
+    GPIO interrupt type
+
+    GPIO interrupt type definition for type argument of gpio_setIntTypePol()
+*/
+typedef enum {
+	GPIO_INTTYPE_EDGE =         0,      ///< GPIO interrupt is edge trigger
+	GPIO_INTTYPE_LEVEL =        1,      ///< GPIO interrupt is level trigger
+
+	ENUM_DUMMY4WORD(GPIO_INTTYPE)
+} GPIO_INTTYPE;
+
+/**
+    GPIO interrupt polarity
+
+    GPIO interrupt polarity definition for pol argument of gpio_setIntTypePol()
+*/
+typedef enum {
+	GPIO_INTPOL_POSHIGH =       0,      ///< GPIO interrupt polarity is \n
+	///< - @b positvie edge for edge trigger
+	///< - @b high level for level trigger
+	GPIO_INTPOL_NEGLOW =        1,      ///< GPIO interrupt polarity is \n
+	///< - @b negative edge for edge trigger
+	///< - @b low level for level trigger
+	GPIO_INTPOL_BOTHEDGE =      2,      ///< GPIO interrupt polarity is \n
+	///< - @b both edge for edge trigger
+	ENUM_DUMMY4WORD(GPIO_INTPOL)
+} GPIO_INTPOL;
+
+
+
+/**
+    @name   GPIO pins ID
+
+    GPIO pins ID definition
+
+    For detail GPIO pin out, please refer to NT96520 data sheet.
+*/
+//@{
+/*Storage GPIO - CGPIO*/
+#define C_GPIO_0    0                       ///< C_GPIO[0]
+#define C_GPIO_1    1                       ///< C_GPIO[1]
+#define C_GPIO_2    2                       ///< C_GPIO[2]
+#define C_GPIO_3    3                       ///< C_GPIO[3]
+#define C_GPIO_4    4                       ///< C_GPIO[4]
+#define C_GPIO_5    5                       ///< C_GPIO[5]
+#define C_GPIO_6    6                       ///< C_GPIO[6]
+#define C_GPIO_7    7                       ///< C_GPIO[7]
+#define C_GPIO_8    8                       ///< C_GPIO[8]
+#define C_GPIO_9    9                       ///< C_GPIO[9]
+#define C_GPIO_10   10                      ///< C_GPIO[10]
+#define C_GPIO_11   11                      ///< C_GPIO[11]
+#define C_GPIO_12   12                      ///< C_GPIO[12]
+#define C_GPIO_13   13                      ///< C_GPIO[13]
+#define C_GPIO_14   14                      ///< C_GPIO[14]
+#define C_GPIO_15   15                      ///< C_GPIO[15]
+#define C_GPIO_16   16                      ///< C_GPIO[16]
+#define C_GPIO_17   17                      ///< C_GPIO[17]
+#define C_GPIO_18   18                      ///< C_GPIO[18]
+#define C_GPIO_19   19                      ///< C_GPIO[19]
+#define C_GPIO_20   20                      ///< C_GPIO[20]
+#define C_GPIO_21   21                      ///< C_GPIO[21]
+#define C_GPIO_22   22                      ///< C_GPIO[22]
+
+/*Peripheral GPIO - PGPIO*/
+#define P_GPIO_SHIFT_BASE 32
+#define P_GPIO_0    (0 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[0]
+#define P_GPIO_1    (1 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[1]
+#define P_GPIO_2    (2 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[2]
+#define P_GPIO_3    (3 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[3]
+#define P_GPIO_4    (4 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[4]
+#define P_GPIO_5    (5 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[5]
+#define P_GPIO_6    (6 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[6]
+#define P_GPIO_7    (7 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[7]
+#define P_GPIO_8    (8 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[8]
+#define P_GPIO_9    (9 +P_GPIO_SHIFT_BASE)  ///< P_GPIO[9]
+#define P_GPIO_10   (10+P_GPIO_SHIFT_BASE)  ///< P_GPIO[10]
+#define P_GPIO_11   (11+P_GPIO_SHIFT_BASE)  ///< P_GPIO[11]
+#define P_GPIO_12   (12+P_GPIO_SHIFT_BASE)  ///< P_GPIO[12]
+#define P_GPIO_13   (13+P_GPIO_SHIFT_BASE)  ///< P_GPIO[13]
+#define P_GPIO_14   (14+P_GPIO_SHIFT_BASE)  ///< P_GPIO[14]
+#define P_GPIO_15   (15+P_GPIO_SHIFT_BASE)  ///< P_GPIO[15]
+#define P_GPIO_16   (16+P_GPIO_SHIFT_BASE)  ///< P_GPIO[16]
+#define P_GPIO_17   (17+P_GPIO_SHIFT_BASE)  ///< P_GPIO[17]
+#define P_GPIO_18   (18+P_GPIO_SHIFT_BASE)  ///< P_GPIO[18]
+#define P_GPIO_19   (19+P_GPIO_SHIFT_BASE)  ///< P_GPIO[19]
+#define P_GPIO_20   (20+P_GPIO_SHIFT_BASE)  ///< P_GPIO[20]
+#define P_GPIO_21   (21+P_GPIO_SHIFT_BASE)  ///< P_GPIO[21]
+#define P_GPIO_22   (22+P_GPIO_SHIFT_BASE)  ///< P_GPIO[22]
+#define P_GPIO_23   (23+P_GPIO_SHIFT_BASE)  ///< P_GPIO[23]
+#define P_GPIO_24   (24+P_GPIO_SHIFT_BASE)  ///< P_GPIO[24]
+#define P_GPIO_25   (25+P_GPIO_SHIFT_BASE)  ///< P_GPIO[25]
+
+/*Sensor GPIO - SGPIO*/
+#define S_GPIO_SHIFT_BASE 64
+#define S_GPIO_0    (0 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[0]
+#define S_GPIO_1    (1 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[1]
+#define S_GPIO_2    (2 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[2]
+#define S_GPIO_3    (3 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[3]
+#define S_GPIO_4    (4 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[4]
+#define S_GPIO_5    (5 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[5]
+#define S_GPIO_6    (6 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[6]
+#define S_GPIO_7    (7 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[7]
+#define S_GPIO_8    (8 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[8]
+#define S_GPIO_9    (9 +S_GPIO_SHIFT_BASE)  ///< S_GPIO[9]
+#define S_GPIO_10   (10+S_GPIO_SHIFT_BASE)  ///< S_GPIO[10]
+#define S_GPIO_11   (11+S_GPIO_SHIFT_BASE)  ///< S_GPIO[11]
+#define S_GPIO_12   (12+S_GPIO_SHIFT_BASE)  ///< S_GPIO[11]
+
+
+/*LCD GPIO - LGPIO*/
+#define L_GPIO_SHIFT_BASE 96
+#define L_GPIO_0    (0 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[0]
+#define L_GPIO_1    (1 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[1]
+#define L_GPIO_2    (2 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[2]
+#define L_GPIO_3    (3 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[3]
+#define L_GPIO_4    (4 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[4]
+#define L_GPIO_5    (5 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[5]
+#define L_GPIO_6    (6 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[6]
+#define L_GPIO_7    (7 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[7]
+#define L_GPIO_8    (8 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[8]
+#define L_GPIO_9    (9 +L_GPIO_SHIFT_BASE)  ///< L_GPIO[9]
+#define L_GPIO_10   (10+L_GPIO_SHIFT_BASE)  ///< L_GPIO[10]
+#define L_GPIO_11   (11+L_GPIO_SHIFT_BASE)  ///< L_GPIO[11]
+#define L_GPIO_12   (12+L_GPIO_SHIFT_BASE)  ///< L_GPIO[12]
+#define L_GPIO_13   (13+L_GPIO_SHIFT_BASE)  ///< L_GPIO[13]
+#define L_GPIO_14   (14+L_GPIO_SHIFT_BASE)  ///< L_GPIO[14]
+#define L_GPIO_15   (15+L_GPIO_SHIFT_BASE)  ///< L_GPIO[15]
+#define L_GPIO_16   (16+L_GPIO_SHIFT_BASE)  ///< L_GPIO[16]
+#define L_GPIO_17   (17+L_GPIO_SHIFT_BASE)  ///< L_GPIO[17]
+#define L_GPIO_18   (18+L_GPIO_SHIFT_BASE)  ///< L_GPIO[18]
+#define L_GPIO_19   (19+L_GPIO_SHIFT_BASE)  ///< L_GPIO[19]
+#define L_GPIO_20   (20+L_GPIO_SHIFT_BASE)  ///< L_GPIO[20]
+#define L_GPIO_21   (21+L_GPIO_SHIFT_BASE)  ///< L_GPIO[21]
+#define L_GPIO_22   (22+L_GPIO_SHIFT_BASE)  ///< L_GPIO[22]
+#define L_GPIO_23   (23+L_GPIO_SHIFT_BASE)  ///< L_GPIO[23]
+#define L_GPIO_24   (24+L_GPIO_SHIFT_BASE)  ///< L_GPIO[24]
+
+/*Dedicated GPIO - DGPIO*/
+// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* "
+#define D_GPIO_SHIFT_BASE 128
+#define D_GPIO_0    (0 +D_GPIO_SHIFT_BASE)  ///< DGPIO[0]
+#define D_GPIO_1    (1 +D_GPIO_SHIFT_BASE)  ///< DGPIO[1]
+#define D_GPIO_2    (2 +D_GPIO_SHIFT_BASE)  ///< DGPIO[2]
+#define D_GPIO_3    (3 +D_GPIO_SHIFT_BASE)  ///< DGPIO[3]
+#define D_GPIO_4    (4 +D_GPIO_SHIFT_BASE)  ///< DGPIO[4]
+#define D_GPIO_5    (5 +D_GPIO_SHIFT_BASE)  ///< DGPIO[5]
+#define D_GPIO_6    (6 +D_GPIO_SHIFT_BASE)  ///< DGPIO[6]
+#define D_GPIO_7    (7 +D_GPIO_SHIFT_BASE)  ///< DGPIO[7]
+#define D_GPIO_8    (8 +D_GPIO_SHIFT_BASE)  ///< DGPIO[8]
+#define D_GPIO_9    (9 +D_GPIO_SHIFT_BASE)  ///< DGPIO[9]
+#define D_GPIO_10   (10+D_GPIO_SHIFT_BASE)  ///< DGPIO[10]
+
+#define D_GPIO_16   (16 +D_GPIO_SHIFT_BASE) ///< D_GPIO[16] (USB Wakeup) (No pad instance)
+
+/*GPIO HSI Data register(High speed interface)*/
+#define H_GPIO_SHIFT_BASE 160
+#define H_GPIO_0    (0 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[0]
+#define H_GPIO_1    (1 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[1]
+#define H_GPIO_2    (2 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[2]
+#define H_GPIO_3    (3 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[3]
+#define H_GPIO_4    (4 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[4]
+#define H_GPIO_5    (5 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[5]
+#define H_GPIO_6    (6 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[6]
+#define H_GPIO_7    (7 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[7]
+#define H_GPIO_8    (8 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[8]
+#define H_GPIO_9    (9 +H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[9]
+#define H_GPIO_10   (10+H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[10]
+#define H_GPIO_11   (11+H_GPIO_SHIFT_BASE)  ///< HSI_GPIO[11]
+
+/*GPIO ADC Data register*/
+#define A_GPI_SHIFT_BASE 192
+#define A_GPIO_0    (0 + A_GPI_SHIFT_BASE)  ///< A_GPIO[0]
+#define A_GPIO_1    (1 + A_GPI_SHIFT_BASE)  ///< A_GPIO[1]
+#define A_GPIO_2    (2 + A_GPI_SHIFT_BASE)  ///< A_GPIO[2]
+
+#define DSI_GPIO_2  0xE2
+
+//@}
+
+/*For temporary usage as passing build codes*/
+#define C_GPIO_23   23
+#define C_GPIO_24   24
+#define C_GPIO_25   25
+#define C_GPIO_26   26
+#define C_GPIO_27   27
+#define C_GPIO_28   28
+#define C_GPIO_29   29
+#define C_GPIO_30   30
+#define C_GPIO_31   31
+#define C_GPIO_32   32
+#define C_GPIO_33   33
+#define L_GPIO_30   (30+L_GPIO_SHIFT_BASE)
+#define L_GPIO_31   (31+L_GPIO_SHIFT_BASE)
+#define L_GPIO_32   (32+L_GPIO_SHIFT_BASE)
+#define GPIO_INT_USBPLUGIN (GPIO_INT_39)
+
+
+
+
+/**
+    @name   GPIO Interrupt ID
+
+    GPIO interrupt ID definition
+
+    GPIO interrupt ID for interrupt related APIs.
+*/
+//@{
+#define GPIO_INT_00                 0       ///< GPIO INT[0]:   C_GPIO[3]
+#define GPIO_INT_01                 1       ///< GPIO INT[1]:   C_GPIO[5]
+#define GPIO_INT_02                 2       ///< GPIO INT[2]:   C_GPIO[7]
+#define GPIO_INT_03                 3       ///< GPIO INT[3]:   C_GPIO[9]
+#define GPIO_INT_04                 4       ///< GPIO INT[4]:   C_GPIO[12]
+#define GPIO_INT_05                 5       ///< GPIO INT[5]:   C_GPIO[14]
+#define GPIO_INT_06                 6       ///< GPIO INT[6]:   C_GPIO[16]
+#define GPIO_INT_07                 7       ///< GPIO INT[7]:   C_GPIO[18]
+#define GPIO_INT_08                 8       ///< GPIO INT[8]:   C_GPIO[20]
+#define GPIO_INT_09                 9       ///< GPIO INT[9]:   C_GPIO[22]
+#define GPIO_INT_10                 10      ///< GPIO INT[10]:  H_GPIO[0]
+#define GPIO_INT_11                 11      ///< GPIO INT[11]:  H_GPIO[11]
+#define GPIO_INT_12                 12      ///< GPIO INT[12]:  S_GPIO[1]
+#define GPIO_INT_13                 13      ///< GPIO INT[13]:  S_GPIO[4]
+#define GPIO_INT_14                 14      ///< GPIO INT[14]:  S_GPIO[6]
+#define GPIO_INT_15                 15      ///< GPIO INT[15]:  S_GPIO[10]
+#define GPIO_INT_16                 16      ///< GPIO INT[16]:  S_GPIO[12]
+#define GPIO_INT_17                 17      ///< GPIO INT[17]:  P_GPIO[3]
+#define GPIO_INT_18                 18      ///< GPIO INT[18]:  P_GPIO[7]
+#define GPIO_INT_19                 19      ///< GPIO INT[19]:  P_GPIO[8]
+#define GPIO_INT_20                 20      ///< GPIO INT[20]:  P_GPIO[9]
+#define GPIO_INT_21                 21      ///< GPIO INT[21]:  P_GPIO[11]
+#define GPIO_INT_22                 22      ///< GPIO INT[22]:  P_GPIO[15]
+#define GPIO_INT_23                 23      ///< GPIO INT[23]:  P_GPIO[17]
+#define GPIO_INT_24                 24      ///< GPIO INT[24]:  P_GPIO[18]
+#define GPIO_INT_25                 25      ///< GPIO INT[25]:  P_GPIO[24]
+#define GPIO_INT_26                 26      ///< GPIO INT[26]:  L_GPIO[1]
+#define GPIO_INT_27                 27      ///< GPIO INT[27]:  L_GPIO[6]
+#define GPIO_INT_28                 28      ///< GPIO INT[28]:  L_GPIO[11]
+#define GPIO_INT_29                 29      ///< GPIO INT[29]:  L_GPIO[14]
+#define GPIO_INT_30                 30      ///< GPIO INT[30]:  P_GPIO[18]
+#define GPIO_INT_31                 31      ///< GPIO INT[31]:  L_GPIO[22]
+#define GPIO_INT_32                 32      ///< DGPIO INT[0]:  D_GPIO[0]
+#define GPIO_INT_33                 33      ///< DGPIO INT[1]:  D_GPIO[1]
+#define GPIO_INT_34                 34      ///< DGPIO INT[2]:  D_GPIO[2]
+#define GPIO_INT_35                 35      ///< DGPIO INT[3]:  D_GPIO[3]
+#define GPIO_INT_36                 36      ///< DGPIO INT[4]:  D_GPIO[4]
+#define GPIO_INT_37                 37      ///< DGPIO INT[5]:  D_GPIO[5]
+#define GPIO_INT_38                 38      ///< DGPIO INT[6]:  D_GPIO[6]
+#define GPIO_INT_39                 39      ///< DGPIO INT[7]:  D_GPIO[7]
+
+#define GPIO_INT_48                 48      ///< DGPIO INT[16]: USB wakeup
+
+#define GPIO_INT_USBWAKEUP          (GPIO_INT_48)   ///< DGPIO INT[16]: USB wakeup
+//@}
+
+// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " or "D_GPIO_*"
+#define GPIO_IS_DGPIO               (128)
+
+
+//
+// The general api for the GPIO device driver
+//
+extern void     gpio_setDir(UINT32 pin, UINT32 dir);
+extern UINT32   gpio_getDir(UINT32 pin);
+extern void     gpio_setPin(UINT32 pin);
+extern void     gpio_clearPin(UINT32 pin);
+extern UINT32   gpio_getPin(UINT32 pin);
+extern void     gpio_pullSet(UINT32 pin);
+extern void     gpio_pullClear(UINT32 pin);
+extern UINT32   gpio_readData(UINT32 dataidx);
+extern void     gpio_writeData(UINT32 dataidx, UINT32 value);
+//extern UINT32   gpio_readDir(UINT32 dataidx);
+//extern void     gpio_writeDir(UINT32 dataidx, UINT32 value);
+extern UINT32   dgpio_readData(void);
+extern void     dgpio_writeData(UINT32 value);
+extern UINT32 	top_get_bs(void);
+//extern UINT32   dgpio_readDir(void);
+//extern void     dgpio_writeDir(UINT32 value);
+//@}
+#endif
+

loader/Include/Driver/Memory.h

@@ -0,0 +1,437 @@
+# ifndef _MEMORY_520_H
+# define _MEMORY_520_H
+
+#ifndef __ASSEMBLY__
+    COMMENT  /* Memory Map */ /* # define BOOT_ROM_RAM_BASE_ADDR        0x20000000*/
+#endif
+# define DRAM_BASE_ADDR             (0x00000000)
+# define DRAM_EXP_BASE_ADDR         (DRAM_BASE_ADDR + 0x180)
+# define DRAM_INT_BASE_ADDR         (DRAM_BASE_ADDR + 0x200)
+
+# define StackSize_KNL              0x1000       /* 4KB */
+# define StackSize_INT              0x400        /* 1KB */
+
+# define FAT_HEAP_BUFFER_SIZE       0xA0000//0x1E0000 //0x1E8000
+# define EXFAT_BITMAP_BUFFER_SIZE   0x20000  //0x18000
+# define LOADER_TMP_BUFFER_SIZE     0x80000
+
+# define BOOT_ROM_SP_LIMIT_ADDR     0xF07F8FFC
+# define BOOT_ROM_RAM_TEMP_ADDR     0xF0800200
+# define BOOT_ROM_CFG_TEMP_ADDR     0xF0800248
+# define BOOT_ROM_RAM_BASE_ADDR     0x00000000
+# define DMA2_CTRL_REG_BASE_ADDR    0xF0100000
+# define DMA2_PHY_REG_BASE_ADDR     0xF0101000
+# define USB_OTG_REG_BASE_ADDR      0//0xF0600000
+# define DDR_CTRL_REG_BASE_ADDR     0xF0000000      /* DDR phy base address     */
+# define DDR_PHY_REG_BASE_ADDR      0xF0001000
+# define DDR_ARB_REG_BASE_ADDR      0xF0008000
+# define DMA2_ARB_REG_BASE_ADDR     0xF0108000
+
+# define CLOCK_GEN_REG_BASE_ADDR    0xF0020000
+# define PMU_REG_BASE_ADDR          0xF0024000
+# define TOP_CTRL_REG_BASE_ADDR     0xF0010000
+# define PAD_CTRL_REG_BASE_ADDR     0xF0030000
+# define GPIO_CTRL_REG_BASE_ADDR    0xF0070000
+# define PMC_REG_BASE               0xF00A0000
+
+# define TRNG_REG_BASE_ADDR         0xF0680000
+
+# define CPU_REG_BASE_ADDR          0xF0FF0000
+
+# define UART0_REG_BASE_ADDR        0xF0290000
+// Real board is UART3
+# define UART2_REG_BASE_ADDR        0xF0310000
+# define SM_HOST_REG_BASE_ADDR      0xF0400000
+# define MS_HOST_REG_BASE_ADDR      0xF0410000
+# define SD_HOST1_REG_BASE_ADDR     0xF0420000
+# define SD_HOST2_REG_BASE_ADDR     0xF0500000
+# define SD_HOST3_REG_BASE_ADDR     0xF0510000
+# define SPI_CTRL_REG_BASE_ADDR     0xF0230000
+# define ETH_CTRL_REG_BASE_ADDR     0xF02B0000
+# define EFUSE_CTRL_REG_BASE_ADDR   0xF0660000
+# define IDE_SRAM_BASE_ADDR         0xF07C0000
+# define IDE_CTRL_REG_BASE_ADDR     0xF0800000
+# define TIMER_REG_BASE_ADDR        0xF0040000
+# define WDT_REG_BASE_ADDR          0xF0050000
+
+# define BOOT_LOADER_TMP_BUFFER     0x00001000
+# define CHIP_REMAP_REG_OFFSET      0x00000088
+# define CPE_RTC_BASE               0xF0060000      /* RTC controller           */
+# define CPE_GPIO_BASE              0xF0070000      /* GPIO controller          */
+# define INTERRUPT_BASE_ADDR        0xF0080000      /* Interrupt controller     */
+# define CC_BASE_ADDR               0xF0090000      /* CC controller     */
+# define IOADDR_GIC_REG_BASE        0xFFD00000      /* GIC Interrupt     */
+# define configARM_TIMER_BASEADDR   0xFFD00200
+# define ARM_TIMER_LOAD_OFFSET      0x00       		/**< Timer Load Register */
+
+
+# define BOOT_ROM_RAM_TEMP_ADDR2    0xF07E8000   	//Eth
+# define PAD_REG_BASE				0xF0030000
+# define L2_MEM_BASE				0xFFE00000
+# define IOADDR_HVYLOAD_REG_BASE    0xF0008000
+
+# define CC_CPU2_CPU1_CMDBUF_REG1 	0xF07F8000						//CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address
+# define CC_CPU2_CPU1_CMDBUF_REG2 	0xF07F8004 						//CC_CPU2_CPU1_CMDBUF_REG1 has used in core2_entry.s
+# define NVT_CORE2_START 			CC_CPU2_CPU1_CMDBUF_REG2		//core2_entry.S 's entry point
+
+# define ARM_TIMER_LOAD_OFFSET      		0x00       		/**< Timer Load Register */
+# define ARM_TIMER_LOAD_OFFSET              0x00       /**< Timer Load Register */
+# define ARM_TIMER_COUNTER_OFFSET           0x04       /**< Timer Counter Register */
+# define ARM_TIMER_CONTROL_OFFSET           0x08       /**< Timer Control Register */
+# define ARM_TIMER_ISR_OFFSET               0x0C       /**< Timer Interrupt Status Register */
+# define ARM_TIMER_COUNTER_OFFSET_L         0x00       /**< Timer Counter Register */
+# define ARM_TIMER_COUNTER_OFFSET_H         0x04       /**< Timer Counter Register */
+# define ARM_TIMER_COUNTER_CMP_OFFSET_L     0x10       /**< Timer Counter Register */
+# define ARM_TIMER_COUNTER_CMP_OFFSET_H     0x14       /**< Timer Counter Register */
+# define CYGHWR_HAL_RTC_PRESCALER			1
+# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */
+# define ARM_TIMER_CONTROL_PRESCALER_MASK   0x0000FF00 /**< Prescaler */
+# define ARM_TIMER_CONTROL_PRESCALER_SHIFT  8
+# define ARM_TIMER_CONTROL_IRQ_ENABLE_MASK  0x00000004 /**< Intr enable */
+# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */
+# define ARM_TIMER_CONTROL_ENABLE_MASK      0x00000001 /**< Timer enable */
+
+#define ARM_TIMER_ISR_EVENT_FLAG_MASK       0x00000001 /**< Event flag */
+#define CRYPTO_REG_BASE_ADDR				0xF0620000
+#define HASH_REG_BASE_ADDR         			0xF0670000
+#define RSA_REG_BASE_ADDR          			0xF06A0000
+
+#define CRYPTO_CONFIG_REG        			(CRYPTO_REG_BASE_ADDR + 0x00)
+#define CRYPTO_CONTROL_REG       			(CRYPTO_REG_BASE_ADDR + 0x04)
+#define CRYPTO_OUT_DATA_REG      			(CRYPTO_REG_BASE_ADDR + 0x08)
+#define CRYPTO_STATUS_REG        			(CRYPTO_REG_BASE_ADDR + 0x0C)
+
+#define CRYPTO_PIO_INPUT0_REG    			(CRYPTO_REG_BASE_ADDR + 0x30)
+#define CRYPTO_PIO_INPUT1_REG    			(CRYPTO_REG_BASE_ADDR + 0x34)
+#define CRYPTO_PIO_INPUT2_REG    			(CRYPTO_REG_BASE_ADDR + 0x38)
+#define CRYPTO_PIO_INPUT3_REG    			(CRYPTO_REG_BASE_ADDR + 0x3C)
+#define CRYPTO_PIO_OUTPUT0_REG   			(CRYPTO_REG_BASE_ADDR + 0x40)
+#define CRYPTO_PIO_OUTPUT1_REG   			(CRYPTO_REG_BASE_ADDR + 0x44)
+#define CRYPTO_PIO_OUTPUT2_REG   			(CRYPTO_REG_BASE_ADDR + 0x48)
+#define CRYPTO_PIO_OUTPUT3_REG   			(CRYPTO_REG_BASE_ADDR + 0x4C)
+
+// Hash
+#define HASH_CONFIG_REG         			(HASH_REG_BASE_ADDR + 0x00)
+#define HASH_STATUS_REG         			(HASH_REG_BASE_ADDR + 0x0C)
+#define HASH_OUTPUT_DATA1_REG   			(HASH_REG_BASE_ADDR + 0x70)
+#define HASH_INPUT_DATA_REG     			(HASH_REG_BASE_ADDR + 0x90)
+
+//RSA
+#define RSA_CONFIG_REG              	 	(RSA_REG_BASE_ADDR + 0x00)
+#define RSA_CONTROL_REG              		(RSA_REG_BASE_ADDR + 0x04)
+#define RSA_STATUS_REG               		(RSA_REG_BASE_ADDR + 0x0C)
+#define RSA_KEY_N_REG                		(RSA_REG_BASE_ADDR + 0x10)
+#define RSA_KEY_N_ADDR_REG           		(RSA_REG_BASE_ADDR + 0x14)
+#define RSA_KEY_ED_REG               		(RSA_REG_BASE_ADDR + 0x18)
+#define RSA_KEY_ED_ADDR_REG          		(RSA_REG_BASE_ADDR + 0x1C)
+#define RSA_DATA_REG                 		(RSA_REG_BASE_ADDR + 0x20)
+#define RSA_DATA_ADDR_REG            		(RSA_REG_BASE_ADDR + 0x24)
+#define RSA_CRC32_DEFAULT_REG_OFS    		(RSA_REG_BASE_ADDR + 0x30)
+#define RSA_CRC32_POLY_REG_OFS       		(RSA_REG_BASE_ADDR + 0x34)
+#define RSA_CRC32_OUTPUT_REG_OFS     		(RSA_REG_BASE_ADDR + 0x38)
+
+// Crypto
+#define CRYPTO_CONFREG_SWRST          	(1<<0)
+#define CRYPTO_CONFREG_CRYPTO_EN      	(1<<1)
+#define CRYPTO_CONFREG_AES128         	(2<<4)
+#define CRYPTO_CONFREG_DECRYPT        	(1<<8)
+
+#define CRYPTO_PIO_DONE               	(1<<0)
+
+// Hash
+#define HASH_CONFREG_INITSTATE        	(1<<20)
+#define HASH_CONFREG_SHA256           	(1<<4)
+#define HASH_CONFREG_ENABLE           	(1<<1)
+
+//RSA
+#define RSA_ENABLE                    	(1<<0)
+
+#define RSA_KEYWIDTH_256              	(0x0<<1)
+#define RSA_KEYWIDTH_512              	(0x1<<1)
+#define RSA_KEYWIDTH_1024             	(0x2<<1)
+#define RSA_KEYWIDTH_2048             	(0x3<<1)
+#define RSA_KEYWIDTH_4096             	(0x4<<1)
+
+#define RSA_NORMAL_MODE               	(0x0<<4)
+#define RSA_MODE_CRC_KEY_N           	(0x1<<4)
+#define RSA_MODE_CRC_KEY_ED           	(0x2<<4)
+
+
+#define RSA_TRANSFER_END              	(0x1<<0)
+#define RSA_BUSY                      	(0x1<<1)
+
+#define HASH_TRANSFER_END             	(0x1<<0)
+
+
+
+#define TOP_CTRL_SRAM_RESET_REG0    	(TOP_CTRL_REG_BASE_ADDR + 0x1000)
+
+//Shut down SRAM SDIO1 mask
+#define TOP_SRAM_SD_SDIO1           	0x20000000
+//Shut down SRAM RSA mask
+#define TOP_SRAM_SD_RSA             	0x02000000
+
+
+#define reg0_cache_type_ofs			0x004			//reg0_cache_type
+#define CACHE_CTRL_REG_OFS			0x100
+#define CACHE_AUX_CTRL_REG_OFS		0x104
+
+#define CACHE_TAG_RAM_CTRL_OFS		0x108
+#define CACHE_DATA_RAM_CTRL_OFS		0x10C
+
+
+#define reg2_int_clear_ofs			0x220			//reg2_int_clear
+#define reg7_cache_sync				0x730			//reg7_cache_sync
+#define reg7_inv_way				0x77C			//reg7_inv_way
+
+#define CACHE_PREFETCH_REG_OFS		0xF60
+
+#define L2_REG0_BASE	            (L2_MEM_BASE + 0x000)	/* Cache ID and Cache Type */
+#define L2_REG1_BASE	            (L2_MEM_BASE + 0x100)	/* Control */
+#define L2_REG2_BASE	            (L2_MEM_BASE + 0X200)	/* Interrupt and Counter Control Registers */
+#define L2_REG7_BASE	            (L2_MEM_BASE + 0x700)	/* Cache Maintenance Operations */
+#define L2_REG9_BASE	            (L2_MEM_BASE + 0x900)	/* Cache Lockdown */
+#define L2_REG12_BASE	            (L2_MEM_BASE + 0xC00)	/* Address Filtering */
+#define L2_REG15_BASE	            (L2_MEM_BASE + 0xF00)	/* Debug, Prefetch and Power */
+
+/**
+ * Cache ID and Cache Type
+ */
+#define L2_REG0_CACHE_ID				(*((volatile unsigned long *)(L2_REG0_BASE + 0x00)))
+#define L2_REG0_CACHE_TYPE				(*((volatile unsigned long *)(L2_REG0_BASE + 0x04)))
+
+#define S_L2_REG0_CACHE_TYPE_DB			(31)
+#define M_L2_REG0_CACHE_TYPE_DB			(0xf << S_L2_REG0_CACHE_TYPE_DB)
+#define S_L2_REG0_CACHE_TYPE_CTYPE		(25)
+#define M_L2_REG0_CACHE_TYPE_CTYPE		(0xf << S_L2_REG0_CACHE_TYPE_CTYPE)
+#define S_L2_REG0_CACHE_TYPE_H			(24)
+#define M_L2_REG0_CACHE_TYPE_H			(0x1 << S_L2_REG0_CACHE_TYPE_H)
+#define S_L2_REG0_CACHE_TYPE_DWS		(20)
+#define M_L2_REG0_CACHE_TYPE_DWS		(0x7 << S_L2_REG0_CACHE_TYPE_DWS)
+#define S_L2_REG0_CACHE_TYPE_DA			(18)
+#define M_L2_REG0_CACHE_TYPE_DA			(0x1 << S_L2_REG0_CACHE_TYPE_DA)
+#define S_L2_REG0_CACHE_TYPE_DLS		(12)
+#define M_L2_REG0_CACHE_TYPE_DLS		(0x3 << S_L2_REG0_CACHE_TYPE_DLS)
+#define S_L2_REG0_CACHE_TYPE_IWS		(8)
+#define M_L2_REG0_CACHE_TYPE_IWS		(0x7 << S_L2_REG0_CACHE_TYPE_IWS)
+#define S_L2_REG0_CACHE_TYPE_IA			(6)
+#define M_L2_REG0_CACHE_TYPE_IA			(0x1 << S_L2_REG0_CACHE_TYPE_IA)
+#define S_L2_REG0_CACHE_TYPE_ILS		(0)
+#define M_L2_REG0_CACHE_TYPE_ILS		(0x3 << S_L2_REG0_CACHE_TYPE_ILS)
+
+#define K_L2_REG0_CACHE_TYPE_DA_16WAY	(1)
+#define K_L2_REG0_CACHE_TYPE_DA_8WAY	(0)
+
+/**
+ * Control
+ */
+#define L2_REG1_CONTROL					(*((volatile unsigned long *)(L2_REG1_BASE + 0x00)))
+#define L2_REG1_AUX_CTRL				(*((volatile unsigned long *)(L2_REG1_BASE + 0x04)))
+#define L2_REG1_TAG_RAM_CTRL			(*((volatile unsigned long *)(L2_REG1_BASE + 0x08)))
+#define L2_REG1_DATA_RAM_CTRL			(*((volatile unsigned long *)(L2_REG1_BASE + 0x0C)))
+
+#define S_L2_REG1_CONTROL_EN	(0)
+#define M_L2_REG1_CONTROL_EN	(0x1 << S_L2_REG1_CONTROL_EN)
+
+#define K_L2_REG1_CONTROL_EN_ON		1
+#define K_L2_REG1_CONTROL_EN_OFF	0
+
+#define S_L2_REG1_AUX_CTRL_BRESP						(30)
+#define M_L2_REG1_AUX_CTRL_BRESP						(0x1 << S_L2_REG1_AUX_CTRL_BRESP)
+#define S_L2_REG1_AUX_CTRL_INSTR_PREF					(29)
+#define M_L2_REG1_AUX_CTRL_INSTR_PREF					(0x1 << S_L2_REG1_AUX_CTRL_INSTR_PREF)
+#define S_L2_REG1_AUX_CTRL_DATA_PERF					(28)
+#define M_L2_REG1_AUX_CTRL_DATA_PERF					(0x1 << S_L2_REG1_AUX_CTRL_DATA_PERF)
+#define S_L2_REG1_AUX_CTRL_NS_INT_CTRL					(27)
+#define M_L2_REG1_AUX_CTRL_NS_INT_CTRL					(0x1 << S_L2_REG1_AUX_CTRL_NS_INT_CTRL)
+#define S_L2_REG1_AUX_CTRL_NS_LOCK_EN					(26)
+#define M_L2_REG1_AUX_CTRL_NS_LOCK_EN					(0x1 << S_L2_REG1_AUX_CTRL_NS_LOCK_EN)
+#define S_L2_REG1_AUX_CTRL_CACHE_POLICY					(25)
+#define M_L2_REG1_AUX_CTRL_CACHE_POLICY					(0x1 << S_L2_REG1_AUX_CTRL_CACHE_POLICY)
+#define S_L2_REG1_AUX_CTRL_FORCE_WA						(23)
+#define M_L2_REG1_AUX_CTRL_FORCE_WA						(0x3 << S_L2_REG1_AUX_CTRL_FORCE_WA)
+#define S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN			(22)
+#define M_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN			(0x1 << S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN)
+#define S_L2_REG1_AUX_CTRL_PARITY_EN					(21)
+#define M_L2_REG1_AUX_CTRL_PARITY_EN					(0x1 << S_L2_REG1_AUX_CTRL_PARITY_EN)
+#define S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN				(20)
+#define M_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN				(0x1 << S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN)
+#define S_L2_REG1_AUX_CTRL_WAT_SIZE						(17)
+#define M_L2_REG1_AUX_CTRL_WAT_SIZE						(0x7 << S_L2_REG1_AUX_CTRL_WAT_SIZE)
+#define S_L2_REG1_AUX_CTRL_ASSOCIATIVITY				(16)
+#define M_L2_REG1_AUX_CTRL_ASSOCIATIVITY				(0x1 << S_L2_REG1_AUX_CTRL_ASSOCIATIVITY)
+#define S_L2_REG1_AUX_CTRL_SHARED_INV_EN				(13)
+#define M_L2_REG1_AUX_CTRL_SHARED_INV_EN				(0x1 << S_L2_REG1_AUX_CTRL_SHARED_INV_EN)
+#define S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF			(12)
+#define M_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF			(0x1 << S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF)
+#define S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN		(11)
+#define M_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN		(0x1 << S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN)
+#define S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN	(10)
+#define M_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN	(0x1 << S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN)
+#define S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN				(0)
+#define M_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN				(0x1 << S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN)
+
+/**
+ * Interrupt and Counter Control Registers
+ */
+#define L2_REG2_EV_CNT_CTRL				(*((volatile unsigned long *)(L2_REG2_BASE + 0x00)))
+#define L2_REG2_EV_CNT1_CFG				(*((volatile unsigned long *)(L2_REG2_BASE + 0x04)))
+#define L2_REG2_EV_CNT0_CFG				(*((volatile unsigned long *)(L2_REG2_BASE + 0x08)))
+#define L2_REG2_EV_CNT1					(*((volatile unsigned long *)(L2_REG2_BASE + 0x0C)))
+#define L2_REG2_EV_CNT0					(*((volatile unsigned long *)(L2_REG2_BASE + 0x10)))
+#define L2_REG2_INT_MASK				(*((volatile unsigned long *)(L2_REG2_BASE + 0x14)))
+#define L2_REG2_INT_MASK_STATUS			(*((volatile unsigned long *)(L2_REG2_BASE + 0x18)))
+#define L2_REG2_INT_RAW_STATUS			(*((volatile unsigned long *)(L2_REG2_BASE + 0x1C)))
+#define L2_REG2_INT_CLEAR				(*((volatile unsigned long *)(L2_REG2_BASE + 0x20)))
+
+#define S_L2_REG2_INT_DECERR	(8)
+#define M_L2_REG2_INT_DECERR	(0x1 << S_L2_REG2_INT_DECERR)	/* Decode error */
+#define S_L2_REG2_INT_SLVERR	(7)
+#define M_L2_REG2_INT_SLVERR	(0x1 << S_L2_REG2_INT_SLVERR)	/* Slave error */
+#define S_L2_REG2_INT_ERRRD		(6)
+#define M_L2_REG2_INT_ERRRD		(0x1 << S_L2_REG2_INT_ERRRD)	/* Data RAM read error */
+#define S_L2_REG2_INT_ERRRT		(5)
+#define M_L2_REG2_INT_ERRRT		(0x1 << S_L2_REG2_INT_ERRRT)	/* Tag RAM read error */
+#define S_L2_REG2_INT_ERRWD		(4)
+#define M_L2_REG2_INT_ERRWD		(0x1 << S_L2_REG2_INT_ERRWD)	/* Data RAM write error */
+#define S_L2_REG2_INT_ERRWT		(3)
+#define M_L2_REG2_INT_ERRWT		(0x1 << S_L2_REG2_INT_ERRWT)	/* Tag RAM write error */
+#define S_L2_REG2_INT_PARRD		(2)
+#define M_L2_REG2_INT_PARRD		(0x1 << S_L2_REG2_INT_PARRD)	/* Parity error on data RAM read */
+#define S_L2_REG2_INT_PARRT		(1)
+#define M_L2_REG2_INT_PARRT		(0x1 << S_L2_REG2_INT_PARRT)	/* Pariry error on tag RAM read */
+#define S_L2_REG2_INT_ECNTR		(0)
+#define M_L2_REG2_INT_ECNTR		(0x1 << S_L2_REG2_INT_ECNTR)	/* Event counter1/0 overflow increment */
+
+/**
+ * Cache Maintenance Operations
+ */
+#define L2_REG7_CACHE_SYNC				(*((volatile unsigned long *)(L2_REG7_BASE + 0x30)))
+#define L2_REG7_INV_PA					(*((volatile unsigned long *)(L2_REG7_BASE + 0x70)))
+#define L2_REG7_INV_WAY					(*((volatile unsigned long *)(L2_REG7_BASE + 0x7C)))
+#define L2_REG7_CLEAN_PA				(*((volatile unsigned long *)(L2_REG7_BASE + 0xB0)))
+#define L2_REG7_CLEAN_INDEX				(*((volatile unsigned long *)(L2_REG7_BASE + 0xB8)))
+#define L2_REG7_CLEAN_WAY				(*((volatile unsigned long *)(L2_REG7_BASE + 0xBC)))
+#define L2_REG7_CLEAN_INV_PA			(*((volatile unsigned long *)(L2_REG7_BASE + 0xF0)))
+#define L2_REG7_CLEAN_INV_INDEX			(*((volatile unsigned long *)(L2_REG7_BASE + 0xF8)))
+#define L2_REG7_CLEAN_INV_WAY			(*((volatile unsigned long *)(L2_REG7_BASE + 0xFC)))
+
+
+#define K_L2_REG7_CACHE_SYNC_C			(0x1)
+
+#define K_L2_REG7_INV_WAY_8WAY			(0x00ff)
+#define K_L2_REG7_INV_WAY_16WAY			(0xffff)
+#define K_L2_REG7_CLEAN_WAY_8WAY        (0x00ff)
+#define K_L2_REG7_CLEAN_WAY_16WAY       (0xffff)
+
+
+/**
+ * Cache Lockdown
+ */
+#define L2_REG9_D_LOCKDOWN0				(*((volatile unsigned long *)(L2_REG9_BASE + 0x00)))
+#define L2_REG9_I_LOCKDOWN0				(*((volatile unsigned long *)(L2_REG9_BASE + 0x04)))
+#define L2_REG9_D_LOCKDOWN1				(*((volatile unsigned long *)(L2_REG9_BASE + 0x08)))
+#define L2_REG9_I_LOCKDOWN1				(*((volatile unsigned long *)(L2_REG9_BASE + 0x0C)))
+#define L2_REG9_D_LOCKDOWN2				(*((volatile unsigned long *)(L2_REG9_BASE + 0x10)))
+#define L2_REG9_I_LOCKDOWN2				(*((volatile unsigned long *)(L2_REG9_BASE + 0x14)))
+#define L2_REG9_D_LOCKDOWN3				(*((volatile unsigned long *)(L2_REG9_BASE + 0x18)))
+#define L2_REG9_I_LOCKDOWN3				(*((volatile unsigned long *)(L2_REG9_BASE + 0x1C)))
+#define L2_REG9_D_LOCKDOWN4				(*((volatile unsigned long *)(L2_REG9_BASE + 0x20)))
+#define L2_REG9_I_LOCKDOWN4				(*((volatile unsigned long *)(L2_REG9_BASE + 0x24)))
+#define L2_REG9_D_LOCKDOWN5				(*((volatile unsigned long *)(L2_REG9_BASE + 0x28)))
+#define L2_REG9_I_LOCKDOWN5				(*((volatile unsigned long *)(L2_REG9_BASE + 0x2C)))
+#define L2_REG9_D_LOCKDOWN6				(*((volatile unsigned long *)(L2_REG9_BASE + 0x30)))
+#define L2_REG9_I_LOCKDOWN6				(*((volatile unsigned long *)(L2_REG9_BASE + 0x34)))
+#define L2_REG9_D_LOCKDOWN7				(*((volatile unsigned long *)(L2_REG9_BASE + 0x38)))
+#define L2_REG9_I_LOCKDOWN7				(*((volatile unsigned long *)(L2_REG9_BASE + 0x3C)))
+#define L2_REG9_LOCK_LINE_EN			(*((volatile unsigned long *)(L2_REG9_BASE + 0x50)))
+#define L2_REG9_UNLOCK_WAY				(*((volatile unsigned long *)(L2_REG9_BASE + 0x54)))
+
+/**
+ * Address Filtering
+ */
+#define L2_REG12_ADDR_FILTERING_START	(*((volatile unsigned long *)(L2_REG12_BASE + 0x00)))
+#define L2_REG12_ADDR_FILTERING_END		(*((volatile unsigned long *)(L2_REG12_BASE + 0x04)))
+
+/**
+ * Debug, Prefetch and Power
+ */
+#define L2_REG15_DEBUG_CTRL				(*((volatile unsigned long *)(L2_REG15_BASE + 0x40)))
+#define L2_REG15_PREF_CTRL				(*((volatile unsigned long *)(L2_REG15_BASE + 0x60)))
+#define L2_REG15_POWER_CTRL				(*((volatile unsigned long *)(L2_REG15_BASE + 0x80)))
+
+#define S_L2_REG15_DEBUG_CTRL_SPNIDEN	(2)
+#define M_L2_REG15_DEBUG_CTRL_SPNIDEN	(0x1 << S_L2_REG15_DEBUG_CTRL_SPNIDEN)
+#define S_L2_REG15_DEBUG_CTRL_DWB		(1)
+#define M_L2_REG15_DEBUG_CTRL_DWB		(0x1 << S_L2_REG15_DEBUG_CTRL_DWB)
+#define S_L2_REG15_DEBUG_CTRL_DCL		(0)
+#define M_L2_REG15_DEBUG_CTRL_DCL		(0x1 << S_L2_REG15_DEBUG_CTRL_DCL)
+
+#define S_L2_REG15_PREF_CTRL_DL_FILL_EN					(30)
+#define M_L2_REG15_PREF_CTRL_DL_FILL_EN					(0x1 << S_L2_REG15_PREF_CTRL_DL_FILL_EN)
+#define S_L2_REG15_PREF_CTRL_INST_PREF_EN				(29)
+#define M_L2_REG15_PREF_CTRL_INST_PREF_EN				(0x1 << S_L2_REG15_PREF_CTRL_INST_PREF_EN)
+#define S_L2_REG15_PREF_CTRL_DATA_PREF_EN				(28)
+#define M_L2_REG15_PREF_CTRL_DATA_PREF_EN				(0x1 << S_L2_REG15_PREF_CTRL_DATA_PREF_EN)
+#define S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS			(27)
+#define M_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS			(0x1 << S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS)
+#define S_L2_REG15_PREF_CTRL_PREF_DROP_EN				(24)
+#define M_L2_REG15_PREF_CTRL_PREF_DROP_EN				(0x1 << S_L2_REG15_PREF_CTRL_PREF_DROP_EN)
+#define S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN			(23)
+#define M_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN			(0x1 << S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN)
+#define S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN	(21)
+#define M_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN	(0x1 << S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN)
+#define S_L2_REG15_PREF_CTRL_PREF_OFF					(0)
+#define M_L2_REG15_PREF_CTRL_PREF_OFF					(0xf << S_L2_REG15_PREF_CTRL_PREF_OFF)
+
+// DDR phy duty configuration register bit
+#define DDR_PHY_INCREASE_DUTY       0x40            // P < N
+#define DDR_PHY_DECREASE_DUTY       0x00            // P > N
+#define DDR_PHY_DUTY_TYPE_MSK       0x40            // bit mask for increase/decrease duty
+#define DDR_PHY_CLK_ADJ_EN          0x80
+
+// DDR phy duty calibration control register bit
+#define DDR_PHY_CLK_OP_ONGOING      0x10
+#define DDR_PHY_CLK_OP_DONE         0x00
+#define DDR_PHY_DQS_OP_ONGOING      0x20
+#define DDR_PHY_DQS_OP_DONE         0x00
+
+
+# define DDR_PHY_CAL_CLK_ADJ_OFS    0x000           /* 0x00                     */
+# define DDR_PHY_CAL_CMD_ADJ_OFS    0x01C           /* 0x1C                     */
+# define DDR_PHY_CAL_CTRL_OFS       0x150           /* 0x54                     */
+# define DDR_PHY_CAL_CLK_CFG_OFS    0x154           /* 0x55                     */
+# define DDR_PHY_CAL_DQS_CFG_OFS    0x158           /* 0x56                     */
+# define DDR_PHY_CAL_DTY_CNT_LB_OFS 0x15C           /* 0x57 duty cnt low byte   */
+# define DDR_PHY_CAL_DTY_CNT_HB_OFS 0x160           /* 0x58 duty cnt high byte  */
+# define DDR_PHY_CAL_DQS0_ADJ_OFS   0x1D0           /* 0x1D0                    */
+# define DDR_PHY_CAL_DQ_ADJ_OFS     0x1D4           /* 0x1D0                    */
+
+
+#define BOOT_SOURCE_SPI                0x00
+#define BOOT_SOURCE_CARD               0x01
+#define BOOT_SOURCE_SPI_NAND_2K        0x02
+#define BOOT_SOURCE_SPI_NAND_RS_2K     0x03
+#define BOOT_SOURCE_ETHERNET           0x04
+#define BOOT_SOURCE_USB                0x05
+#define BOOT_SOURCE_SPI_NAND_4K        0x06
+#define BOOT_SOURCE_BMC                0x07
+#define BOOT_SOURCE_EMMC_4BIT          0x08
+#define BOOT_SOURCE_EMMC_8BIT          0x09
+#define BOOT_SOURCE_SPI_NAND_RS_4K     0x0A
+#define BOOT_SOURCE_USB_FULL           0x0B
+
+#define BOOT_SOURCE_MSK                0x0F
+
+
+# define IDENTIFY_ERR       2
+# define MBR_ERR            3
+# define PBR_ERR            4
+# define READ512_ERR        5
+# define READ_ERR           7
+# define HPA_ERR            8
+# define CHECKSUM_ERR       9
+#ifndef __ASSEMBLY__
+    END
+#endif
+# endif

loader/Include/Driver/crypto.h

@@ -0,0 +1,98 @@
+/**
+    Header file for CC (Core Communicator) module.
+
+    This file is the header file that define the API and data type
+    for CC module.
+
+    @file       CC.h
+    @ingroup    mIDrvSys_CC
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2015.  All rights reserved.
+*/
+
+#include "constant.h"
+
+#ifndef _CRYPTO_H
+#define _CRYPTO_H
+
+#define ROM_AES_SIZE                    (16)
+#define ROM_SHA_SIZE                    (32)    // unit: byte
+#define ROM_RSA_SIZE                    (256)   // RSA-2048
+#define ROM_RSA_EKEY_SIZE               (32)
+#define ROM_RSA_CRC32_SIZE              (4)
+/**
+    Crypto engine crypto mode
+*/
+typedef enum {
+    CRYPTO_RSV0,
+    CRYPTO_RSV1,
+	CRYPTO_AES,                         ///< Select Crypto mode AES
+	CRYPTO_MODE_NUM,
+} CRYPTO_MODE;
+
+/**
+    Crypto engine crypto Operating mode
+*/
+typedef enum {
+	CRYPTO_EBC = 0x00,                  ///< Select Crypto opmode EBC
+	CRYPTO_CBC,                         ///< Select Crypto opmode CBC
+	CRYPTO_OPMODE_NUM,
+} CRYPTO_OPMODE;
+
+/**
+    Crypto engine encrypt or decrypt
+*/
+typedef enum {
+	CRYPTO_ENCRYPT = 0x00,              ///< Select Crypto engine encrypt
+	CRYPTO_DECRYPT,                     ///< Select Crypto engine decrypt
+	CRYPTO_TYPE_NUM,
+
+} CRYPTO_TYPE;
+
+typedef enum {
+	EFUSE_OTP_1ST_KEY_SET_FIELD = 0x0,        // This if for secure boot
+	EFUSE_OTP_2ND_KEY_SET_FIELD,
+	EFUSE_OTP_3RD_KEY_SET_FIELD,
+	EFUSE_OTP_4TH_KEY_SET_FIELD,
+
+	EFUSE_OTP_TOTAL_KEY_SET_FIELD,
+} EFUSE_OTP_KEY_SET_FIELD;
+
+typedef struct _CRYPT_OP {
+    CRYPTO_OPMODE   op_mode;            ///< Operation Mode (now support ECB only)
+    CRYPTO_TYPE     en_de_crypt;        ///< Encrypt or decrypt (CRYPTO_ENCRYPT or CRYPTO_DECRYPT)
+    UINT32          src_addr;           ///< Source address
+    UINT32          dst_addr;           ///< Destination address
+    UINT32          length;             ///< length
+} CRYPT_OP;
+
+/**
+    Crypto engine check
+*/
+typedef enum {
+	SECUREBOOT_SECURE_EN = 0x00,       	///< Quary if secure enable or not
+	SECUREBOOT_DATA_AREA_ENCRYPT,       ///< Quary if data area encrypt to cypher text or not
+	SECUREBOOT_SIGN_RSA,				///< Quary if Signature methed is RSA or not(AES)
+	SECUREBOOT_SIGN_RSA_CHK,			///< Quary if Signature hash checksum RSA key correct or not
+	SECUREBOOT_STATUS_NUM,
+
+} SECUREBOOT_STATUS;
+
+#define is_secure_enable()				quary_secure_boot(SECUREBOOT_SECURE_EN)			//For backward compatitable
+#define is_data_area_encrypted()		quary_secure_boot(SECUREBOOT_DATA_AREA_ENCRYPT)	//For backward compatitable
+#define is_signature_rsa()				quary_secure_boot(SECUREBOOT_SIGN_RSA)			//For backward compatitable
+#define is_signature_aes()				!quary_secure_boot(SECUREBOOT_SIGN_RSA)			//For backward compatitable
+BOOL quary_secure_boot(SECUREBOOT_STATUS scu_status);
+UINT32 crypto_data_operation(EFUSE_OTP_KEY_SET_FIELD key_set, CRYPT_OP crypt_op_param);
+void rsa_setConfig(UINT32 mode);
+void rsa_setkey_n(UINT8* key, UINT32 len, UINT32 sram_size);
+void rsa_setkey_ed(UINT8* key, UINT32 len, UINT32 sram_size);
+INT32 rsa_pio_enable(UINT8* data, UINT32 len, UINT32 sram_size);
+void rsa_getOutput(UINT8 * Output, UINT32 len, UINT32 sram_size);
+
+void shahw( const unsigned char *input, int ilen, UINT32 output[8]);
+void rsa_decrypt(UINT32 *input ,UINT32 input_len, UINT32 *pRSAN, UINT32 RSAN_len,  UINT32 *pRSAED, UINT32 RSAED_len , UINT32 *pShaOut);
+BOOL rsa_keycheck(UINT32 *input , BOOL efuseCheck);
+
+#endif

loader/Include/Driver/nand.h

@@ -0,0 +1,121 @@
+/**
+    nand module driver.
+
+    This file is the driver of storage module.
+
+    @file       nand.h
+    @ingroup    mIDrvStorage
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _NAND_DEF_
+#define _NAND_DEF_
+
+#include "IOReg.h"
+
+#define _SNAND_WINBOND_ID               (0xEF)
+#define _SNAND_ESMT_ID                  (0xC8)
+#define _SNAND_GD_ID                    (0xC8)
+#define _SNAND_MICRON_ID                (0x2C)
+#define _SNAND_ATO_ID                   (0x9B)
+#define _SNAND_ETRON_ID                 (0xD5)
+#define _SNAND_MXIC_ID     				(0xC2)
+#define _SNAND_TOSHIBA_ID               (0x98)
+#define _SNAND_DOSILICON_ID             (0xE5)
+
+
+
+#define _GD_SPI_NAND_1Gb            	(0xF1)
+#define _MXIC_SPI_NAND_1Gb            	(0x12)
+#define _DOSILICON_NAND_1Gb				(0x71)
+/**
+    SPI NAND flash QE(quid enable) identify type
+
+*/
+
+//@{
+typedef enum {
+	SPINAND_QE_NONE = 0x0,             ///< SPI NAND flash not with QE bit(only by quad command)
+	SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, ///< SPI NAND flash QE bit locate at feature field(0xB0H) bit[0]
+} SPINAND_QE_TYPE;
+
+
+/**
+    SPI NAND flash twp plane identify type
+
+*/
+//@{
+typedef enum {
+	SPINAND_2_PLANE_NONE = 0x0,       				///< SPI NAND flash not 2 plane type
+	SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL,///< SPI NAND flash use column addr bit[12] as plane select
+} SPINAND_PLANE_TYPE;
+
+
+
+/**
+    SPI flash identification structure
+
+    @note For SPIFLASH_IDENTIFY_CB
+*/
+typedef struct {
+	UINT32	pagesize;
+	UINT32	erasesize;
+	UINT32	qe_opt;
+	UINT32	plane_opt;
+} SPINAND_IDENTIFY, *PSPINAND_IDENTIFY;
+
+/**
+    SPIFLASH identify callback
+
+    Callback routine to be invoked after JEDEC ID is read from spi flash.
+    Callback routine should check if read ID is supported.
+
+    @note STRG_EXT_CMD_SPI_IDENTIFY_CB
+
+    @param[in] first parameter  (JEDEC) manufacturer ID read from spi flash
+    @param[in] second parameter (JEDEC) type ID read from spi flash
+    @param[in] third parameter  (JEDEC) capacity ID read from spi flash
+    @param[out] forth parameter flash identification returned to spi flash driver
+
+    @return
+        - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information
+        - @b FALSE: input ID is NOT supported/identified by call back
+*/
+typedef BOOL (*SPINAND_IDENTIFY_CB)(UINT32, UINT32, PSPINAND_IDENTIFY);
+
+
+
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
+ *          memory address as @id[0])
+ * @dev_id: the device ID (the second byte of the full chip ID array)
+ * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
+ *            well as the eraseblock size) is determined from the extended NAND
+ *            chip ID array)
+ * @erasesize: NAND block size
+ * @qe_opt: Quad enable type(please reference document to select this option)
+ * @plane_opt: 2 plane nand option(please reference document to select this option)
+ * @options: stores various chip bit options
+ *
+ */
+typedef struct _nand_flash_dev {
+	UINT32 	mfr_id;
+	UINT32	dev_id;
+	UINT32	pagesize;
+	UINT32	erasesize;
+	UINT32	qe_opt;
+	UINT32	plane_opt;
+} NAND_FLASH_DEV, *PNAND_FLASH_DEV;
+
+#define SPI_ID_NAND(mfrid, devid, pagesz, erasesz, opts, plane_opt_type)\
+	{ .mfr_id =(mfrid), .dev_id = (devid), .pagesize = (pagesz), \
+	  .erasesize = (erasesz), .qe_opt = (opts), .plane_opt=(plane_opt_type) }
+
+extern BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, PSPINAND_IDENTIFY pIdentify);
+
+#endif
+

loader/Include/Driver/nor.h

@@ -0,0 +1,51 @@
+/**
+    nand module driver.
+
+    This file is the driver of storage module.
+
+    @file       nand.h
+    @ingroup    mIDrvStorage
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _NOR_DEF_
+#define _NOR_DEF_
+
+#include "IOReg.h"
+#include "StorageDef.h"
+
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @name: a human-readable name of the NAND chip
+ * @dev_id: the device ID (the second byte of the full chip ID array)
+ * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
+ *          memory address as @id[0])
+ * @dev_id: device ID part of the full chip ID array (refers the same memory
+ *          address as @id[1])
+ * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
+ *            well as the eraseblock size) is determined from the extended NAND
+ *            chip ID array)
+ * @chipsize: total chip size in MiB
+ * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
+ * @options: stores various chip bit options
+ *
+ */
+typedef struct _nor_flash_dev {
+	UINT32 	mfr_id;
+	UINT32	dev_id;
+	UINT32	capacity_id;
+	UINT32	bDualRead;
+	UINT32	uiQuadReadType;
+	UINT32	uiFlashSize;
+} NOR_FLASH_DEV, *PNOR_FLASH_DEV;
+
+#define SPI_ID_NOR(mfrid, devid, capacityid, dual_read, quad_read_type, flash_size)\
+	{ .mfr_id =(mfrid), .dev_id = (devid), .capacity_id =(capacityid), .bDualRead=(dual_read), \
+	  .uiQuadReadType=(quad_read_type), .uiFlashSize=(flash_size) }
+
+
+extern BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify);
+#endif

loader/Include/Driver/pad.h

@@ -0,0 +1,874 @@
+/**
+    PAD controller header
+
+    PAD controller header
+
+    @file       pad.h
+    @ingroup    mIHALSysPAD
+    @note       Nothing
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _PAD_H
+#define _PAD_H
+
+//#include "Type.h"
+#include "constant.h"
+
+
+
+/** \addtogroup mIHALSysPAD */
+//@{
+
+// Macro to generate dummy element for enum type to expand enum size to word (4 bytes)
+#define ENUM_DUMMY4WORD(name)   E_##name = 0x10000000
+
+#if 0
+/**
+    Pad type select
+
+    Pad type select
+
+    Pad type value for pad_setPullUpDown().
+*/
+typedef enum
+{
+    PAD_NONE         =          0x00,      ///< none of pull up/down
+    PAD_PULLDOWN     =          0x01,      ///< pull down
+    PAD_PULLUP       =          0x02,      ///< pull up
+    PAD_KEEPER       =          0x03,      ///< keeper
+
+    ENUM_DUMMY4WORD(PAD_PULL)
+} PAD_PULL;
+
+/**
+    Pad driving select
+
+    Pad driving select
+
+    Pad driving value for pad_setDrivingSink().
+*/
+typedef enum {
+	PAD_DRIVINGSINK_2P5MA  =    0x01,       ///< for backward compatible
+	PAD_DRIVINGSINK_5MA  =      0x02,       ///< Pad driver/sink 5mA
+	PAD_DRIVINGSINK_7P5MA  =    0x04,       ///< for backward compatible
+	PAD_DRIVINGSINK_10MA  =     0x08,       ///< Pad driver/sink 10mA
+
+	PAD_DRIVINGSINK_12P5MA =    0x10,       ///< for backward compatible
+	PAD_DRIVINGSINK_15MA =      0x20,       ///< Pad driver/sink 15mA
+	PAD_DRIVINGSINK_17P5MA =    0x40,       ///< for backward compatible
+	PAD_DRIVINGSINK_20MA =      0x80,       ///< Pad driver/sink 20mA
+	PAD_DRIVINGSINK_25MA =     0x100,       ///< Pad driver/sink 25mA
+	PAD_DRIVINGSINK_30MA =     0x200,       ///< Pad driver/sink 30mA
+	PAD_DRIVINGSINK_35MA =     0x400,       ///< Pad driver/sink 35mA
+	PAD_DRIVINGSINK_40MA =     0x800,       ///< Pad driver/sink 40mA
+	PAD_DRIVINGSINK_4MA  =    0x1000,       ///< PAD driver/sink 4mA
+	PAD_DRIVINGSINK_6MA  =    0x2000,       ///< PAD driver/sink 6mA
+	PAD_DRIVINGSINK_8MA  =    0x4000,       ///< PAD driver/sink 8mA
+	PAD_DRIVINGSINK_16MA  =   0x8000,       ///< PAD driver/sink 16mA
+
+	ENUM_DUMMY4WORD(PAD_DRIVINGSINK)
+} PAD_DRIVINGSINK;
+
+/**
+    @name Pad type pin ID.
+
+    Pad type pin ID.
+
+    Pad ID of pad_setPullUpDown().
+*/
+#define PAD_PIN_NOT_EXIST       (15)                        // For backward compatible
+//@{
+//CGPIOx group begin
+#define PAD_PIN_CGPIO_BASE      0
+#define PAD_PIN_CGPIO0          (PAD_PIN_CGPIO_BASE + 0)      ///< CGPIO0
+#define PAD_PIN_CGPIO1          (PAD_PIN_CGPIO_BASE + 1)      ///< CGPIO1
+#define PAD_PIN_CGPIO2          (PAD_PIN_CGPIO_BASE + 2)      ///< CGPIO2
+#define PAD_PIN_CGPIO3          (PAD_PIN_CGPIO_BASE + 3)      ///< CGPIO3
+#define PAD_PIN_CGPIO4          (PAD_PIN_CGPIO_BASE + 4)      ///< CGPIO4
+#define PAD_PIN_CGPIO5          (PAD_PIN_CGPIO_BASE + 5)      ///< CGPIO5
+#define PAD_PIN_CGPIO6          (PAD_PIN_CGPIO_BASE + 6)      ///< CGPIO6
+#define PAD_PIN_CGPIO7          (PAD_PIN_CGPIO_BASE + 7)      ///< CGPIO7
+#define PAD_PIN_CGPIO8          (PAD_PIN_CGPIO_BASE + 8)      ///< CGPIO8
+#define PAD_PIN_CGPIO9          (PAD_PIN_CGPIO_BASE + 9)      ///< CGPIO9
+#define PAD_PIN_CGPIO10         (PAD_PIN_CGPIO_BASE + 10)     ///< CGPIO10
+#define PAD_PIN_CGPIO11         (PAD_PIN_CGPIO_BASE + 11)     ///< CGPIO11
+#define PAD_PIN_CGPIO12         (PAD_PIN_CGPIO_BASE + 12)     ///< CGPIO12
+#define PAD_PIN_CGPIO13         (PAD_PIN_CGPIO_BASE + 13)     ///< CGPIO13
+#define PAD_PIN_CGPIO14         (PAD_PIN_CGPIO_BASE + 14)     ///< CGPIO14
+#define PAD_PIN_CGPIO15         (PAD_PIN_CGPIO_BASE + 15)     ///< CGPIO15
+
+#define PAD_PIN_CGPIO16         (PAD_PIN_CGPIO_BASE + 16)     ///< CGPIO16
+#define PAD_PIN_CGPIO17         (PAD_PIN_CGPIO_BASE + 17)     ///< CGPIO17
+#define PAD_PIN_CGPIO18         (PAD_PIN_CGPIO_BASE + 18)     ///< CGPIO18
+#define PAD_PIN_CGPIO19         (PAD_PIN_CGPIO_BASE + 19)     ///< CGPIO19
+#define PAD_PIN_CGPIO20         (PAD_PIN_CGPIO_BASE + 20)     ///< CGPIO20
+#define PAD_PIN_CGPIO21         (PAD_PIN_CGPIO_BASE + 21)     ///< CGPIO21
+#define PAD_PIN_CGPIO22         (PAD_PIN_CGPIO_BASE + 22)     ///< CGPIO22
+#define PAD_PIN_CGPIO23         (PAD_PIN_CGPIO_BASE + 23)     ///< CGPIO23
+#define PAD_PIN_CGPIO24         (PAD_PIN_CGPIO_BASE + 24)     ///< CGPIO24
+#define PAD_PIN_CGPIO25         (PAD_PIN_CGPIO_BASE + 25)     ///< CGPIO25
+#define PAD_PIN_CGPIO26         (PAD_PIN_CGPIO_BASE + 26)     ///< CGPIO26
+#define PAD_PIN_CGPIO27         (PAD_PIN_CGPIO_BASE + 27)     ///< CGPIO27
+#define PAD_PIN_CGPIO28         (PAD_PIN_CGPIO_BASE + 28)     ///< CGPIO28
+#define PAD_PIN_CGPIO29         (PAD_PIN_CGPIO_BASE + 29)     ///< CGPIO29
+#define PAD_PIN_CGPIO30         (PAD_PIN_CGPIO_BASE + 30)     ///< CGPIO30
+#define PAD_PIN_CGPIO31         (PAD_PIN_CGPIO_BASE + 31)     ///< CGPIO31
+
+#define PAD_PIN_CGPIO32         (PAD_PIN_CGPIO_BASE + 32)     ///< CGPIO32
+#define PAD_PIN_CGPIO33         (PAD_PIN_CGPIO_BASE + 33)     ///< CGPIO33
+//CGPIOx group end
+
+//SGPIOx group begin
+#define PAD_PIN_SGPIO_BASE       100
+#define PAD_PIN_SGPIO0          (PAD_PIN_SGPIO_BASE + 0)      ///< SGPIO0
+#define PAD_PIN_SGPIO1          (PAD_PIN_SGPIO_BASE + 1)      ///< SGPIO1
+#define PAD_PIN_SGPIO2          (PAD_PIN_SGPIO_BASE + 2)      ///< SGPIO2
+#define PAD_PIN_SGPIO3          (PAD_PIN_SGPIO_BASE + 3)      ///< SGPIO3
+#define PAD_PIN_SGPIO4          (PAD_PIN_SGPIO_BASE + 4)      ///< SGPIO4
+#define PAD_PIN_SGPIO5          (PAD_PIN_SGPIO_BASE + 5)      ///< SGPIO5
+#define PAD_PIN_SGPIO6          (PAD_PIN_SGPIO_BASE + 6)      ///< SGPIO6
+#define PAD_PIN_SGPIO7          (PAD_PIN_SGPIO_BASE + 7)      ///< SGPIO7
+#define PAD_PIN_SGPIO8          (PAD_PIN_SGPIO_BASE + 8)      ///< SGPIO8
+#define PAD_PIN_SGPIO9          (PAD_PIN_SGPIO_BASE + 9)      ///< SGPIO9
+#define PAD_PIN_SGPIO10         (PAD_PIN_SGPIO_BASE + 10)     ///< SGPIO10
+#define PAD_PIN_SGPIO11         (PAD_PIN_SGPIO_BASE + 11)     ///< SGPIO11
+//SGPIOx group end
+
+//PGPIOx group begin
+#define PAD_PIN_PGPIO_BASE       150
+#define PAD_PIN_PGPIO0          (PAD_PIN_PGPIO_BASE + 0)      ///< PGPIO0
+#define PAD_PIN_PGPIO1          (PAD_PIN_PGPIO_BASE + 1)      ///< PGPIO1
+#define PAD_PIN_PGPIO2          (PAD_PIN_PGPIO_BASE + 2)      ///< PGPIO2
+#define PAD_PIN_PGPIO3          (PAD_PIN_PGPIO_BASE + 3)      ///< PGPIO3
+#define PAD_PIN_PGPIO4          (PAD_PIN_PGPIO_BASE + 4)      ///< PGPIO4
+#define PAD_PIN_PGPIO5          (PAD_PIN_PGPIO_BASE + 5)      ///< PGPIO5
+#define PAD_PIN_PGPIO6          (PAD_PIN_PGPIO_BASE + 6)      ///< PGPIO6
+#define PAD_PIN_PGPIO7          (PAD_PIN_PGPIO_BASE + 7)      ///< PGPIO7
+#define PAD_PIN_PGPIO8          (PAD_PIN_PGPIO_BASE + 8)      ///< PGPIO8
+#define PAD_PIN_PGPIO9          (PAD_PIN_PGPIO_BASE + 9)      ///< PGPIO9
+#define PAD_PIN_PGPIO10         (PAD_PIN_PGPIO_BASE + 10)     ///< PGPIO10
+#define PAD_PIN_PGPIO11         (PAD_PIN_PGPIO_BASE + 11)     ///< PGPIO11
+#define PAD_PIN_PGPIO12         (PAD_PIN_PGPIO_BASE + 12)     ///< PGPIO12
+#define PAD_PIN_PGPIO13         (PAD_PIN_PGPIO_BASE + 13)     ///< PGPIO13
+#define PAD_PIN_PGPIO14         (PAD_PIN_PGPIO_BASE + 14)     ///< PGPIO14
+#define PAD_PIN_PGPIO15         (PAD_PIN_PGPIO_BASE + 15)     ///< PGPIO15
+
+#define PAD_PIN_PGPIO16         (PAD_PIN_PGPIO_BASE + 16)     ///< PGPIO16
+#define PAD_PIN_PGPIO17         (PAD_PIN_PGPIO_BASE + 17)     ///< PGPIO17
+#define PAD_PIN_PGPIO18         (PAD_PIN_PGPIO_BASE + 18)     ///< PGPIO18
+#define PAD_PIN_PGPIO19         (PAD_PIN_PGPIO_BASE + 19)     ///< PGPIO19
+#define PAD_PIN_PGPIO20         (PAD_PIN_PGPIO_BASE + 20)     ///< PGPIO20
+#define PAD_PIN_PGPIO21         (PAD_PIN_PGPIO_BASE + 21)     ///< PGPIO21
+#define PAD_PIN_PGPIO22         (PAD_PIN_PGPIO_BASE + 22)     ///< PGPIO22
+#define PAD_PIN_PGPIO23         (PAD_PIN_PGPIO_BASE + 23)     ///< PGPIO23
+#define PAD_PIN_PGPIO24         (PAD_PIN_PGPIO_BASE + 24)     ///< PGPIO24
+#define PAD_PIN_PGPIO25         (PAD_PIN_PGPIO_BASE + 25)     ///< PGPIO25
+#define PAD_PIN_PGPIO26         (PAD_PIN_PGPIO_BASE + 26)     ///< PGPIO26
+#define PAD_PIN_PGPIO27         (PAD_PIN_PGPIO_BASE + 27)     ///< PGPIO27
+#define PAD_PIN_PGPIO28         (PAD_PIN_PGPIO_BASE + 28)     ///< PGPIO28
+#define PAD_PIN_PGPIO29         (PAD_PIN_PGPIO_BASE + 29)     ///< PGPIO29
+#define PAD_PIN_PGPIO30         (PAD_PIN_PGPIO_BASE + 30)     ///< PGPIO30
+#define PAD_PIN_PGPIO31         (PAD_PIN_PGPIO_BASE + 31)     ///< PGPIO31
+
+#define PAD_PIN_PGPIO32         (PAD_PIN_PGPIO_BASE + 32)     ///< PGPIO32
+#define PAD_PIN_PGPIO33         (PAD_PIN_PGPIO_BASE + 33)     ///< PGPIO33
+#define PAD_PIN_PGPIO34         (PAD_PIN_PGPIO_BASE + 34)     ///< PGPIO34
+#define PAD_PIN_PGPIO35         (PAD_PIN_PGPIO_BASE + 35)     ///< PGPIO35
+#define PAD_PIN_PGPIO36         (PAD_PIN_PGPIO_BASE + 36)     ///< PGPIO36
+#define PAD_PIN_PGPIO37         (PAD_PIN_PGPIO_BASE + 37)     ///< PGPIO37
+#define PAD_PIN_PGPIO38         (PAD_PIN_PGPIO_BASE + 38)     ///< PGPIO38
+#define PAD_PIN_PGPIO39         (PAD_PIN_PGPIO_BASE + 39)     ///< PGPIO39
+#define PAD_PIN_PGPIO40         (PAD_PIN_PGPIO_BASE + 40)     ///< PGPIO40
+#define PAD_PIN_PGPIO41         (PAD_PIN_PGPIO_BASE + 41)     ///< PGPIO41
+#define PAD_PIN_PGPIO42         (PAD_PIN_PGPIO_BASE + 42)     ///< PGPIO42
+#define PAD_PIN_PGPIO43         (PAD_PIN_PGPIO_BASE + 43)     ///< PGPIO43
+#define PAD_PIN_PGPIO44         (PAD_PIN_PGPIO_BASE + 44)     ///< PGPIO44
+#define PAD_PIN_PGPIO45         (PAD_PIN_PGPIO_BASE + 45)     ///< PGPIO45
+#define PAD_PIN_PGPIO46         (PAD_PIN_PGPIO_BASE + 46)     ///< PGPIO46
+#define PAD_PIN_PGPIO47         (PAD_PIN_PGPIO_BASE + 47)     ///< PGPIO47
+//PGPIOx group end
+
+
+//LGPIOx group begin
+#define PAD_PIN_LGPIO_BASE      250
+#define PAD_PIN_LGPIO0          (PAD_PIN_LGPIO_BASE + 0)       ///< LGPIO0
+#define PAD_PIN_LGPIO1          (PAD_PIN_LGPIO_BASE + 1)       ///< LGPIO1
+#define PAD_PIN_LGPIO2          (PAD_PIN_LGPIO_BASE + 2)       ///< LGPIO2
+#define PAD_PIN_LGPIO3          (PAD_PIN_LGPIO_BASE + 3)       ///< LGPIO3
+#define PAD_PIN_LGPIO4          (PAD_PIN_LGPIO_BASE + 4)       ///< LGPIO4
+#define PAD_PIN_LGPIO5          (PAD_PIN_LGPIO_BASE + 5)       ///< LGPIO5
+#define PAD_PIN_LGPIO6          (PAD_PIN_LGPIO_BASE + 6)       ///< LGPIO6
+#define PAD_PIN_LGPIO7          (PAD_PIN_LGPIO_BASE + 7)       ///< LGPIO7
+#define PAD_PIN_LGPIO8          (PAD_PIN_LGPIO_BASE + 8)       ///< LGPIO8
+#define PAD_PIN_LGPIO9          (PAD_PIN_LGPIO_BASE + 9)       ///< LGPIO9
+#define PAD_PIN_LGPIO10         (PAD_PIN_LGPIO_BASE + 10)      ///< LGPIO10
+#define PAD_PIN_LGPIO11         (PAD_PIN_LGPIO_BASE + 11)      ///< LGPIO11
+#define PAD_PIN_LGPIO12         (PAD_PIN_LGPIO_BASE + 12)      ///< LGPIO12
+#define PAD_PIN_LGPIO13         (PAD_PIN_LGPIO_BASE + 13)      ///< LGPIO13
+#define PAD_PIN_LGPIO14         (PAD_PIN_LGPIO_BASE + 14)      ///< LGPIO14
+#define PAD_PIN_LGPIO15         (PAD_PIN_LGPIO_BASE + 15)      ///< LGPIO15
+
+#define PAD_PIN_LGPIO16         (PAD_PIN_LGPIO_BASE + 16)      ///< LGPIO16
+#define PAD_PIN_LGPIO17         (PAD_PIN_LGPIO_BASE + 17)      ///< LGPIO17
+#define PAD_PIN_LGPIO18         (PAD_PIN_LGPIO_BASE + 18)      ///< LGPIO18
+#define PAD_PIN_LGPIO19         (PAD_PIN_LGPIO_BASE + 19)      ///< LGPIO19
+#define PAD_PIN_LGPIO20         (PAD_PIN_LGPIO_BASE + 20)      ///< LGPIO20
+#define PAD_PIN_LGPIO21         (PAD_PIN_LGPIO_BASE + 21)      ///< LGPIO21
+#define PAD_PIN_LGPIO22         (PAD_PIN_LGPIO_BASE + 22)      ///< LGPIO22
+#define PAD_PIN_LGPIO23         (PAD_PIN_LGPIO_BASE + 23)      ///< LGPIO23
+#define PAD_PIN_LGPIO24         (PAD_PIN_LGPIO_BASE + 24)      ///< LGPIO24
+#define PAD_PIN_LGPIO25         (PAD_PIN_LGPIO_BASE + 25)      ///< LGPIO25
+#define PAD_PIN_LGPIO26         (PAD_PIN_LGPIO_BASE + 26)      ///< LGPIO26
+#define PAD_PIN_LGPIO27         (PAD_PIN_LGPIO_BASE + 27)      ///< LGPIO27
+#define PAD_PIN_LGPIO28         (PAD_PIN_LGPIO_BASE + 28)      ///< LGPIO28
+#define PAD_PIN_LGPIO29         (PAD_PIN_LGPIO_BASE + 29)      ///< LGPIO29
+#define PAD_PIN_LGPIO30         (PAD_PIN_LGPIO_BASE + 30)      ///< LGPIO30
+#define PAD_PIN_LGPIO31         (PAD_PIN_LGPIO_BASE + 31)      ///< LGPIO31
+#define PAD_PIN_LGPIO32         (PAD_PIN_LGPIO_BASE + 32)      ///< LGPIO32
+//LGPIOx group end
+
+//DGPIO group begin
+#define PAD_PIN_DGPIO_BASE      300
+#define PAD_PIN_DGPIO0          (PAD_PIN_DGPIO_BASE + 0)       ///< DGPIO0
+#define PAD_PIN_DGPIO1          (PAD_PIN_DGPIO_BASE + 1)       ///< DGPIO1
+#define PAD_PIN_DGPIO2          (PAD_PIN_DGPIO_BASE + 2)       ///< DGPIO2
+#define PAD_PIN_DGPIO3          (PAD_PIN_DGPIO_BASE + 3)       ///< DGPIO3
+#define PAD_PIN_DGPIO4          (PAD_PIN_DGPIO_BASE + 4)       ///< DGPIO4
+#define PAD_PIN_DGPIO5          (PAD_PIN_DGPIO_BASE + 5)       ///< DGPIO5
+#define PAD_PIN_DGPIO6          (PAD_PIN_DGPIO_BASE + 6)       ///< DGPIO6
+#define PAD_PIN_DGPIO7          (PAD_PIN_DGPIO_BASE + 7)       ///< DGPIO7
+#define PAD_PIN_DGPIO8          (PAD_PIN_DGPIO_BASE + 8)       ///< DGPIO8
+#define PAD_PIN_DGPIO9          (PAD_PIN_DGPIO_BASE + 9)       ///< DGPIO9
+#define PAD_PIN_DGPIO10         (PAD_PIN_DGPIO_BASE + 10)      ///< DGPIO10
+#define PAD_PIN_DGPIO11         (PAD_PIN_DGPIO_BASE + 11)      ///< DGPIO11
+#define PAD_PIN_DGPIO12         (PAD_PIN_DGPIO_BASE + 12)      ///< DGPIO12
+//DGPIO group end
+
+//@}
+
+
+
+#define PAD_DS_GROUP4_10        0x0000
+#define PAD_DS_GROUP6_16        0x1000
+#define PAD_DS_GROUP8           0x2000
+#define PAD_DS_GROUP16          0x4000
+#define PAD_DS_GROUP5_40        0x8000
+
+/**
+    @name Pad driving pin ID.
+
+    Pad driving pin ID.
+
+    Pad ID of pad_setDrivingSink()
+*/
+//@{
+//CGPIO group begin
+#define PAD_DS_CGPIO_BASE      0
+#define PAD_DS_CGPIO0          (PAD_DS_CGPIO_BASE + 0)      ///< CGPIO0
+#define PAD_DS_CGPIO1          (PAD_DS_CGPIO_BASE + 1)      ///< CGPIO1
+#define PAD_DS_CGPIO2          (PAD_DS_CGPIO_BASE + 2)      ///< CGPIO2
+#define PAD_DS_CGPIO3          (PAD_DS_CGPIO_BASE + 3)      ///< CGPIO3
+#define PAD_DS_CGPIO4          (PAD_DS_CGPIO_BASE + 4)      ///< CGPIO4
+#define PAD_DS_CGPIO5          (PAD_DS_CGPIO_BASE + 5)      ///< CGPIO5
+#define PAD_DS_CGPIO6          (PAD_DS_CGPIO_BASE + 6)      ///< CGPIO6
+#define PAD_DS_CGPIO7          (PAD_DS_CGPIO_BASE + 7)      ///< CGPIO7
+#define PAD_DS_CGPIO8          (PAD_DS_CGPIO_BASE + 8)      ///< CGPIO8
+#define PAD_DS_CGPIO9          ((PAD_DS_CGPIO_BASE + 9) | PAD_DS_GROUP6_16)      ///< CGPIO9
+#define PAD_DS_CGPIO10         (PAD_DS_CGPIO_BASE + 10)     ///< CGPIO10
+#define PAD_DS_CGPIO11         (PAD_DS_CGPIO_BASE + 11)     ///< CGPIO11
+#define PAD_DS_CGPIO12         (PAD_DS_CGPIO_BASE + 12)     ///< CGPIO12
+#define PAD_DS_CGPIO13         (PAD_DS_CGPIO_BASE + 13)     ///< CGPIO13
+#define PAD_DS_CGPIO14         (PAD_DS_CGPIO_BASE + 14)     ///< CGPIO14
+#define PAD_DS_CGPIO15         (PAD_DS_CGPIO_BASE + 15)     ///< CGPIO15
+
+#define PAD_DS_CGPIO16         ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP5_40)     ///< CGPIO16
+#define PAD_DS_CGPIO17         ((PAD_DS_CGPIO_BASE + 17) | PAD_DS_GROUP5_40)     ///< CGPIO17
+#define PAD_DS_CGPIO18         ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP5_40)     ///< CGPIO18
+#define PAD_DS_CGPIO19         ((PAD_DS_CGPIO_BASE + 19) | PAD_DS_GROUP5_40)     ///< CGPIO19
+#define PAD_DS_CGPIO20         ((PAD_DS_CGPIO_BASE + 20) | PAD_DS_GROUP5_40)     ///< CGPIO20
+#define PAD_DS_CGPIO21         ((PAD_DS_CGPIO_BASE + 21) | PAD_DS_GROUP5_40)     ///< CGPIO21
+#define PAD_DS_CGPIO22         ((PAD_DS_CGPIO_BASE + 22) | PAD_DS_GROUP5_40)     ///< CGPIO22
+#define PAD_DS_CGPIO23         ((PAD_DS_CGPIO_BASE + 23) | PAD_DS_GROUP5_40)     ///< CGPIO23
+#define PAD_DS_CGPIO24         ((PAD_DS_CGPIO_BASE + 24) | PAD_DS_GROUP5_40)     ///< CGPIO24
+#define PAD_DS_CGPIO25         ((PAD_DS_CGPIO_BASE + 25) | PAD_DS_GROUP5_40)     ///< CGPIO25
+#define PAD_DS_CGPIO26         ((PAD_DS_CGPIO_BASE + 26) | PAD_DS_GROUP5_40)     ///< CGPIO26
+#define PAD_DS_CGPIO27         ((PAD_DS_CGPIO_BASE + 27) | PAD_DS_GROUP5_40)     ///< CGPIO27
+#define PAD_DS_CGPIO28         ((PAD_DS_CGPIO_BASE + 28) | PAD_DS_GROUP6_16)     ///< CGPIO28
+#define PAD_DS_CGPIO29         (PAD_DS_CGPIO_BASE + 29)     ///< CGPIO29
+#define PAD_DS_CGPIO30         (PAD_DS_CGPIO_BASE + 30)     ///< CGPIO30
+#define PAD_DS_CGPIO31         (PAD_DS_CGPIO_BASE + 31)     ///< CGPIO31
+
+#define PAD_DS_CGPIO32         (PAD_DS_CGPIO_BASE + 32)     ///< CGPIO32
+#define PAD_DS_CGPIO33         (PAD_DS_CGPIO_BASE + 33)     ///< CGPIO33
+//CGPIO group end
+
+//SGPIO group Driving/Sink begin
+#define PAD_DS_SGPIO_BASE      48
+#define PAD_DS_SGPIO0          ((PAD_DS_SGPIO_BASE + 0) | PAD_DS_GROUP6_16)      ///< SGPIO0
+#define PAD_DS_SGPIO1          ((PAD_DS_SGPIO_BASE + 1) | PAD_DS_GROUP8)         ///< SGPIO1
+#define PAD_DS_SGPIO2          ((PAD_DS_SGPIO_BASE + 2) | PAD_DS_GROUP8)         ///< SGPIO2
+#define PAD_DS_SGPIO3          ((PAD_DS_SGPIO_BASE + 3) | PAD_DS_GROUP8)         ///< SGPIO3
+#define PAD_DS_SGPIO4          ((PAD_DS_SGPIO_BASE + 4) | PAD_DS_GROUP8)         ///< SGPIO4
+#define PAD_DS_SGPIO5          ((PAD_DS_SGPIO_BASE + 5) | PAD_DS_GROUP6_16)      ///< SGPIO5
+#define PAD_DS_SGPIO6          ((PAD_DS_SGPIO_BASE + 6) | PAD_DS_GROUP8)         ///< SGPIO6
+#define PAD_DS_SGPIO7          ((PAD_DS_SGPIO_BASE + 7) | PAD_DS_GROUP8)         ///< SGPIO7
+#define PAD_DS_SGPIO8          (PAD_DS_SGPIO_BASE + 8)      ///< SGPIO8
+#define PAD_DS_SGPIO9          (PAD_DS_SGPIO_BASE + 9)      ///< SGPIO9
+#define PAD_DS_SGPIO10         (PAD_DS_SGPIO_BASE + 10)     ///< SGPIO10
+#define PAD_DS_SGPIO11         (PAD_DS_SGPIO_BASE + 11)     ///< SGPIO11
+//SGPIO group Driving/Sink end
+
+//PGPIO group Driving/Sink begin
+#define PAD_DS_PGPIO_BASE      64
+#define PAD_DS_PGPIO0          (PAD_DS_PGPIO_BASE + 0)      ///< PGPIO0
+#define PAD_DS_PGPIO1          (PAD_DS_PGPIO_BASE + 1)      ///< PGPIO1
+#define PAD_DS_PGPIO2          (PAD_DS_PGPIO_BASE + 2)      ///< PGPIO2
+#define PAD_DS_PGPIO3          (PAD_DS_PGPIO_BASE + 3)      ///< PGPIO3
+#define PAD_DS_PGPIO4          (PAD_DS_PGPIO_BASE + 4)      ///< PGPIO4
+#define PAD_DS_PGPIO5          (PAD_DS_PGPIO_BASE + 5)      ///< PGPIO5
+#define PAD_DS_PGPIO6          (PAD_DS_PGPIO_BASE + 6)      ///< PGPIO6
+#define PAD_DS_PGPIO7          (PAD_DS_PGPIO_BASE + 7)      ///< PGPIO7
+#define PAD_DS_PGPIO8          (PAD_DS_PGPIO_BASE + 8)      ///< PGPIO8
+#define PAD_DS_PGPIO9          (PAD_DS_PGPIO_BASE + 9)      ///< PGPIO9
+#define PAD_DS_PGPIO10         (PAD_DS_PGPIO_BASE + 10)     ///< PGPIO10
+#define PAD_DS_PGPIO11         (PAD_DS_PGPIO_BASE + 11)     ///< PGPIO11
+#define PAD_DS_PGPIO12         (PAD_DS_PGPIO_BASE + 12)     ///< PGPIO12
+#define PAD_DS_PGPIO13         (PAD_DS_PGPIO_BASE + 13)     ///< PGPIO13
+#define PAD_DS_PGPIO14         (PAD_DS_PGPIO_BASE + 14)     ///< PGPIO14
+#define PAD_DS_PGPIO15         (PAD_DS_PGPIO_BASE + 15)     ///< PGPIO15
+
+#define PAD_DS_PGPIO16         (PAD_DS_PGPIO_BASE + 16)     ///< PGPIO16
+#define PAD_DS_PGPIO17         (PAD_DS_PGPIO_BASE + 17)     ///< PGPIO17
+#define PAD_DS_PGPIO18         (PAD_DS_PGPIO_BASE + 18)     ///< PGPIO18
+#define PAD_DS_PGPIO19         (PAD_DS_PGPIO_BASE + 19)     ///< PGPIO19
+#define PAD_DS_PGPIO20         ((PAD_DS_PGPIO_BASE + 20) | PAD_DS_GROUP6_16)     ///< PGPIO20
+#define PAD_DS_PGPIO21         ((PAD_DS_PGPIO_BASE + 21) | PAD_DS_GROUP6_16)     ///< PGPIO21
+#define PAD_DS_PGPIO22         ((PAD_DS_PGPIO_BASE + 22) | PAD_DS_GROUP6_16)     ///< PGPIO22
+#define PAD_DS_PGPIO23         ((PAD_DS_PGPIO_BASE + 23) | PAD_DS_GROUP6_16)     ///< PGPIO23
+#define PAD_DS_PGPIO24         (PAD_DS_PGPIO_BASE + 24)     ///< PGPIO24
+#define PAD_DS_PGPIO25         (PAD_DS_PGPIO_BASE + 25)     ///< PGPIO25
+#define PAD_DS_PGPIO26         (PAD_DS_PGPIO_BASE + 26)     ///< PGPIO26
+#define PAD_DS_PGPIO27         (PAD_DS_PGPIO_BASE + 27)     ///< PGPIO27
+#define PAD_DS_PGPIO28         (PAD_DS_PGPIO_BASE + 28)     ///< PGPIO28
+#define PAD_DS_PGPIO29         (PAD_DS_PGPIO_BASE + 29)     ///< PGPIO29
+#define PAD_DS_PGPIO30         (PAD_DS_PGPIO_BASE + 30)     ///< PGPIO30
+#define PAD_DS_PGPIO31         (PAD_DS_PGPIO_BASE + 31)     ///< PGPIO31
+
+#define PAD_DS_PGPIO32         (PAD_DS_PGPIO_BASE + 32)     ///< PGPIO32
+#define PAD_DS_PGPIO33         (PAD_DS_PGPIO_BASE + 33)     ///< PGPIO33
+#define PAD_DS_PGPIO34         (PAD_DS_PGPIO_BASE + 34)     ///< PGPIO34
+#define PAD_DS_PGPIO35         (PAD_DS_PGPIO_BASE + 35)     ///< PGPIO35
+#define PAD_DS_PGPIO36         (PAD_DS_PGPIO_BASE + 36)     ///< PGPIO36
+#define PAD_DS_PGPIO37         (PAD_DS_PGPIO_BASE + 37)     ///< PGPIO37
+#define PAD_DS_PGPIO38         (PAD_DS_PGPIO_BASE + 38)     ///< PGPIO38
+#define PAD_DS_PGPIO39         (PAD_DS_PGPIO_BASE + 39)     ///< PGPIO39
+#define PAD_DS_PGPIO40         (PAD_DS_PGPIO_BASE + 40)     ///< PGPIO40
+#define PAD_DS_PGPIO41         (PAD_DS_PGPIO_BASE + 41)     ///< PGPIO41
+#define PAD_DS_PGPIO42         ((PAD_DS_PGPIO_BASE + 42) | PAD_DS_GROUP8)     ///< PGPIO42
+#define PAD_DS_PGPIO43         ((PAD_DS_PGPIO_BASE + 43) | PAD_DS_GROUP8)     ///< PGPIO43
+#define PAD_DS_PGPIO44         ((PAD_DS_PGPIO_BASE + 44) | PAD_DS_GROUP8)     ///< PGPIO44
+#define PAD_DS_PGPIO45         ((PAD_DS_PGPIO_BASE + 45) | PAD_DS_GROUP8)     ///< PGPIO45
+#define PAD_DS_PGPIO46         ((PAD_DS_PGPIO_BASE + 46) | PAD_DS_GROUP8)     ///< PGPIO46
+#define PAD_DS_PGPIO47         ((PAD_DS_PGPIO_BASE + 47) | PAD_DS_GROUP8)     ///< PGPIO47
+//PGPIO group Driving/Sink end
+
+//LCD group Driving/Sink begin
+#define PAD_DS_LGPIO_BASE      112
+#define PAD_DS_LGPIO0          ((PAD_DS_LGPIO_BASE + 0) | PAD_DS_GROUP6_16)      ///< LGPIO0
+#define PAD_DS_LGPIO1          ((PAD_DS_LGPIO_BASE + 1) | PAD_DS_GROUP6_16)      ///< LGPIO1
+#define PAD_DS_LGPIO2          ((PAD_DS_LGPIO_BASE + 2) | PAD_DS_GROUP6_16)      ///< LGPIO2
+#define PAD_DS_LGPIO3          ((PAD_DS_LGPIO_BASE + 3) | PAD_DS_GROUP6_16)      ///< LGPIO3
+#define PAD_DS_LGPIO4          ((PAD_DS_LGPIO_BASE + 4) | PAD_DS_GROUP6_16)      ///< LGPIO4
+#define PAD_DS_LGPIO5          ((PAD_DS_LGPIO_BASE + 5) | PAD_DS_GROUP6_16)      ///< LGPIO5
+#define PAD_DS_LGPIO6          ((PAD_DS_LGPIO_BASE + 6) | PAD_DS_GROUP6_16)      ///< LGPIO6
+#define PAD_DS_LGPIO7          ((PAD_DS_LGPIO_BASE + 7) | PAD_DS_GROUP6_16)      ///< LGPIO7
+#define PAD_DS_LGPIO8          ((PAD_DS_LGPIO_BASE + 8) | PAD_DS_GROUP6_16)      ///< LGPIO8
+#define PAD_DS_LGPIO9          ((PAD_DS_LGPIO_BASE + 9) | PAD_DS_GROUP6_16)      ///< LGPIO9
+#define PAD_DS_LGPIO10         ((PAD_DS_LGPIO_BASE + 10)| PAD_DS_GROUP6_16)      ///< LGPIO10
+#define PAD_DS_LGPIO11         ((PAD_DS_LGPIO_BASE + 11)| PAD_DS_GROUP6_16)      ///< LGPIO11
+#define PAD_DS_LGPIO12         ((PAD_DS_LGPIO_BASE + 12)| PAD_DS_GROUP6_16)      ///< LGPIO12
+#define PAD_DS_LGPIO13         ((PAD_DS_LGPIO_BASE + 13)| PAD_DS_GROUP6_16)      ///< LGPIO13
+#define PAD_DS_LGPIO14         ((PAD_DS_LGPIO_BASE + 14)| PAD_DS_GROUP6_16)      ///< LGPIO14
+#define PAD_DS_LGPIO15         ((PAD_DS_LGPIO_BASE + 15)| PAD_DS_GROUP6_16)      ///< LGPIO15
+
+#define PAD_DS_LGPIO16         ((PAD_DS_LGPIO_BASE + 16)| PAD_DS_GROUP6_16)      ///< LGPIO16
+#define PAD_DS_LGPIO17         ((PAD_DS_LGPIO_BASE + 17)| PAD_DS_GROUP6_16)      ///< LGPIO17
+#define PAD_DS_LGPIO18         ((PAD_DS_LGPIO_BASE + 18)| PAD_DS_GROUP6_16)      ///< LGPIO18
+#define PAD_DS_LGPIO19         ((PAD_DS_LGPIO_BASE + 19)| PAD_DS_GROUP6_16)      ///< LGPIO19
+#define PAD_DS_LGPIO20         ((PAD_DS_LGPIO_BASE + 20)| PAD_DS_GROUP6_16)      ///< LGPIO20
+#define PAD_DS_LGPIO21         ((PAD_DS_LGPIO_BASE + 21)| PAD_DS_GROUP6_16)      ///< LGPIO21
+#define PAD_DS_LGPIO22         ((PAD_DS_LGPIO_BASE + 22)| PAD_DS_GROUP6_16)      ///< LGPIO22
+#define PAD_DS_LGPIO23         ((PAD_DS_LGPIO_BASE + 23)| PAD_DS_GROUP6_16)      ///< LGPIO23
+#define PAD_DS_LGPIO24         ((PAD_DS_LGPIO_BASE + 24)| PAD_DS_GROUP6_16)      ///< LGPIO24
+#define PAD_DS_LGPIO25         ((PAD_DS_LGPIO_BASE + 25)| PAD_DS_GROUP6_16)      ///< LGPIO25
+#define PAD_DS_LGPIO26         ((PAD_DS_LGPIO_BASE + 26)| PAD_DS_GROUP6_16)      ///< LGPIO26
+#define PAD_DS_LGPIO27         ((PAD_DS_LGPIO_BASE + 27)| PAD_DS_GROUP6_16)      ///< LGPIO27
+#define PAD_DS_LGPIO28         ((PAD_DS_LGPIO_BASE + 28)| PAD_DS_GROUP6_16)      ///< LGPIO28
+#define PAD_DS_LGPIO29         ((PAD_DS_LGPIO_BASE + 29)| PAD_DS_GROUP6_16)      ///< LGPIO29
+#define PAD_DS_LGPIO30         ((PAD_DS_LGPIO_BASE + 30)| PAD_DS_GROUP4_10)      ///< LGPIO30
+#define PAD_DS_LGPIO31         ((PAD_DS_LGPIO_BASE + 31)| PAD_DS_GROUP4_10)      ///< LGPIO31
+#define PAD_DS_LGPIO32         ((PAD_DS_LGPIO_BASE + 32)| PAD_DS_GROUP4_10)      ///< LGPIO32
+//LCD group Driving/Sink end
+
+//DGPIO group Driving/Sink begin
+#define PAD_DS_DGPIO_BASE      160
+#define PAD_DS_DGPIO0          ((PAD_DS_DGPIO_BASE + 0) | PAD_DS_GROUP16)       ///< DGPIO0
+#define PAD_DS_DGPIO1          ((PAD_DS_DGPIO_BASE + 1) | PAD_DS_GROUP16)       ///< DGPIO1
+#define PAD_DS_DGPIO2          ((PAD_DS_DGPIO_BASE + 2) | PAD_DS_GROUP16)       ///< DGPIO2
+#define PAD_DS_DGPIO3          ((PAD_DS_DGPIO_BASE + 3) | PAD_DS_GROUP16)       ///< DGPIO3
+#define PAD_DS_DGPIO4          ((PAD_DS_DGPIO_BASE + 4) | PAD_DS_GROUP16)       ///< DGPIO4
+#define PAD_DS_DGPIO5          ((PAD_DS_DGPIO_BASE + 5) | PAD_DS_GROUP16)       ///< DGPIO5
+#define PAD_DS_DGPIO6          ((PAD_DS_DGPIO_BASE + 6) | PAD_DS_GROUP8)        ///< DGPIO6
+#define PAD_DS_DGPIO7          ((PAD_DS_DGPIO_BASE + 7) | PAD_DS_GROUP8)        ///< DGPIO7
+#define PAD_DS_DGPIO8          ((PAD_DS_DGPIO_BASE + 8) | PAD_DS_GROUP8)        ///< DGPIO8
+#define PAD_DS_DGPIO9          ((PAD_DS_DGPIO_BASE + 9) | PAD_DS_GROUP8)        ///< DGPIO9
+#define PAD_DS_DGPIO10         ((PAD_DS_DGPIO_BASE + 10)| PAD_DS_GROUP8)        ///< DGPIO10
+#define PAD_DS_DGPIO11         ((PAD_DS_DGPIO_BASE + 11)| PAD_DS_GROUP4_10)     ///< DGPIO11
+#define PAD_DS_DGPIO12         ((PAD_DS_DGPIO_BASE + 12)| PAD_DS_GROUP4_10)     ///< DGPIO12
+//DGPIO group Driving/Sink end
+//@}
+
+#endif
+
+/**
+    @addtogroup mIDrvSys_PAD
+*/
+//@{
+
+
+#define	PAD_C_GPIO_BASE			0
+#define	PAD_S_GPIO_BASE			96
+#define	PAD_P_GPIO_BASE			128
+#define	PAD_L_GPIO_BASE			224
+#define	PAD_D_GPIO_BASE			288
+#define	PAD_H_GPIO_BASE			320
+#define	PAD_A_GPIO_BASE			352
+#define PAD_DS_GROUP_10         0x00000000
+#define PAD_DS_GROUP_16         0x10000000
+#define PAD_DS_GROUP_40         0x80000000
+
+/**
+    @name Pad type pin ID.
+
+    Pad type pin ID.
+
+    Pad ID of pad_set_pull_up_down (), pad_get_pull_up_down ().
+*/
+#define PAD_PIN_NOT_EXIST       (64)                        // For backward compatible
+//@{
+typedef enum {
+
+	//C_GPIO group
+	PAD_PIN_CGPIO0     =     (PAD_C_GPIO_BASE + 0),     ///< C_GPIO_0
+	PAD_PIN_CGPIO1     =     (PAD_C_GPIO_BASE + 2),     ///< C_GPIO_1
+	PAD_PIN_CGPIO2     =     (PAD_C_GPIO_BASE + 4),     ///< C_GPIO_2
+	PAD_PIN_CGPIO3     =     (PAD_C_GPIO_BASE + 6),     ///< C_GPIO_3
+	PAD_PIN_CGPIO4     =     (PAD_C_GPIO_BASE + 8),     ///< C_GPIO_4
+	PAD_PIN_CGPIO5     =     (PAD_C_GPIO_BASE + 10),    ///< C_GPIO_5
+	PAD_PIN_CGPIO6     =     (PAD_C_GPIO_BASE + 12),    ///< C_GPIO_6
+	PAD_PIN_CGPIO7     =     (PAD_C_GPIO_BASE + 14),    ///< C_GPIO_7
+	PAD_PIN_CGPIO8     =     (PAD_C_GPIO_BASE + 16),    ///< C_GPIO_8
+	PAD_PIN_CGPIO9     =     (PAD_C_GPIO_BASE + 18),    ///< C_GPIO_9
+	PAD_PIN_CGPIO10    =     (PAD_C_GPIO_BASE + 20),    ///< C_GPIO_10
+	PAD_PIN_CGPIO11    =     (PAD_C_GPIO_BASE + 22),    ///< C_GPIO_11
+	PAD_PIN_CGPIO12    =     (PAD_C_GPIO_BASE + 24),    ///< C_GPIO_12
+	PAD_PIN_CGPIO13    =     (PAD_C_GPIO_BASE + 26),    ///< C_GPIO_13
+	PAD_PIN_CGPIO14    =     (PAD_C_GPIO_BASE + 28),    ///< C_GPIO_14
+	PAD_PIN_CGPIO15    =     (PAD_C_GPIO_BASE + 30),    ///< C_GPIO_15
+	PAD_PIN_CGPIO16    =     (PAD_C_GPIO_BASE + 32),    ///< C_GPIO_16
+	PAD_PIN_CGPIO17    =     (PAD_C_GPIO_BASE + 34),    ///< C_GPIO_17
+	PAD_PIN_CGPIO18    =     (PAD_C_GPIO_BASE + 36),    ///< C_GPIO_18
+	PAD_PIN_CGPIO19    =     (PAD_C_GPIO_BASE + 38),    ///< C_GPIO_19
+	PAD_PIN_CGPIO20    =     (PAD_C_GPIO_BASE + 40),    ///< C_GPIO_20
+	PAD_PIN_CGPIO21    =     (PAD_C_GPIO_BASE + 42),    ///< C_GPIO_21
+	PAD_PIN_CGPIO22    =     (PAD_C_GPIO_BASE + 44),    ///< C_GPIO_22
+
+	//S_GPIO group
+	PAD_PIN_SGPIO0      =    (PAD_S_GPIO_BASE + 0),     ///< S_GPIO_0
+	PAD_PIN_SGPIO1      =    (PAD_S_GPIO_BASE + 2),     ///< S_GPIO_1
+	PAD_PIN_SGPIO2      =    (PAD_S_GPIO_BASE + 4),     ///< S_GPIO_2
+	PAD_PIN_SGPIO3      =    (PAD_S_GPIO_BASE + 6),     ///< S_GPIO_3
+	PAD_PIN_SGPIO4      =    (PAD_S_GPIO_BASE + 8),     ///< S_GPIO_4
+	PAD_PIN_SGPIO5      =    (PAD_S_GPIO_BASE + 10),    ///< S_GPIO_5
+	PAD_PIN_SGPIO6      =    (PAD_S_GPIO_BASE + 12),    ///< S_GPIO_6
+	PAD_PIN_SGPIO7      =    (PAD_S_GPIO_BASE + 14),    ///< S_GPIO_7
+	PAD_PIN_SGPIO8      =    (PAD_S_GPIO_BASE + 16),    ///< S_GPIO_8
+	PAD_PIN_SGPIO9      =    (PAD_S_GPIO_BASE + 18),    ///< S_GPIO_9
+	PAD_PIN_SGPIO10     =    (PAD_S_GPIO_BASE + 20),    ///< S_GPIO_10
+	PAD_PIN_SGPIO11     =    (PAD_S_GPIO_BASE + 22),    ///< S_GPIO_11
+	PAD_PIN_SGPIO12     =    (PAD_S_GPIO_BASE + 24),    ///< S_GPIO_12
+
+	//P_GPIO group
+	PAD_PIN_PGPIO0      =    (PAD_P_GPIO_BASE + 0),     ///< P_GPIO_0
+	PAD_PIN_PGPIO1      =    (PAD_P_GPIO_BASE + 2),     ///< P_GPIO_1
+	PAD_PIN_PGPIO2      =    (PAD_P_GPIO_BASE + 4),     ///< P_GPIO_2
+	PAD_PIN_PGPIO3      =    (PAD_P_GPIO_BASE + 6),     ///< P_GPIO_3
+	PAD_PIN_PGPIO4      =    (PAD_P_GPIO_BASE + 8),     ///< P_GPIO_4
+	PAD_PIN_PGPIO5      =    (PAD_P_GPIO_BASE + 10),    ///< P_GPIO_5
+	PAD_PIN_PGPIO6      =    (PAD_P_GPIO_BASE + 12),    ///< P_GPIO_6
+	PAD_PIN_PGPIO7      =    (PAD_P_GPIO_BASE + 14),    ///< P_GPIO_7
+	PAD_PIN_PGPIO8      =    (PAD_P_GPIO_BASE + 16),    ///< P_GPIO_8
+	PAD_PIN_PGPIO9      =    (PAD_P_GPIO_BASE + 18),    ///< P_GPIO_9
+	PAD_PIN_PGPIO10     =    (PAD_P_GPIO_BASE + 20),    ///< P_GPIO_10
+	PAD_PIN_PGPIO11     =    (PAD_P_GPIO_BASE + 22),    ///< P_GPIO_11
+	PAD_PIN_PGPIO12     =    (PAD_P_GPIO_BASE + 24),    ///< P_GPIO_12
+	PAD_PIN_PGPIO13     =    (PAD_P_GPIO_BASE + 26),    ///< P_GPIO_13
+	PAD_PIN_PGPIO14     =    (PAD_P_GPIO_BASE + 28),    ///< P_GPIO_14
+	PAD_PIN_PGPIO15     =    (PAD_P_GPIO_BASE + 30),    ///< P_GPIO_15
+	PAD_PIN_PGPIO16     =    (PAD_P_GPIO_BASE + 32),    ///< P_GPIO_16
+	PAD_PIN_PGPIO17     =    (PAD_P_GPIO_BASE + 34),    ///< P_GPIO_17
+	PAD_PIN_PGPIO18     =    (PAD_P_GPIO_BASE + 36),    ///< P_GPIO_18
+	PAD_PIN_PGPIO19     =    (PAD_P_GPIO_BASE + 38),    ///< P_GPIO_19
+	PAD_PIN_PGPIO20     =    (PAD_P_GPIO_BASE + 40),    ///< P_GPIO_20
+	PAD_PIN_PGPIO21     =    (PAD_P_GPIO_BASE + 42),    ///< P_GPIO_21
+	PAD_PIN_PGPIO22     =    (PAD_P_GPIO_BASE + 44),    ///< P_GPIO_22
+	PAD_PIN_PGPIO23     =    (PAD_P_GPIO_BASE + 46),    ///< P_GPIO_23
+	PAD_PIN_PGPIO24     =    (PAD_P_GPIO_BASE + 48),    ///< P_GPIO_24
+
+	//L_GPIO group
+	PAD_PIN_LGPIO0      =    (PAD_L_GPIO_BASE + 0),      ///< L_GPIO_0
+	PAD_PIN_LGPIO1      =    (PAD_L_GPIO_BASE + 2),      ///< L_GPIO_1
+	PAD_PIN_LGPIO2      =    (PAD_L_GPIO_BASE + 4),      ///< L_GPIO_2
+	PAD_PIN_LGPIO3      =    (PAD_L_GPIO_BASE + 6),      ///< L_GPIO_3
+	PAD_PIN_LGPIO4      =    (PAD_L_GPIO_BASE + 8),      ///< L_GPIO_4
+	PAD_PIN_LGPIO5      =    (PAD_L_GPIO_BASE + 10),     ///< L_GPIO_5
+	PAD_PIN_LGPIO6      =    (PAD_L_GPIO_BASE + 12),     ///< L_GPIO_6
+	PAD_PIN_LGPIO7      =    (PAD_L_GPIO_BASE + 14),     ///< L_GPIO_7
+	PAD_PIN_LGPIO8      =    (PAD_L_GPIO_BASE + 16),     ///< L_GPIO_8
+	PAD_PIN_LGPIO9      =    (PAD_L_GPIO_BASE + 18),     ///< L_GPIO_9
+	PAD_PIN_LGPIO10     =    (PAD_L_GPIO_BASE + 20),     ///< L_GPIO_10
+	PAD_PIN_LGPIO11     =    (PAD_L_GPIO_BASE + 22),     ///< L_GPIO_11
+	PAD_PIN_LGPIO12     =    (PAD_L_GPIO_BASE + 24),     ///< L_GPIO_12
+	PAD_PIN_LGPIO13     =    (PAD_L_GPIO_BASE + 26),     ///< L_GPIO_13
+	PAD_PIN_LGPIO14     =    (PAD_L_GPIO_BASE + 28),     ///< L_GPIO_14
+	PAD_PIN_LGPIO15     =    (PAD_L_GPIO_BASE + 30),     ///< L_GPIO_15
+	PAD_PIN_LGPIO16     =    (PAD_L_GPIO_BASE + 32),     ///< L_GPIO_16
+	PAD_PIN_LGPIO17     =    (PAD_L_GPIO_BASE + 34),     ///< L_GPIO_17
+	PAD_PIN_LGPIO18     =    (PAD_L_GPIO_BASE + 36),     ///< L_GPIO_18
+	PAD_PIN_LGPIO19     =    (PAD_L_GPIO_BASE + 38),     ///< L_GPIO_19
+	PAD_PIN_LGPIO20     =    (PAD_L_GPIO_BASE + 40),     ///< L_GPIO_20
+	PAD_PIN_LGPIO21     =    (PAD_L_GPIO_BASE + 42),     ///< L_GPIO_21
+	PAD_PIN_LGPIO22     =    (PAD_L_GPIO_BASE + 44),     ///< L_GPIO_22
+	PAD_PIN_LGPIO23     =    (PAD_L_GPIO_BASE + 46),     ///< L_GPIO_23
+	PAD_PIN_LGPIO24     =    (PAD_L_GPIO_BASE + 48),     ///< L_GPIO_23
+
+	//D_GPIO group
+	PAD_PIN_DGPIO0      =    (PAD_D_GPIO_BASE + 0),      ///< D_GPIO_0
+	PAD_PIN_DGPIO1      =    (PAD_D_GPIO_BASE + 2),      ///< D_GPIO_1
+	PAD_PIN_DGPIO2      =    (PAD_D_GPIO_BASE + 4),      ///< D_GPIO_2
+	PAD_PIN_DGPIO3      =    (PAD_D_GPIO_BASE + 6),      ///< D_GPIO_3
+	PAD_PIN_DGPIO4      =    (PAD_D_GPIO_BASE + 8),      ///< D_GPIO_4
+	PAD_PIN_DGPIO5      =    (PAD_D_GPIO_BASE + 10),     ///< D_GPIO_5
+	PAD_PIN_DGPIO6      =    (PAD_D_GPIO_BASE + 12),     ///< D_GPIO_6
+	PAD_PIN_DGPIO7      =    (PAD_D_GPIO_BASE + 14),     ///< D_GPIO_7
+
+	//HSI_GPIO group
+	PAD_PIN_HSIGPIO0    =    (PAD_H_GPIO_BASE + 0),      ///< HSI_GPIO_0
+	PAD_PIN_HSIGPIO1    =    (PAD_H_GPIO_BASE + 2),      ///< HSI_GPIO_1
+	PAD_PIN_HSIGPIO2    =    (PAD_H_GPIO_BASE + 4),      ///< HSI_GPIO_2
+	PAD_PIN_HSIGPIO3    =    (PAD_H_GPIO_BASE + 6),      ///< HSI_GPIO_3
+	PAD_PIN_HSIGPIO4    =    (PAD_H_GPIO_BASE + 8),      ///< HSI_GPIO_4
+	PAD_PIN_HSIGPIO5    =    (PAD_H_GPIO_BASE + 10),     ///< HSI_GPIO_5
+	PAD_PIN_HSIGPIO6    =    (PAD_H_GPIO_BASE + 12),     ///< HSI_GPIO_6
+	PAD_PIN_HSIGPIO7    =    (PAD_H_GPIO_BASE + 14),     ///< HSI_GPIO_7
+	PAD_PIN_HSIGPIO8    =    (PAD_H_GPIO_BASE + 16),     ///< HSI_GPIO_8
+	PAD_PIN_HSIGPIO9    =    (PAD_H_GPIO_BASE + 18),     ///< HSI_GPIO_9
+	PAD_PIN_HSIGPIO10   =    (PAD_H_GPIO_BASE + 20),     ///< HSI_GPIO_10
+	PAD_PIN_HSIGPIO11   =    (PAD_H_GPIO_BASE + 22),     ///< HSI_GPIO_11
+
+	//A_GPIO group
+	PAD_PIN_AGPIO0      =    (PAD_A_GPIO_BASE + 0),      ///< A_GPIO_0
+	PAD_PIN_AGPIO1      =    (PAD_A_GPIO_BASE + 2),      ///< A_GPIO_1
+	PAD_PIN_AGPIO2      =    (PAD_A_GPIO_BASE + 4),      ///< A_GPIO_2
+
+	PAD_PIN_MAX			=     PAD_PIN_AGPIO2,
+	ENUM_DUMMY4WORD(PAD_PIN)
+} PAD_PIN;
+//@}
+
+/**
+    Pad type select
+
+    Pad type select
+
+    Pad type value for pad_set_pull_up_down(), pad_get_pull_up_down().
+*/
+typedef enum {
+	PAD_NONE         =          0x00,      ///< none of pull up/down
+	PAD_PULLDOWN     =          0x01,      ///< pull down
+	PAD_PULLUP       =          0x02,      ///< pull up
+	PAD_KEEPER       =          0x03,      ///< keeper
+
+	ENUM_DUMMY4WORD(PAD_PULL)
+} PAD_PULL;
+
+/**
+    Pad driving select
+
+    Pad driving select
+
+    Pad driving value for pad_set_driving_sink(), pad_get_driving_sink().
+*/
+typedef enum {
+	PAD_DRIVINGSINK_4MA		=   0x0001,			///< Pad driver/sink 4mA
+	PAD_DRIVINGSINK_10MA	=   0x0202,			///< Pad driver/sink 10mA
+
+	PAD_DRIVINGSINK_6MA		=   0x0010,			///< Pad driver/sink 6mA
+	PAD_DRIVINGSINK_16MA	=   0x0020,			///< Pad driver/sink 16mA
+
+	PAD_DRIVINGSINK_5MA		=   0x0100,			///< Pad driver/sink 5mA
+	PAD_DRIVINGSINK_15MA	=   0x0400,			///< Pad driver/sink 15mA
+	PAD_DRIVINGSINK_20MA	=   0x0800,			///< Pad driver/sink 20mA
+	PAD_DRIVINGSINK_25MA	=   0x1000,			///< Pad driver/sink 25mA
+	PAD_DRIVINGSINK_30MA	=   0x2000,			///< Pad driver/sink 30mA
+	PAD_DRIVINGSINK_35MA	=   0x4000,			///< Pad driver/sink 35mA
+	PAD_DRIVINGSINK_40MA	=   0x8000,			///< Pad driver/sink 40mA
+
+	ENUM_DUMMY4WORD(PAD_DRIVINGSINK)
+} PAD_DRIVINGSINK;
+
+/**
+    @name Pad driving pin ID.
+
+    Pad driving pin ID.
+
+    Pad ID of pad_set_driving_sink(), pad_get_driving_sink()
+*/
+//@{
+typedef enum {
+
+	//C_GPIO group
+	PAD_DS_CGPIO0     =		((PAD_C_GPIO_BASE +  0)		| PAD_DS_GROUP_10), ///< C_GPIO_0
+	PAD_DS_CGPIO1     =     ((PAD_C_GPIO_BASE +  2)		| PAD_DS_GROUP_10), ///< C_GPIO_1
+	PAD_DS_CGPIO2     =		((PAD_C_GPIO_BASE +  4)		| PAD_DS_GROUP_10), ///< C_GPIO_2
+	PAD_DS_CGPIO3     =     ((PAD_C_GPIO_BASE +  6)		| PAD_DS_GROUP_10), ///< C_GPIO_3
+	PAD_DS_CGPIO4     =     ((PAD_C_GPIO_BASE +  8)		| PAD_DS_GROUP_10), ///< C_GPIO_4
+	PAD_DS_CGPIO5     =     ((PAD_C_GPIO_BASE + 10)		| PAD_DS_GROUP_10), ///< C_GPIO_5
+	PAD_DS_CGPIO6     =     ((PAD_C_GPIO_BASE + 12)		| PAD_DS_GROUP_10), ///< C_GPIO_6
+	PAD_DS_CGPIO7     =     ((PAD_C_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< C_GPIO_7
+	PAD_DS_CGPIO8     =		((PAD_C_GPIO_BASE + 16)		| PAD_DS_GROUP_16),	///< C_GPIO_8
+	PAD_DS_CGPIO9     =     ((PAD_C_GPIO_BASE + 18)		| PAD_DS_GROUP_10), ///< C_GPIO_9
+	PAD_DS_CGPIO10    =     ((PAD_C_GPIO_BASE + 20)		| PAD_DS_GROUP_10), ///< C_GPIO_10
+	PAD_DS_CGPIO11    =     ((PAD_C_GPIO_BASE + 0)		| PAD_DS_GROUP_40), ///< C_GPIO_11
+	PAD_DS_CGPIO12    =		((PAD_C_GPIO_BASE + 4)		| PAD_DS_GROUP_40), ///< C_GPIO_12
+	PAD_DS_CGPIO13    =		((PAD_C_GPIO_BASE + 8)		| PAD_DS_GROUP_40), ///< C_GPIO_13
+	PAD_DS_CGPIO14    =		((PAD_C_GPIO_BASE + 12)		| PAD_DS_GROUP_40), ///< C_GPIO_14
+	PAD_DS_CGPIO15    =		((PAD_C_GPIO_BASE + 16)		| PAD_DS_GROUP_40), ///< C_GPIO_15
+	PAD_DS_CGPIO16    =		((PAD_C_GPIO_BASE + 20)		| PAD_DS_GROUP_40), ///< C_GPIO_16
+	PAD_DS_CGPIO17    =		((PAD_C_GPIO_BASE + 24)		| PAD_DS_GROUP_40), ///< C_GPIO_17
+	PAD_DS_CGPIO18    =		((PAD_C_GPIO_BASE + 36)		| PAD_DS_GROUP_16), ///< C_GPIO_18
+	PAD_DS_CGPIO19    =		((PAD_C_GPIO_BASE + 38)		| PAD_DS_GROUP_16), ///< C_GPIO_19
+	PAD_DS_CGPIO20    =		((PAD_C_GPIO_BASE + 40)		| PAD_DS_GROUP_16), ///< C_GPIO_20
+	PAD_DS_CGPIO21    =		((PAD_C_GPIO_BASE + 42)		| PAD_DS_GROUP_16), ///< C_GPIO_21
+	PAD_DS_CGPIO22    =		((PAD_C_GPIO_BASE + 44)		| PAD_DS_GROUP_16), ///< C_GPIO_22
+
+	//S_GPIO group
+	PAD_DS_SGPIO0     =     ((PAD_S_GPIO_BASE + 0)		| PAD_DS_GROUP_16), ///< S_GPIO_0
+	PAD_DS_SGPIO1     =		((PAD_S_GPIO_BASE + 2)		| PAD_DS_GROUP_16), ///< S_GPIO_1
+	PAD_DS_SGPIO2     =		((PAD_S_GPIO_BASE + 4)		| PAD_DS_GROUP_10), ///< S_GPIO_2
+	PAD_DS_SGPIO3     =		((PAD_S_GPIO_BASE + 6)		| PAD_DS_GROUP_10), ///< S_GPIO_3
+	PAD_DS_SGPIO4     =		((PAD_S_GPIO_BASE + 8)		| PAD_DS_GROUP_10), ///< S_GPIO_4
+	PAD_DS_SGPIO5     =		((PAD_S_GPIO_BASE + 10)		| PAD_DS_GROUP_16), ///< S_GPIO_5
+	PAD_DS_SGPIO6     =		((PAD_S_GPIO_BASE + 12)		| PAD_DS_GROUP_10), ///< S_GPIO_6
+	PAD_DS_SGPIO7     =		((PAD_S_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< S_GPIO_7
+	PAD_DS_SGPIO8     =		((PAD_S_GPIO_BASE + 16)		| PAD_DS_GROUP_10), ///< S_GPIO_8
+	PAD_DS_SGPIO9     =		((PAD_S_GPIO_BASE + 18)		| PAD_DS_GROUP_10), ///< S_GPIO_9
+	PAD_DS_SGPIO10    =		((PAD_S_GPIO_BASE + 20)		| PAD_DS_GROUP_10), ///< S_GPIO_10
+	PAD_DS_SGPIO11    =		((PAD_S_GPIO_BASE + 22)		| PAD_DS_GROUP_10), ///< S_GPIO_11
+	PAD_DS_SGPIO12    =		((PAD_S_GPIO_BASE + 24)		| PAD_DS_GROUP_10), ///< S_GPIO_12
+
+	//P_GPIO group
+	PAD_DS_PGPIO0     =     ((PAD_P_GPIO_BASE + 0)		| PAD_DS_GROUP_10), ///< P_GPIO_0
+	PAD_DS_PGPIO1     =     ((PAD_P_GPIO_BASE + 2)		| PAD_DS_GROUP_10), ///< P_GPIO_1
+	PAD_DS_PGPIO2     =     ((PAD_P_GPIO_BASE + 4)		| PAD_DS_GROUP_10), ///< P_GPIO_2
+	PAD_DS_PGPIO3     =     ((PAD_P_GPIO_BASE + 6)		| PAD_DS_GROUP_10), ///< P_GPIO_3
+	PAD_DS_PGPIO4     =     ((PAD_P_GPIO_BASE + 8)		| PAD_DS_GROUP_10), ///< P_GPIO_4
+	PAD_DS_PGPIO5     =     ((PAD_P_GPIO_BASE + 10)		| PAD_DS_GROUP_10), ///< P_GPIO_5
+	PAD_DS_PGPIO6     =     ((PAD_P_GPIO_BASE + 12)		| PAD_DS_GROUP_10), ///< P_GPIO_6
+	PAD_DS_PGPIO7     =     ((PAD_P_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< P_GPIO_7
+	PAD_DS_PGPIO8     =     ((PAD_P_GPIO_BASE + 16)		| PAD_DS_GROUP_16), ///< P_GPIO_8
+	PAD_DS_PGPIO9     =     ((PAD_P_GPIO_BASE + 18)		| PAD_DS_GROUP_10), ///< P_GPIO_9
+	PAD_DS_PGPIO10    =     ((PAD_P_GPIO_BASE + 20)		| PAD_DS_GROUP_10), ///< P_GPIO_10
+	PAD_DS_PGPIO11    =     ((PAD_P_GPIO_BASE + 22)		| PAD_DS_GROUP_10), ///< P_GPIO_11
+	PAD_DS_PGPIO12    =     ((PAD_P_GPIO_BASE + 24)		| PAD_DS_GROUP_10), ///< P_GPIO_12
+	PAD_DS_PGPIO13    =     ((PAD_P_GPIO_BASE + 26)		| PAD_DS_GROUP_10), ///< P_GPIO_13
+	PAD_DS_PGPIO14    =     ((PAD_P_GPIO_BASE + 28)		| PAD_DS_GROUP_10), ///< P_GPIO_14
+	PAD_DS_PGPIO15    =     ((PAD_P_GPIO_BASE + 30)		| PAD_DS_GROUP_10), ///< P_GPIO_15
+	PAD_DS_PGPIO16    =     ((PAD_P_GPIO_BASE + 32)		| PAD_DS_GROUP_10), ///< P_GPIO_16
+	PAD_DS_PGPIO17    =     ((PAD_P_GPIO_BASE + 34)		| PAD_DS_GROUP_10), ///< P_GPIO_17
+	PAD_DS_PGPIO18    =     ((PAD_P_GPIO_BASE + 36)		| PAD_DS_GROUP_10), ///< P_GPIO_18
+	PAD_DS_PGPIO19    =     ((PAD_P_GPIO_BASE + 38)		| PAD_DS_GROUP_10), ///< P_GPIO_19
+	PAD_DS_PGPIO20    =     ((PAD_P_GPIO_BASE + 40)		| PAD_DS_GROUP_10), ///< P_GPIO_20
+	PAD_DS_PGPIO21    =     ((PAD_P_GPIO_BASE + 42)		| PAD_DS_GROUP_10), ///< P_GPIO_21
+	PAD_DS_PGPIO22    =     ((PAD_P_GPIO_BASE + 44)		| PAD_DS_GROUP_10), ///< P_GPIO_22
+	PAD_DS_PGPIO23    =     ((PAD_P_GPIO_BASE + 46)		| PAD_DS_GROUP_10), ///< P_GPIO_23
+	PAD_DS_PGPIO24    =     ((PAD_P_GPIO_BASE + 48)		| PAD_DS_GROUP_10), ///< P_GPIO_24
+
+	//L_GPIO group
+	PAD_DS_LGPIO0     =     ((PAD_L_GPIO_BASE + 0)		| PAD_DS_GROUP_10), ///< L_GPIO_0
+	PAD_DS_LGPIO1     =     ((PAD_L_GPIO_BASE + 2)		| PAD_DS_GROUP_10), ///< L_GPIO_1
+	PAD_DS_LGPIO2     =     ((PAD_L_GPIO_BASE + 4)		| PAD_DS_GROUP_10), ///< L_GPIO_2
+	PAD_DS_LGPIO3     =     ((PAD_L_GPIO_BASE + 6)		| PAD_DS_GROUP_10), ///< L_GPIO_3
+	PAD_DS_LGPIO4     =     ((PAD_L_GPIO_BASE + 8)		| PAD_DS_GROUP_10), ///< L_GPIO_4
+	PAD_DS_LGPIO5     =     ((PAD_L_GPIO_BASE + 10)		| PAD_DS_GROUP_10), ///< L_GPIO_5
+	PAD_DS_LGPIO6     =     ((PAD_L_GPIO_BASE + 12)		| PAD_DS_GROUP_10), ///< L_GPIO_6
+	PAD_DS_LGPIO7     =     ((PAD_L_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< L_GPIO_7
+	PAD_DS_LGPIO8     =     ((PAD_L_GPIO_BASE + 16)		| PAD_DS_GROUP_16), ///< L_GPIO_8
+	PAD_DS_LGPIO9     =     ((PAD_L_GPIO_BASE + 18)		| PAD_DS_GROUP_10), ///< L_GPIO_9
+	PAD_DS_LGPIO10    =     ((PAD_L_GPIO_BASE + 20)		| PAD_DS_GROUP_10), ///< L_GPIO_10
+	PAD_DS_LGPIO11    =     ((PAD_L_GPIO_BASE + 22)		| PAD_DS_GROUP_10), ///< L_GPIO_11
+	PAD_DS_LGPIO12    =     ((PAD_L_GPIO_BASE + 24)		| PAD_DS_GROUP_10), ///< L_GPIO_12
+	PAD_DS_LGPIO13    =     ((PAD_L_GPIO_BASE + 26)		| PAD_DS_GROUP_10), ///< L_GPIO_13
+	PAD_DS_LGPIO14    =     ((PAD_L_GPIO_BASE + 28)		| PAD_DS_GROUP_10), ///< L_GPIO_14
+	PAD_DS_LGPIO15    =     ((PAD_L_GPIO_BASE + 30)		| PAD_DS_GROUP_10), ///< L_GPIO_15
+	PAD_DS_LGPIO16    =     ((PAD_L_GPIO_BASE + 32)		| PAD_DS_GROUP_10), ///< L_GPIO_16
+	PAD_DS_LGPIO17    =     ((PAD_L_GPIO_BASE + 34)		| PAD_DS_GROUP_10), ///< L_GPIO_17
+	PAD_DS_LGPIO18    =     ((PAD_L_GPIO_BASE + 36)		| PAD_DS_GROUP_10), ///< L_GPIO_18
+	PAD_DS_LGPIO19    =     ((PAD_L_GPIO_BASE + 38)		| PAD_DS_GROUP_10), ///< L_GPIO_19
+	PAD_DS_LGPIO20    =     ((PAD_L_GPIO_BASE + 40)		| PAD_DS_GROUP_10), ///< L_GPIO_20
+	PAD_DS_LGPIO21    =     ((PAD_L_GPIO_BASE + 42)		| PAD_DS_GROUP_10), ///< L_GPIO_21
+	PAD_DS_LGPIO22    =     ((PAD_L_GPIO_BASE + 44)		| PAD_DS_GROUP_10), ///< L_GPIO_22
+	PAD_DS_LGPIO23    =     ((PAD_L_GPIO_BASE + 46)		| PAD_DS_GROUP_10), ///< L_GPIO_23
+	PAD_DS_LGPIO24    =     ((PAD_L_GPIO_BASE + 48)		| PAD_DS_GROUP_10), ///< L_GPIO_23
+
+	//D_GPIO group
+	PAD_DS_DGPIO0     =     ((PAD_D_GPIO_BASE + 0)		| PAD_DS_GROUP_16), ///< D_GPIO_0
+	PAD_DS_DGPIO1     =     ((PAD_D_GPIO_BASE + 2)		| PAD_DS_GROUP_16), ///< D_GPIO_1
+	PAD_DS_DGPIO2     =     ((PAD_D_GPIO_BASE + 4)		| PAD_DS_GROUP_16), ///< D_GPIO_2
+	PAD_DS_DGPIO3     =     ((PAD_D_GPIO_BASE + 6)		| PAD_DS_GROUP_16), ///< D_GPIO_3
+	PAD_DS_DGPIO4     =     ((PAD_D_GPIO_BASE + 8)		| PAD_DS_GROUP_16), ///< D_GPIO_4
+	PAD_DS_DGPIO5     =     ((PAD_D_GPIO_BASE + 10)		| PAD_DS_GROUP_16), ///< D_GPIO_5
+	PAD_DS_DGPIO6     =     ((PAD_D_GPIO_BASE + 12)		| PAD_DS_GROUP_16), ///< D_GPIO_6
+	PAD_DS_DGPIO7     =     ((PAD_D_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< D_GPIO_7
+
+	//HSI_GPIO group
+	PAD_DS_HSIGPIO0    =    ((PAD_H_GPIO_BASE + 0)		| PAD_DS_GROUP_10), ///< HSI_GPIO_0
+	PAD_DS_HSIGPIO1    =    ((PAD_H_GPIO_BASE + 2)		| PAD_DS_GROUP_10), ///< HSI_GPIO_1
+	PAD_DS_HSIGPIO2    =    ((PAD_H_GPIO_BASE + 4)		| PAD_DS_GROUP_10), ///< HSI_GPIO_2
+	PAD_DS_HSIGPIO3    =    ((PAD_H_GPIO_BASE + 6)		| PAD_DS_GROUP_10), ///< HSI_GPIO_3
+	PAD_DS_HSIGPIO4    =    ((PAD_H_GPIO_BASE + 8)		| PAD_DS_GROUP_10), ///< HSI_GPIO_4
+	PAD_DS_HSIGPIO5    =    ((PAD_H_GPIO_BASE + 10)		| PAD_DS_GROUP_10), ///< HSI_GPIO_5
+	PAD_DS_HSIGPIO6    =    ((PAD_H_GPIO_BASE + 12)		| PAD_DS_GROUP_10), ///< HSI_GPIO_6
+	PAD_DS_HSIGPIO7    =    ((PAD_H_GPIO_BASE + 14)		| PAD_DS_GROUP_10), ///< HSI_GPIO_7
+	PAD_DS_HSIGPIO8    =    ((PAD_H_GPIO_BASE + 16)		| PAD_DS_GROUP_10), ///< HSI_GPIO_8
+	PAD_DS_HSIGPIO9    =    ((PAD_H_GPIO_BASE + 18)		| PAD_DS_GROUP_10), ///< HSI_GPIO_9
+	PAD_DS_HSIGPIO10   =    ((PAD_H_GPIO_BASE + 20)		| PAD_DS_GROUP_10), ///< HSI_GPIO_10
+	PAD_DS_HSIGPIO11   =    ((PAD_H_GPIO_BASE + 22)		| PAD_DS_GROUP_10), ///< HSI_GPIO_11
+
+	//A_GPIO group
+	PAD_DS_AGPIO0      =    ((PAD_A_GPIO_BASE + 0)		| PAD_DS_GROUP_10), ///< A_GPIO_0
+	PAD_DS_AGPIO1      =    ((PAD_A_GPIO_BASE + 2)		| PAD_DS_GROUP_10), ///< A_GPIO_1
+	PAD_DS_AGPIO2      =    ((PAD_A_GPIO_BASE + 4)		| PAD_DS_GROUP_10), ///< A_GPIO_2
+
+	PAD_DS_MAX = PAD_DS_AGPIO2,
+	ENUM_DUMMY4WORD(PAD_DS)
+} PAD_DS;
+//@}
+
+/**
+    Pad power ID select
+
+    Pad power ID for PAD_POWER_STRUCT.
+*/
+typedef enum {
+	PAD_POWERID_MC0  =          0x00,      ///< Pad power id for MC0
+	PAD_POWERID_MC1  =          0x01,      ///< Pad power id for MC1
+	PAD_POWERID_ADC  =          0x02,      ///< Pad power id for Audio ADC
+	PAD_POWERID_CSI  =          0x04,      ///< Pad power id for CSI/LVDS
+
+	ENUM_DUMMY4WORD(PAD_POWERID)
+} PAD_POWERID;
+
+/**
+    Pad power select
+
+    Pad power value for PAD_POWER_STRUCT.
+*/
+typedef enum {
+	PAD_3P3V         =          0x00,      ///< Pad power is 3.3V
+	PAD_AVDD         =          0x00,      ///< Pad power is AVDD ( for PAD_POWERID_ADC use)
+	PAD_1P8V         =          0x01,      ///< Pad power is 1.8V
+	PAD_PAD_VAD      =          0x01,      ///< Pad power is PAD_ADC_VAD ( for PAD_POWERID_ADC use)
+
+	ENUM_DUMMY4WORD(PAD_POWER)
+} PAD_POWER;
+
+/**
+    Pad power VAD for  PAD_POWERID_ADC
+
+    Pad power VAD value for PAD_POWER_STRUCT.
+*/
+typedef enum {
+	PAD_VAD_2P9V     =          0x00,      ///< Pad power VAD = 2.9V <ADC>
+	PAD_VAD_3P0V     =          0x01,      ///< Pad power VAD = 3.0V <ADC>
+	PAD_VAD_3P1V     =          0x03,      ///< Pad power VAD = 3.1V <ADC>
+
+	PAD_VAD_2P4V     =          0x100,     ///< Pad power VAD = 2.4V <CSI>
+	PAD_VAD_2P5V     =          0x101,     ///< Pad power VAD = 2.5V <CSI>
+	PAD_VAD_2P6V     =          0x103,     ///< Pad power VAD = 2.6V <CSI>
+
+	ENUM_DUMMY4WORD(PAD_VAD)
+} PAD_VAD;
+
+
+/**
+    PAD power structure
+
+    PAD power setting for pad_set_power()
+*/
+typedef struct {
+	PAD_POWERID         power_id;           ///< Pad power id
+	PAD_POWER           power;              ///< Pad power
+	BOOL                bias_current;       ///< Regulator bias current selection
+											///< - @b FALSE: disable
+											///< - @b TRUE: enable
+	BOOL                opa_gain;           ///< Regulator OPA gain/phase selection
+											///< - @b FALSE: disable
+											///< - @b TRUE: enable
+	BOOL                pull_down;          ///< Regulator output pull down control
+											///< - @b FALSE: none
+											///< - @b TRUE: pull down enable
+	BOOL                regulator_en;       ///< Regulator enable
+											///< - @b FALSE: disable
+											///< - @b TRUE: enable
+	PAD_VAD             vad;                ///< Pad VAD of PAD_POWERID_ADC when PAD_PAD_VAD = 1
+} PAD_POWER_STRUCT;
+
+
+
+
+
+
+
+
+// Backward compatible usages
+#define PAD_PIN_CGPIO23        PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO23         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO24         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO25         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO26         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO27         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO28         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO29         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO30         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO31         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO32         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_CGPIO33         PAD_PIN_NOT_EXIST				// For backward compatible
+#define PAD_DS_PGPIO39         PAD_PIN_NOT_EXIST				// For backward compatible
+
+
+/*
+	Exporting APIs
+*/
+
+extern ER pad_setPullUpDown(UINT32 pin, PAD_PULL pulltype);
+extern ER pad_setDrivingSink(UINT32 name, PAD_DRIVINGSINK driving);
+//@}
+
+
+
+//@}
+
+#endif

loader/Include/Driver/regdef.h

@@ -0,0 +1,199 @@
+/*
+ * MIPS register definitions, originally from:
+ *
+ * include/asm-mips/regdefs.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License, Version 2.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 1994, 1995 by Ralf Baechle
+ */
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+# define Mode_USR               0x10        /* M[4:0] = 01010 */
+# define Mode_FIQ               0x11        /* M[4:0] = 10001 */
+# define Mode_IRQ               0x12        /* M[4:0] = 10010 */
+# define Mode_SVC               0x13        /* M[4:0] = 10011 */
+# define Mode_ABT               0x17        /* M[4:0] = 10111 */
+# define Mode_UNDEF             0x1B        /* M[4:0] = 11011 */
+# define Mode_SYS               0x1F        /* M[4:0] = 11111 */
+# define Mode_MSK               0x1F        /* M[4:0] = 11111 */
+# define I_Bit                  0x80        /* 7  6  5  4  3  2  1  0 */
+# define F_Bit                  0x40        /* I  F  T M4 M3 M2 M1 M0 */
+
+/*
+ ************************************************************************
+ *    		Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0)       	*
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |W|W|R|W|NumSets			 			 |Associativity      |L    |
+ * |T|B|A|A|                             |                   |S    |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_CCSIDR_WT		31
+#define M_CCSIDR_WT		(0x1  << S_CCSIDR_WT)		/* Support write-through */
+#define S_CCSIDR_WB		30
+#define M_CCSIDR_WB		(0x1  << S_CCSIDR_WB)		/* Support write-back */
+#define S_CCSIDR_RA		29
+#define M_CCSIDR_RA		(0x1  << S_CCSIDR_RA)		/* Support read-allocation */
+#define S_CCSIDR_WA		28
+#define M_CCSIDR_WA		(0x1  << S_CCSIDR_WA)		/* Support write-allocation */
+#define S_CCSIDR_SETS	13
+#define M_CCSIDR_SETS	(0x7fff  << S_CCSIDR_SETS)	/* Number of sets */
+#define S_CCSIDR_A		3
+#define M_CCSIDR_A		(0x3ff  << S_CCSIDR_A)		/* Number of associatiovity */
+#define S_CCSIDR_LS		0
+#define M_CCSIDR_LS		(0x7  << S_CCSIDR_LS)		/* Cache line size */
+
+/*
+ ************************************************************************
+ *    		Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1)       	*
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |0|0|LoUU |LoC  |LoUIS|CT7  |CT6  |CT5  |CT4  |CT3  |CT2  |CT1  |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_CLIDR_LoUU	27
+#define M_CLIDR_LoUU	(0x7 << S_CLIDR_LoUU)
+#define S_CLIDR_LoC		24
+#define M_CLIDR_LoC		(0x7 << S_CLIDR_LoC)	/* Cache cohernecy level */
+#define S_CLIDR_LoUIS	21
+#define M_CLIDR_LoUIS	(0x7 << S_CLIDR_LoUIS)
+#define S_CLIDR_Ctype7	18
+#define M_CLIDR_Ctype7	(0x7 << S_CLIDR_Ctype7)	/* Cache type of level 7 cache */
+#define S_CLIDR_Ctype6	15
+#define M_CLIDR_Ctype6	(0x7 << S_CLIDR_Ctype6)	/* Cache type of level 6 cache */
+#define S_CLIDR_Ctype5	12
+#define M_CLIDR_Ctype5	(0x7 << S_CLIDR_Ctype5)	/* Cache type of level 5 cache */
+#define S_CLIDR_Ctype4	9
+#define M_CLIDR_Ctype4	(0x7 << S_CLIDR_Ctype4)	/* Cache type of level 4 cache */
+#define S_CLIDR_Ctype3	6
+#define M_CLIDR_Ctype3	(0x7 << S_CLIDR_Ctype3)	/* Cache type of level 3 cache */
+#define S_CLIDR_Ctype2	3
+#define M_CLIDR_Ctype2	(0x7 << S_CLIDR_Ctype2)	/* Cache type of level 2 cache */
+#define S_CLIDR_Ctype1	0
+#define M_CLIDR_Ctype1	(0x7 << S_CLIDR_Ctype1)	/* Cache type of level 1 cache */
+
+#define K_CLIDR_Ctype_NO	0	/* No cache */
+#define K_CLIDR_Ctype_IC	1	/* Instruction cache only */
+#define K_CLIDR_Ctype_DC	2	/* Data cache only */
+#define K_CLIDR_Ctype_ID	3	/* Seperate instruction and data caches, Harvard cache */
+#define K_CLIDR_Ctype_U		4	/* Unified cache, von Neumann cacge */
+
+/*
+ ************************************************************************
+ *    	Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0)      *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |Reserved                                               |Level|I|
+ * |                                                       |     |n|
+ * |                                                       |     |D|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_CCSELR_Level	1
+#define M_CCSELR_Level	(0x7  << S_CCSELR_Level)	/* Cache level */
+#define S_CCSELR_InD	0
+#define M_CCSELR_InD	(0x1  << S_CCSELR_InD)		/* I$ or D$ */
+
+/*
+ ************************************************************************
+ *    		System Control Register, SCTLR (cp15, 0, c1, c0, 0)         *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M|
+ * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | |
+ * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | |
+ * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_SCTLR_TE		30
+#define M_SCTLR_TE		(0x1 << S_SCTLR_TE)			/* Thumb exception enable */
+#define S_SCTLR_AFE		29
+#define M_SCTLR_AFE		(0x1 << S_SCTLR_AFE)		/* Access flag enable */
+#define S_SCTLR_TRE		28
+#define M_SCTLR_TRE		(0x1 << S_SCTLR_TRE)		/* TXE remap enable */
+#define S_SCTLR_NMFI	27
+#define M_SCTLR_NMFI	(0x1 << S_SCTLR_NMFI)		/* None-maskable FIQ enbale (RO) */
+#define S_SCTLR_EE		25
+#define M_SCTLR_EE		(0x1 << S_SCTLR_EE)			/* Exception Endianness: big-endian */
+#define S_SCTLR_VE		24
+#define M_SCTLR_VE		(0x1 << S_SCTLR_VE)			/* Interrupt Vector Enable */
+#define S_SCTLR_FI		21
+#define M_SCTLR_FI		(0x1 << S_SCTLR_FI)			/* Fast interrupt configuraiont enable */
+#define S_SCTLR_UWXN	20
+#define M_SCTLR_UWXN	(0x1 << S_SCTLR_UWXN)		/* */
+#define S_SCTLR_WXN		19
+#define M_SCTLR_WXN		(0x1 << S_SCTLR_WXN)
+#define S_SCTLR_HA		17
+#define M_SCTLR_HA		(0x1 << S_SCTLR_HA)			/* Hardware access flag enable */
+#define S_SCTLR_RR		14
+#define M_SCTLR_RR		(0x1 << S_SCTLR_RR)			/* Round-robin select */
+#define S_SCTLR_V		13
+#define M_SCTLR_V		(0x1 << S_SCTLR_V)			/* Vector bits */
+#define S_SCTLR_I		12
+#define M_SCTLR_I		(0x1 << S_SCTLR_I)			/* Instruction cache enable */
+#define S_SCTLR_Z		11
+#define M_SCTLR_Z		(0x1 << S_SCTLR_Z)			/* Branch prediction enable */
+#define S_SCTLR_SW		10
+#define M_SCTLR_SW		(0x1 << S_SCTLR_SW)			/* SW and SWP enable */
+#define S_SCTLR_CP15BEN	5
+#define M_SCTLR_CP15BEN	(0x1 << S_SCTLR_CP15BEN)	/* CP15 barrier support */
+#define S_SCTLR_C		2
+#define M_SCTLR_C		(0x1 << S_SCTLR_C)			/* Data and Unidied cache enable */
+#define S_SCTLR_A		1
+#define M_SCTLR_A		(0x1 << S_SCTLR_A)			/* Alignment fault checking enable */
+#define S_SCTLR_M		0
+#define M_SCTLR_M		(0x1 << S_SCTLR_M)			/* PL1&0 stage MMU enable */
+
+/************************************************************************
+ *    		Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1)      *
+ ************************************************************************
+ *
+ *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
+ *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |UNP/SBZP                                   |P|A|E|S|RAZ|W|L|L|F|
+ * |                                           |a|l|X|M|   | |1|2|W|
+ * |                                           |r|l|C|P|   |f| | | |
+ * |                                           | |o|L| |   |l|p|p| |
+ * |                                           |o|c| | |   | |r|r| |
+ * |                                           |n| | | |   |z|e|e| |
+ * |                                           | |o| | |   |e|f|f| |
+ * |                                           | |n| | |   |r| | | |
+ * |                                           | |e| | |   |o|e|e| |
+ * |                                           | | | | |   |s|n|n| |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define S_ACTLR_PAR_ON		9
+#define M_ACTLR_PAR_ON		(0x1 << S_ACTLR_PAR_ON)		/* Parity on */
+#define S_ACTLR_ALLOC_ONE	8
+#define M_ACTLR_ALLOC_ONE	(0x1 << S_ACTLR_ALLOC_ONE)	/* Alloc in one way */
+#define S_ACTLR_EXCL		7
+#define M_ACTLR_EXCL		(0x1 << S_ACTLR_EXCL)		/* Exclusive cache */
+#define S_ACTLR_SMP			6
+#define M_ACTLR_SMP			(0x1 << S_ACTLR_SMP)		/* SMP */
+#define S_ACTLR_W_FL_ZEROS	3
+#define M_ACTLR_W_FL_ZEROS	(0x1 << S_ACTLR_W_FL_ZEROS)	/* Write full line of zeros mode */
+#define S_ACTLR_L1_PERF_EN	2
+#define M_ACTLR_L1_PERF_EN	(0x1 << S_ACTLR_L1_PERF_EN)	/* Dside prefetch enable */
+#define S_ACTLR_L2_PERF_EN	1
+#define M_ACTLR_L2_PERF_EN	(0x1 << S_ACTLR_L2_PERF_EN)	/* L2 prefetch enable */
+#define S_ACTLR_FW			0
+#define M_ACTLR_FW			(0x1 << S_ACTLR_FW)			/* Cache and TLB maintenance boardcast */
+
+

loader/Include/IOReg.h

@@ -0,0 +1,190 @@
+/**
+    I/O Access header file
+
+    I/O Access header file
+
+    @file       IOReg.h
+    @ingroup    mISYSUtil
+    @note       Nothing
+*/
+
+#ifndef __IO_REG_H
+#define __IO_REG_H
+
+#include "constant.h"
+#include "CMacro.h"
+#include "Memory.h"
+
+/**
+    @addtogroup mISYSUtil
+*/
+//@{
+
+/**
+    @name Input 8bit IO register
+
+    Input 8bit IO register
+
+    @param[in] x        I/O address
+
+    @return register value
+*/
+//@{
+#define INREG8(x)       (*((volatile UINT8*)(x)))               ///< Read 8bits IO register
+//@}
+
+/**
+    @name Output 8bit IO register
+
+    Output to 8bit IO register
+
+    @param[in] x        I/O address
+    @param[in] y        Value to be output
+
+    @return void
+*/
+//@{
+#define OUTREG8(x, y)       (*((volatile UINT8*)(x)) = (y))     ///< Write 8bits IO register
+//@}
+
+/**
+    @name Set bits to 8bit IO register
+
+    Set bits to 8bit IO register
+
+    @param[in] x        I/O address
+    @param[in] y        Value to be set. y will be ORed to this address
+
+    @return register value
+*/
+//@{
+#define SETREG8(x, y)       OUTREG8((x), INREG8(x) | (y))       ///< Set 8bits IO register
+//@}
+
+/**
+    @name Clear bits from 8bit IO register
+
+    Clear bits from 8bit IO register
+
+    @param[in] x        I/O address
+    @param[in] y        Value to be clear. ~(y) will be ANDed to this address
+
+    @return register value
+*/
+//@{
+#define CLRREG8(x, y)       OUTREG8((x), INREG8(x) & ~(y))      ///< Clear 8bits IO register
+//@}
+
+/**
+    @name Input 16bit IO register
+
+    Input 16bit IO register
+
+    @param[in] x        I/O address (should be 2 bytes alignment)
+
+    @return register value
+*/
+//@{
+#define INREG16(x)      (*((volatile UINT16*)(x)))              ///< Read 16bits IO register
+//@}
+
+/**
+    @name Output 16bit IO register
+
+    Output to 16bit IO register
+
+    @param[in] x        I/O address (should be 2 bytes alignment)
+    @param[in] y        Value to be output
+
+    @return void
+*/
+//@{
+#define OUTREG16(x, y)      (*((volatile UINT16*)(x)) = (y))    ///< Write 16bits IO register
+//@}
+
+/**
+    @name Set bits to 16bit IO register
+
+    Set bits to 16bit IO register
+
+    @param[in] x        I/O address (should be 2 bytes alignment)
+    @param[in] y        Value to be set. y will be ORed to this address
+
+    @return register value
+*/
+//@{
+#define SETREG16(x, y)      OUTREG16((x), INREG16(x) | (y))     ///< Set 16bits IO register
+//@}
+
+/**
+    @name Clear bits from 16bit IO register
+
+    Clear bits from 16bit IO register
+
+    @param[in] x        I/O address (should be 2 bytes alignment)
+    @param[in] y        Value to be clear. ~(y) will be ANDed to this address
+
+    @return register value
+*/
+//@{
+#define CLRREG16(x, y)      OUTREG16((x), INREG16(x) & ~(y))    ///< Clear 16bits IO register
+//@}
+
+/**
+    @name Input 32bit IO register
+
+    Input 32bit IO register
+
+    @param[in] x        I/O address (should be 4 bytes alignment)
+
+    @return register value
+*/
+//@{
+#define INREG32(x)          (*((volatile UINT32*)(x)))          ///< Read 32bits IO register
+//@}
+
+/**
+    @name Output 32bit IO register
+
+    Output to 32bit IO register
+
+    @param[in] x        I/O address (should be 4 bytes alignment)
+    @param[in] y        Value to be output
+
+    @return void
+*/
+//@{
+#define OUTREG32(x, y)      (*((volatile UINT32*)(x)) = (y))    ///< Write 32bits IO register
+//@}
+
+/**
+    @name Set bits to 32bit IO register
+
+    Set bits to 32bit IO register
+
+    @param[in] x        I/O address (should be 4 bytes alignment)
+    @param[in] y        Value to be set. y will be ORed to this address
+
+    @return register value
+*/
+//@{
+#define SETREG32(x, y)      OUTREG32((x), INREG32(x) | (y))     ///< Set 32bits IO register
+//@}
+
+/**
+    @name Clear bits from 32bit IO register
+
+    Clear bits from 32bit IO register
+
+    @param[in] x        I/O address (should be 4 bytes alignment)
+    @param[in] y        Value to be clear. ~(y) will be ANDed to this address
+
+    @return register value
+*/
+//@{
+#define CLRREG32(x, y)      OUTREG32((x), INREG32(x) & ~(y))    ///< Clear 32bits IO register
+//@}
+
+//@}
+
+#endif  // __IO_REG_H

loader/Include/SMacro.h

@@ -0,0 +1,129 @@
+; Global vars for arg parsing
+
+    GBLS    _arg0
+    GBLS    _arg1
+
+; _spaces_remove
+; remove start and end spaces from global variable wstring
+
+        MACRO
+        _spaces_remove $wstring
+        WHILE (  ("*" :CC: $wstring) :RIGHT: 1 = " ")
+$wstring    SETS ($wstring :LEFT: (:LEN: $wstring - 1))
+        WEND
+        WHILE ( ($wstring :CC: "*") :LEFT: 1 = " ")
+$wstring    SETS ($wstring :RIGHT: (:LEN: $wstring - 1))
+        WEND
+        MEND
+
+; _lbracket_remove
+; Attempt to remove a single left bracket - error if not there
+
+    MACRO
+    _lbracket_remove $s
+    ASSERT  $s:LEFT:1 = "("
+$s  SETS    $s:RIGHT:(:LEN:$s-1)
+    _spaces_remove $s
+    MEND
+
+; _rbracket_remove
+; Attempt to remove a single right bracket - error if not there
+; then removes excess spaces
+
+    MACRO
+    _rbracket_remove $s
+    ASSERT  $s:RIGHT:1 = ")"
+$s  SETS    $s:LEFT:(:LEN:$s-1)
+    _spaces_remove $s
+    MEND
+
+; _comment_remove
+; Remove any comment from line end and then strip any spaces
+
+    MACRO
+    _comment_remove $s
+    _spaces_remove $s
+    IF (("**":CC:$s):RIGHT:2) = "*/"
+      WHILE ($s:RIGHT:2) <> "/*"
+$s      SETS $s:LEFT:(:LEN:$s-1)
+      WEND
+$s  SETS $s:LEFT:(:LEN:$s-2)
+    _spaces_remove $s
+    ENDIF
+    MEND
+
+; _arg_remove
+; Pull an argument from the front of a spaces stripped string
+
+    MACRO
+    _arg_remove $s,$arg
+    LCLA    _arglen
+    LCLL    _ok
+_arglen SETA    0
+_ok SETL    {TRUE}
+    WHILE    _ok
+      IF _arglen>=:LEN:$s
+_ok     SETL {FALSE}    ; break if used up input string
+      ELSE
+$arg        SETS ($s:LEFT:(_arglen+1)):RIGHT:1    ; next character
+        IF $arg=" "
+_ok       SETL {FALSE}
+        ELSE
+_arglen       SETA _arglen+1
+        ENDIF
+      ENDIF
+    WEND
+$arg    SETS $s:LEFT:_arglen
+$s  SETS $s:RIGHT:(:LEN:$s-_arglen)
+    _spaces_remove $s
+    MEND
+
+; ifndef
+; Purpose: Allow #ifndef for common C headers (Just for guarded C header file)
+; Syntax : #<space/tab>ifndef<spaces><symbol></*comment*/>
+
+    MACRO
+    ifndef $a
+    MEND
+
+; define
+; Purpose: Allow #defines for common C/Assembler headers
+; Syntax : #<space/tab>define<spaces><symbol><spaces><value></*comment*/>
+
+    MACRO
+$la define $a
+_arg0   SETS    "$a"
+    ASSERT  "$la"="#"    ; syntax: # define fred 1
+    _comment_remove _arg0
+    _arg_remove _arg0,_arg1
+    IF "$_arg0"<>""
+$_arg1  EQU    $_arg0
+    ENDIF
+    MEND
+
+
+; COMMENT
+; Purpose: Allow comments in common C/Assembler headers
+; Syntax : COMMENT <anything you like!>
+
+    MACRO
+    COMMENT $a,$b,$c,$d,$e,$f,$g,$h
+    MEND
+
+; local labels use label$l to get a local label and LOCAL to start a new
+; area
+
+    GBLA LocalCount
+    GBLS l
+LocalCount SETA 1
+l    SETS "x$LocalCount"
+
+; increment local variable number
+
+    MACRO
+    LOCAL
+LocalCount SETA LocalCount+1
+l   SETS "x$LocalCount"
+    MEND
+
+    END

loader/Include/StorageDef.h

@@ -0,0 +1,448 @@
+/**
+    Storage module driver.
+
+    This file is the driver of storage module.
+
+    @file       StorageDef.h
+    @ingroup    mIDrvStorage
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _STORAGE_DEF_
+#define _STORAGE_DEF_
+
+#include "constant.h"
+
+#define _STORAGE_OBJ_					1
+/**
+    @addtogroup mIDrvStorage
+*/
+//@{
+
+/**
+    @name External storage type
+
+*/
+//@{
+#define EXT_STORAGE_TYPE_NONE           (0)
+#define EXT_STORAGE_TYPE_SDIO1          (1)
+#define EXT_STORAGE_TYPE_SDIO2          (2)
+#define EXT_STORAGE_TYPE_USB            (3)
+#define EXT_STORAGE_TYPE_ETH            (4)
+//*}
+
+/**
+    @name SPI Quad read type
+
+    @note for SPI_IDENTIFY
+*/
+//@{
+#define     SPI_QUAD_NONE               0       ///< Not support
+#define     SPI_QUAD_TYPE1              1       ///< Support quad read, QE(Quad Enable) bit is in Status Reigster[bit 6] and 0x6B command requires 8 dummy clocks.
+#define     SPI_QUAD_TYPE2              2       ///< Support quad read, QE(Quad Enable) bit  is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks.
+#define     SPI_QUAD_TYPE3              3       ///< Support quad read, QE(Quad Enable) NOT exist and 0x6B command requires 8 dummy clocks
+#define     SPI_QUAD_TYPE4              4       ///< Support quad read, QE(Quad Enable) bit  is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks.
+                                                ///< But QE should be modified by 0x31 command
+//@}
+
+
+/**
+    @name SPI RDCR read type
+
+    @note for SPI_IDENTIFY
+*/
+//@{
+#define     SPI_RDCR_NONE               0       ///< Not support
+#define     SPI_RDCR_TYPE1              1       ///< Support RDCR(0x15) bit[7..6] need config as 0x3
+
+//@}
+
+/**
+    SPI flash identify descriptor
+
+    @note For STRG_IDENTIFY_CB
+*/
+typedef struct
+{
+    BOOL    bSupportEWSR;                       ///< EWSR(0x50) command capability
+                                                ///< - @b TRUE: support EWSR command
+                                                ///< - @b FALSE: NOT support EWSR command
+    BOOL    bSupportAAI;                        ///< AAI program(0xAD) command capability
+                                                ///< - @b TRUE: ONLY support AAI program command
+                                                ///< - @b FALSE: NOT support AAI program command, but support page program command
+    BOOL    bDualRead;                          ///< Dual read (0x3B) command capability
+                                                ///< - @b TRUE: support dual read comand. (Command value should be 0x3B.)
+                                                ///< - @b FALSE: NOT support dual read command
+    UINT32  uiQuadReadType;                     ///< Quad read type capability. (ONLY support quad command 0x6B)
+                                                ///< - @b SPI_QUAD_NONE: NOT support quad read command
+                                                ///< - @b SPI_QUAD_TYPE1: Support quad read command, QE in Status Register bit 6
+                                                ///< - @b SPI_QUAD_TYPE2: Support quad read command, QE in Status Register bit 9
+                                                ///< - @b SPI_QUAD_TYPE3: Support quad read command, QE NOT exist
+                                                ///< - @b SPI_QUAD_TYPE4: Support quad read command, QE in Status Register bit 9 (but need 0x31 command)
+    UINT32  uiFlashSize;                        ///< Flash total byte size. (unit: byte)
+} SPI_IDENTIFY, *PSPI_IDENTIFY;
+
+/**
+    @name Storage Access CallBack
+
+    Storage Access CallBack Prototype
+
+    @return void
+*/
+//@{
+typedef void (*STRG_ACCESS_CB)(void);   ///< Storage access call back prototype
+//@}
+
+/**
+    @name Storage Identify CallBack
+
+    Storage Identify CallBack Prototype
+
+    @param[in] UINT32 uiMfgID   (JEDEC) manufacturer ID read from spi flash
+    @param[in] UINT32 uiTypeID  (JEDEC) type ID read from spi flash
+    @param[in] UINT32 uiCapacityID  (JEDEC) capacity ID read from spi flash
+    @param[out] PSPI_IDENTIFY   flash identification returned to spi flash driver
+
+    @return
+        - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information
+        - @b FALSE: input ID is NOT supported/identified by call back
+*/
+//@{
+typedef BOOL (*STRG_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPI_IDENTIFY);    ///< Storage identify call back prototype
+//@}
+
+/**
+    @name Storage return value
+
+    @note for flash_open(), flash_readSectors(), and flash_writeSectors()
+*/
+//@{
+#define     E_OK                         0      ///< Success
+#define     E_NAND_IDENTIFY_ERR         -1      ///< Read NAND ID (information) error
+#define     E_NAND_INSUFFICINET_BLK     -2      ///< Bad block is too much to write data
+#define     E_NAND_BLK_NOT_FOUND        -3      ///< Logic block number not found in physical block
+#define     E_NAND_WRITE_PAGEDATA_ERR   -4      ///< Logic block number not found in physical block
+#define     E_NAND_ERASEE_BLK_ERR       -5      ///< NAND erase block error
+#define     E_NAND_READ_PAGE_ERR        -6      ///< NAND read page data error
+#define     E_NAND_READ_BLK_ERR         -7      ///< NAND read block data error
+#define     E_NAND_ID_NOT_SUPPORT       -8      ///< Not support NAND ID
+#define     E_IDENTIFY_ERR              -9      ///< SPI IDENTIFY error
+#define     E_SYS                       -10     ///< System Error
+#define     E_NAND_ALIGN_ERR            -11     ///< Not block alignment
+#define     E_NAND_BOUNDARY_ERR         -12     ///< boundary < write buffer
+#define     E_OK_TABLE_FOUND             1      ///< Success & NAND table find
+#define     E_OK_TABLE_NOT_FOUND         2      ///< Success & NAND table not find
+//@}
+
+/**
+    @name Internal Storage Update Region
+
+    @note for flash_readSectors(), and flash_writeSectors()
+*/
+//@{
+#define     NAND_RW_LOADER               0      ///< Update Region is Loader (Update size is assumed 16 KB)
+#define     NAND_RW_RESERVED             1      ///< Update Region is reserved area (Update size is assumed 16 KB)
+#define     NAND_RW_FIRMWARE             2      ///< Update Region is FW (Update size is variable)
+#define     NAND_RW_FIRMWARE_2           3      ///< Update Region is FW from 2-5(Update size is variable)
+#define     NAND_RW_FIRMWARE_3           4      ///< Update Region is FW from 2-5(Update size is variable)
+#define     NAND_RW_FIRMWARE_4           5      ///< Update Region is FW from 2-5(Update size is variable)
+#define     NAND_RW_FIRMWARE_5           6      ///< Update Region is FW from 2-5(Update size is variable)
+//@}
+
+/**
+    @name Internal Storage Configuration ID
+
+    @note for flash_setConfig()
+*/
+//@{
+#define     FLASH_CFG_ID_NONE                   0
+#define     FLASH_CFG_ID_SPI_SUPPORT_4BITS      1   ///< Enable your project to support 4 bit SPI flash. ONLY enable when you ENSURE SPI_D0~SPI_D3 are connected to SPI flash in your PCB!!!
+#define     FLASH_CFG_ID_EMMC_SUPPORT_8BITS     2   ///< Enable your project to support 8 bit EMMC. ONLY enable when you ENSURE EMMC_D0~SPI_D7 are connected to EMMC flash in your PCB!!!
+#define	    FLASH_CFG_ID_CS_SELECT				3   ///< Select this flash (nand/nor) is connected with CS0 or CS1
+#define 	FLASH_CFG_ID_SPI_IDENTIFY_CB		4	///< Install flash identify call back
+//@}
+
+#if (_STORAGE_OBJ_== 1)
+
+
+#define BOOT_SOURCE_SPI                0x00
+#define BOOT_SOURCE_SPI_NAND_2K        0x02
+#define BOOT_SOURCE_SPI_NAND_4K        0x06
+#define BOOT_SOURCE_EMMC_4BIT          0x08
+#define BOOT_SOURCE_EMMC_8BIT          0x09
+
+/**
+    @name New storage object interface
+
+    For new version storage device driver
+*/
+//@{
+typedef struct {
+	INT32(*flash_open)(void);												///< Flash Open
+  	 void(*flash_close)(void);												///< Flash Close
+	INT32(*flash_readSectors)(UINT32, UINT32, UINT8 *,UINT32);				///< Flash Read Sector
+	INT32(*flash_writeSectors)(UINT32, UINT32, UINT8 *, UINT32);			///< Flash Write Sector
+	INT32(*flash_writePartition)(UINT32, UINT32, UINT32, UINT8 *, UINT32);	///< Flash Write Sector, and remain space need erase
+   UINT32(*flash_getBlockSize)(void);										///< Flash Get Block Size
+     void(*flash_setReservedBadBlockNumber)(UINT32);						///< Flash Set Reserved Bad Block Number
+	 void(*flash_setReservedAreaMaxBlockNumber)(UINT32);					///< Flash Set Reserved Area Block Number
+   UINT64(*flash_getTotalSize)(void);
+     void(*flash_installAccessCB)(STRG_ACCESS_CB);
+	 void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB);
+	 void(*flash_setFrequency)(UINT32);
+	INT32(*flash_setConfig)(UINT32, UINT32);
+	INT32(*flash_get_spare_data)(UINT32, UINT32 *);
+} STORAGE_OBJ, *PSTORAGE_OBJ;
+
+extern PSTORAGE_OBJ emmc_get_storage_object(void);
+extern PSTORAGE_OBJ nand_get_storage_object(void);
+extern PSTORAGE_OBJ nor_get_storage_object(void);
+
+//@}
+#else
+#define	FLASH_OPEN(m)						flash_open()
+#define	FLASH_CLOSE(m)						flash_close()
+#define FLASH_READSECTOR(m, n, o, x, y)		flash_readSectors(n,o,x,y)	///< Flash Read Sector
+#define FLASH_WRITESECTOR(m, n, o, x, y)	flash_writeSectors(n,o,x,y)	///< Flash Write Sector
+#define FLASH_GETBLKSIZE(m)					flash_getBlockSize()
+
+     void(*flash_setReservedBadBlockNumber)(UINT32);				///< Flash Set Reserved Bad Block Number
+	 void(*flash_setReservedAreaMaxBlockNumber)(UINT32);			///< Flash Set Reserved Area Block Number
+   UINT64(*flash_getTotalSize)(void);
+     void(*flash_installAccessCB)(STRG_ACCESS_CB);
+	 void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB);
+	 void(*flash_setFrequency)(UINT32);
+	INT32(*flash_setConfig)(UINT32, UINT32);
+} STORAGE_OBJ, *PSTORAGE_OBJ;
+
+/**
+    Flash Open
+
+    This function will initialize internal flash driver
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @return
+        - @b E_OK: open success
+        - @b E_IDENTIFY_ERR: identify fail (SPI path)
+        - @b E_NAND_IDENTIFY_ERR: identify fail (NAND path)
+        - @b E_NAND_ID_NOT_SUPPORT: not supported NAND flash
+*/
+extern INT32    flash_open(void);
+/**
+    Flash Close
+
+    This function will close internal flash driver
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @return void
+*/
+extern void     flash_close(void);
+
+/**
+    Flash Read Sector
+
+    This function will read data from internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] startblk         Start block of this read operation (unit: flash block)
+    @param[in] length           Length of read operation (unit: byte)
+    @param[out] buffer          Pointer to DRAM buffer to receive read data (word alignment)
+    @param[in] updateType       Operation Access Region
+                                - @b NAND_RW_LOADER: loader region
+                                - @b NAND_RW_RESERVED: reserved area
+                                - @b NAND_RW_FIRMWARE: f/w region
+
+    @return
+        - @b E_OK: read success
+        - @b E_NAND_BLK_NOT_FOUND: can not find available physical block
+        - @b E_NAND_READ_BLK_ERR: NAND access block error
+        - @b E_NAND_READ_PAGE_ERR: NAND access page error
+*/
+extern INT32    flash_readSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType);
+
+/**
+    Flash Write Sector
+
+    This function will write data to internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] startblk         Start block of this write operation (unit: flash block)
+    @param[in] length           Length of write operation (unit: byte)
+    @param[in] buffer           Pointer to DRAM buffer of written data (word alignment)
+    @param[in] updateType       Operation Access Region
+                                - @b NAND_RW_LOADER: loader region
+                                - @b NAND_RW_RESERVED: reserved area
+                                - @b NAND_RW_FIRMWARE: f/w region
+
+    @return
+        - @b E_OK: read success
+        - @b E_NAND_BLK_NOT_FOUND: can not find available physical block
+        - @b E_NAND_ERASEE_BLK_ERR: erase block error
+        - @b E_NAND_WRITE_PAGEDATA_ERR: page program error
+        - @b E_NAND_INSUFFICINET_BLK: insufficient good block
+*/
+extern INT32    flash_writeSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType);
+
+/**
+    Flash Get Block Size
+
+    This function will return block size of attached internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @return block size (unit: byte)
+*/
+extern UINT32   flash_getBlockSize(void);
+
+/**
+    Flash Set Reserved Bad Block Number
+
+    This function will set block count reserved to do bad block replacement
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] badBlkNum        reserved bad block count (unit: block)
+
+    @return void
+*/
+extern void     flash_setReservedBadBlockNumber(UINT32 badBlkNum);
+
+//#NT#2010/04/20#Steven Wang -begin
+//#NT#Autumn reserved area from 2 ~ 23
+/**
+    Flash Set Reserved Area Block Number
+
+    This function will set reserved area max block count
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] RsvMaxBlkNum     max reserved area block count (unit: block)
+
+    @return void
+*/
+extern void     flash_setReservedAreaMaxBlockNumber(UINT32 RsvMaxBlkNum);
+//#NT#2010/04/20#Steven Wang -end
+
+/**
+    Flash Get Total Size
+
+    This function will return total size of attached internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @return total size (unit: byte)
+*/
+extern UINT64   flash_getTotalSize(void);
+
+/**
+    Install Flash Access CallBack
+
+    This function will install access callback.
+    The installed callback will be invoked when one block/page is programmed
+
+    @note card is selected by STORAGEEXT in MakeConfig.txt
+
+    @param[in] accessCB     installed callback
+
+    @return void
+*/
+extern void     flash_installAccessCB(STRG_ACCESS_CB accessCB);
+
+/**
+    Install Flash Identify CallBack
+
+    This function will install identification callback.
+    The installed callback will be invoked when spi flash driver is opened.
+
+    @note NAND driver will NOT invoke the installed call back
+
+    @param[in] identifyCB   installed callback
+
+    @return void
+*/
+extern void     flash_installIdentifyCB(STRG_IDENTIFY_CB identifyCB);
+
+/**
+    Flash Set Bus Frequency
+
+    This function will set operating frequency of attached internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] uiFreq       Operating frequency (unit: MHz)
+
+    @return void
+*/
+extern void     flash_setFrequency(UINT32 uiFreq);
+
+/**
+    Flash Set Configuration
+
+    This function will set specific configuration for internal flash
+
+    @note Internal flash is selected by STORAGEINT in MakeConfig.txt
+
+    @param[in] uiConfigId   Configuration ID, can be:
+                            - @b FLASH_CFG_ID_SPI_SUPPORT_4BITS: configure to support 4 bit SPI flash
+    @param[in] uiContext    Configuration context for uiConfigId
+                            When uiConfigId == FLASH_CFG_ID_SPI_SUPPORT_4BITS:
+                            - @b TRUE: use 4 bit read when attached SPI flash support 4 bit read
+                            - @b FALSE: won't use 4 bit read
+
+    @return
+        - @b E_OK: success
+        - @b Else: fail
+*/
+extern INT32    flash_setConfig(UINT32 uiConfigId, UINT32 uiContext);
+#endif
+// External storage public API ( SDIO/MS/xD )
+/**
+    Open card driver
+
+    This function will initialize card driver and register it to file system
+
+    @note card is selected by STORAGEEXT in MakeConfig.txt
+
+    @return
+        - @b TRUE: open success
+        - @b FALSE: open fail
+*/
+extern INT32    card_open(void);
+
+/**
+    Close card driver
+
+    This function will close card driver
+
+    @note card is selected by STORAGEEXT in MakeConfig.txt
+
+    @return void
+*/
+extern void     card_close(void);
+
+/**
+    Get card type
+
+    This function is used to get card storage type
+
+    @note card is selected by STORAGEEXT in MakeConfig.txt
+
+    @return void
+*/
+
+extern UINT32   card_get_type(void);
+
+//@}
+
+extern void  USBOTGReset(void);
+//extern INT32 USB3Download(void);
+extern INT32 USBDownload(void);
+extern void  USBSetResult(UINT32 uiResult);
+extern INT32 USBStateMachine(void);
+#endif

loader/Include/Type.h

@@ -0,0 +1,9 @@
+#ifndef __TYPE_H
+#define __TYPE_H
+
+#include <stdio.h>
+//#include <stdint.h>
+
+#define _ALIGNED(x) __attribute__((aligned(x)))
+
+#endif  // __TYPE_H

loader/Include/constant.h

@@ -0,0 +1,115 @@
+#ifndef _CONSTANT_H
+#define _CONSTANT_H
+
+//Size MNEMONIC
+
+#define SZ_1                    (1 << 0)    /* 0x00000001 */
+#define SZ_2                    (1 << 1)    /* 0x00000002 */
+#define SZ_4                    (1 << 2)    /* 0x00000004 */
+#define SZ_8                    (1 << 3)    /* 0x00000008 */
+#define SZ_16                   (1 << 4)    /* 0x00000010 */
+#define SZ_32                   (1 << 5)    /* 0x00000020 */
+#define SZ_64                   (1 << 6)    /* 0x00000040 */
+#define SZ_128                  (1 << 7)    /* 0x00000080 */
+#define SZ_256                  (1 << 8)    /* 0x00000100 */
+#define SZ_512                  (1 << 9)    /* 0x00000200 */
+
+#define SZ_1K                   (1 << 10)   /* 0x00000400 */
+#define SZ_2K                   (1 << 11)   /* 0x00000800 */
+#define SZ_4K                   (1 << 12)   /* 0x00001000 */
+#define SZ_8K                   (1 << 13)   /* 0x00002000 */
+#define SZ_16K                  (1 << 14)   /* 0x00004000 */
+#define SZ_32K                  (1 << 15)   /* 0x00008000 */
+#define SZ_64K                  (1 << 16)   /* 0x00010000 */
+#define SZ_128K                 (1 << 17)   /* 0x00020000 */
+#define SZ_256K                 (1 << 18)   /* 0x00040000 */
+#define SZ_512K                 (1 << 19)   /* 0x00080000 */
+
+#define SZ_1M                   (1 << 20)   /* 0x00100000 */
+#define SZ_2M                   (1 << 21)   /* 0x00200000 */
+#define SZ_4M                   (1 << 22)   /* 0x00400000 */
+#define SZ_8M                   (1 << 23)   /* 0x00800000 */
+#define SZ_16M                  (1 << 24)   /* 0x01000000 */
+#define SZ_32M                  (1 << 25)   /* 0x02000000 */
+#define SZ_64M                  (1 << 26)   /* 0x04000000 */
+#define SZ_128M                 (1 << 27)   /* 0x08000000 */
+#define SZ_256M                 (1 << 28)   /* 0x10000000 */
+#define SZ_512M                 (1 << 29)   /* 0x20000000 */
+
+#define SZ_1G                   (1 << 30)   /* 0x40000000 */
+#define SZ_2G                   (1 << 31)   /* 0x80000000 */
+
+#define SZ_30M                  (SZ_32M - SZ_2M)
+
+// ASCII code
+
+#define CR                      0x0D
+#define LF                      0x0A
+#define BS                      0x08
+#define ESC                     27
+
+// Boolean constant definition
+
+#if 0
+#ifndef FALSE
+#define FALSE                   0
+#endif
+#ifndef TRUE
+#define TRUE                    1
+#endif
+#endif
+
+#ifndef NULL
+#define NULL                    0
+#endif
+
+#ifndef ON
+#define ON                      1
+#endif
+
+#ifndef OFF
+#define OFF                     0
+#endif
+
+#ifndef ENABLE
+#define ENABLE                  1
+#endif
+
+#ifndef DISABLE
+#define DISABLE                 0
+#endif
+
+#ifndef DISK_FULL
+#define DISK_FULL               (-1)
+#endif
+
+// type declaration
+
+typedef int                     BOOLEAN;
+typedef unsigned long long      UINT64;
+typedef long long               INT64;
+typedef unsigned long           UINT32;
+typedef unsigned long           INT32U;
+typedef unsigned                INT32S;
+typedef unsigned char           INT8U;
+typedef long                    INT32;
+typedef unsigned short          UINT16;
+typedef short                   INT16;
+typedef unsigned char           UINT8;
+typedef char                    INT8;
+typedef unsigned long long  u64;
+typedef unsigned int        u32;
+typedef unsigned char       u8;
+typedef unsigned short      u16;
+typedef unsigned int        uint;
+typedef unsigned short      ushort;
+typedef unsigned char       uchar;
+typedef unsigned int            UINT;
+typedef int                     INT;
+
+typedef enum {FALSE, TRUE} BOOL;
+
+// error codes
+typedef long                    ER;
+
+#endif

loader/Include/ctype.h

@@ -0,0 +1,36 @@
+
+
+#ifndef NVT_CTYPES_H__
+#define NVT_CTYPES_H__
+
+
+#define _U  0x01    /* upper */
+#define _L  0x02    /* lower */
+#define _D  0x04    /* digit */
+#define _C  0x08    /* cntrl */
+#define _P  0x10    /* punct */
+#define _S  0x20    /* white space (space/lf/tab) */
+#define _X  0x40    /* hex digit */
+#define _SP 0x80    /* hard space (0x20) */
+
+extern unsigned char _ctype[];
+
+#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
+
+#define isalnum(c)  ((__ismask(c)&(_U|_L|_D)) != 0)
+#define isalpha(c)  ((__ismask(c)&(_U|_L)) != 0)
+#define iscntrl(c)  ((__ismask(c)&(_C)) != 0)
+#define isdigit(c)  ((__ismask(c)&(_D)) != 0)
+#define isgraph(c)  ((__ismask(c)&(_P|_U|_L|_D)) != 0)
+#define islower(c)  ((__ismask(c)&(_L)) != 0)
+#define isprint(c)  ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
+#define ispunct(c)  ((__ismask(c)&(_P)) != 0)
+#define isspace(c)  ((__ismask(c)&(_S)) != 0)
+#define isupper(c)  ((__ismask(c)&(_U)) != 0)
+#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0)
+
+#define isascii(c) (((unsigned char)(c))<=0x7f)
+#define toascii(c) (((unsigned char)(c))&0x7f)
+
+
+#endif

loader/Include/debug.h

@@ -0,0 +1,31 @@
+/**
+    string header
+
+    string header
+
+    @file       string.h
+    @ingroup    mISYSClib
+    @note       Nothing
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef __NVT_DEBUG_H__
+#define __NVT_DEBUG_H__
+
+#include "fuart.h"
+/** \addtogroup mISYSClib */
+//@{
+
+extern void debug_set_console(CONSOLE_OBJ *p_obj);
+extern void debug_err(char *str);
+extern void debug_err_var(char *str, int var);
+extern void debug_msg(char *str) __attribute__ ((section (".part1")));
+extern void debug_msg_var(char *str, int var) __attribute__ ((section (".part1")));
+extern void debug_dump_addr(UINT32 addr, UINT32 size);
+
+
+//@}
+
+#endif
+

loader/Include/fat.h

@@ -0,0 +1,48 @@
+/**
+    File system library
+
+    This file is the library of file system
+
+    @file       fat.h
+    @ingroup    mISYSFile
+    @note       Nothing.
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+#ifndef _FAT_H
+#define _FAT_H
+
+#include "constant.h"
+#include "StorageDef.h"
+
+/**
+    @addtogroup mISYSFile
+*/
+//@{
+
+#define FAT_READ_TOTAL_FILE_LENGTH          0
+
+typedef void (*TOGGLE_LED)(UINT8 WithCount);
+
+extern BOOL     fat_initFAT(UINT32 uiBuf, UINT32 uiSize);
+extern UINT32   fat_getPartitionCount(void);
+extern BOOL     fat_mountPartition(UINT32 partition_id);
+extern void     fat_closeFAT(void);
+extern BOOL     fat_open_rootfile(UINT8 *pfilename);
+extern UINT32   fat_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen);
+extern UINT32   fat_getRootfileSize(void);
+extern void     fat_close_rootfile(void);
+extern void     fat_regToggleLED(TOGGLE_LED pToggleLED);
+extern void     fat_installAccessCB(STRG_ACCESS_CB accessCB);
+
+// For SD registration
+extern BOOL     fat_internal_initFAT(UINT32 uiBuf, UINT32 uiSize);
+extern BOOL     fat_internal_open_rootfile(UINT8 *pfilename);
+extern UINT32   fat_internal_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen);
+extern void     fat_internal_close_rootfile(void);
+
+//@}
+
+#endif
+

loader/Include/fdt/compiler.h

@@ -0,0 +1,56 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#if 0
+#define uswap_16(x) (x)
+#define uswap_32(x) (x)
+#define _uswap_64(x, sfx) (x)
+#else
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#endif
+#if defined(__GNUC__)
+#define uswap_64(x) _uswap_64(x, ull)
+#else
+#define uswap_64(x) _uswap_64(x, )
+#endif
+#define cpu_to_le16(x)     (x)
+#define cpu_to_le32(x)     (x)
+#define cpu_to_le64(x)     (x)
+#define le16_to_cpu(x)     (x)
+#define le32_to_cpu(x)     (x)
+#define le64_to_cpu(x)     (x)
+#define cpu_to_be16(x)     uswap_16(x)
+#define cpu_to_be32(x)     uswap_32(x)
+#define cpu_to_be64(x)     uswap_64(x)
+#define be16_to_cpu(x)     uswap_16(x)
+#define be32_to_cpu(x)     uswap_32(x)
+#define be64_to_cpu(x)     uswap_64(x)
+
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+
+#endif

loader/Include/fdt/fdt.h

@@ -0,0 +1,111 @@
+#ifndef _FDT_H
+#define _FDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	fdt32_t magic;			 /* magic word FDT_MAGIC */
+	fdt32_t totalsize;		 /* total size of DT block */
+	fdt32_t off_dt_struct;		 /* offset to structure */
+	fdt32_t off_dt_strings;		 /* offset to strings */
+	fdt32_t off_mem_rsvmap;		 /* offset to memory reserve map */
+	fdt32_t version;		 /* format version */
+	fdt32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	fdt32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	fdt32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	fdt32_t size_dt_struct;		 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	fdt64_t address;
+	fdt64_t size;
+};
+
+struct fdt_node_header {
+	fdt32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	fdt32_t tag;
+	fdt32_t len;
+	fdt32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(fdt32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(fdt32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(fdt32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(fdt32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(fdt32_t))
+
+#endif /* _FDT_H */

loader/Include/fdt/libfdt_env.h

@@ -0,0 +1,64 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * SPDX-License-Identifier:	LGPL-2.1+
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include "compiler.h"
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef		__u8		uint8_t;
+typedef		__u16		uint16_t;
+typedef		__u32		uint32_t;
+typedef		__s32		int32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef		__u64		uint64_t;
+typedef		__u64		u_int64_t;
+typedef		__s64		int64_t;
+#endif
+
+#define __bitwise
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+
+extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
+
+typedef __be16 fdt16_t;
+typedef __be32 fdt32_t;
+typedef __be64 fdt64_t;
+
+#define fdt32_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_fdt32(x)		cpu_to_be32(x)
+#define fdt64_to_cpu(x)		be64_to_cpu(x)
+#define cpu_to_fdt64(x)		cpu_to_be64(x)
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+
+#endif /* _LIBFDT_ENV_H */

loader/Include/fuart.h

@@ -0,0 +1,85 @@
+/**
+    Header file for UART
+
+    This file is the header file for UART driver
+
+    @file       fuart.h
+    @ingroup    mIIOUART
+    @note       Nothing
+
+    Copyright   Novatek Microelectronics Corp. 2012.  All rights reserved.
+*/
+
+
+#ifndef _FUART_H
+#define _FUART_H
+
+#include "constant.h"
+
+/**
+    @addtogroup mIIOUART
+*/
+//@{
+#ifndef ENUM_DUMMY4WORD
+#define ENUM_DUMMY4WORD(name)   E_##name = 0x10000000
+#endif
+
+typedef enum {
+	CONSOLE_UART0,
+	CONSOLE_UART1,
+
+	ENUM_DUMMY4WORD(UART_CONSOLE_CH)
+} UART_CONSOLE_CH;
+
+
+typedef struct _CONSOLE {
+	void (*hook)(void); 			///< start this object
+	void (*putc)(char c); 			///< console input funciton pointer
+	unsigned char (*getc)(void); 	///< console output function point
+} CONSOLE_OBJ, *PCONSOLE_OBJ;
+
+
+
+/**
+    @name Put system UART string
+
+    Print string to UART
+
+    @param[in] m        printed string
+*/
+//@{
+#define uart_putSystemUARTStr(m)    fLib_PutSerialStr(m)    ///< Print string MACRO
+//@}
+
+/**
+    @name Put system UART character
+
+    Print character to UART
+
+    @param[in] m        printed character
+*/
+//@{
+#define uart_putSystemUARTChar(m)   fLib_PutSerialChar(m)   ///< Print character MACRO
+//@}
+
+extern void fLib_PutSerialChar(char Ch)    __attribute__ ((section (".part1")));
+extern void fLib_PutSerialStr(char *Str)   __attribute__ ((section (".part1")));
+extern void uart_openSystemUART(void);
+extern void uart_openSystemUART2(void);
+
+extern void uart_getChar_polling(char * c);
+extern void uart_chkChar(char * c);
+extern void uart_getStr_polling(char * c);
+extern void uart_getBinary(char *pcString, UINT32 BufferLen);
+
+void serial_init(void);
+unsigned char serial_getc(void);
+void serial_putc(char c);
+void serial2_init(void);
+unsigned char serial2_getc(void);
+void serial2_putc(char c);
+PCONSOLE_OBJ get_uart_object(UART_CONSOLE_CH uart_ch);
+
+//@}
+
+#endif

loader/Include/gic.h

@@ -0,0 +1,195 @@
+
+#ifndef _ASM_ARMV8_GIC_H_
+#define _ASM_ARMV8_GIC_H_
+//#include "FLibARM.h"
+#define UART_INTID     43
+
+
+
+#define GIC_UART_INTID (UART_INTID + 32)
+#if 0
+/*
+ * Distributor layout
+ */
+#define GICD_CTLR      0x0000
+#define GICD_TYPER     0x0004
+#define GICD_IIDR      0x0008
+#define GICD_IGROUP    0x0080
+#define GICD_ISENABLE  0x0100
+#define GICD_ICENABLE  0x0180
+#define GICD_ISPEND    0x0200
+#define GICD_ICPEND    0x0280
+#define GICD_ISACTIVE  0x0300
+#define GICD_ICACTIVE  0x0380
+#define GICD_IPRIORITY 0x0400
+#define GICD_ITARGETS  0x0800
+#define GICD_ICFG      0x0c00
+#define GICD_PPISR     0x0d00
+#define GICD_SPISR     0x0d04
+#define GICD_SGIR      0x0f00
+#define GICD_CPENDSGI  0x0f10
+#define GICD_SPENDSGI  0x0f20
+#define GICD_PIDR4     0x0fd0
+#define GICD_PIDR5     0x0fd4
+#define GICD_PIDR6     0x0fd8
+#define GICD_PIDR7     0x0fdc
+#define GICD_PIDR0     0x0fe0
+#define GICD_PIDR1     0x0fe4
+#define GICD_PIDR2     0x0fe8
+#define GICD_PIDR3     0x0fec
+#define GICD_CIDR0     0x0ff0
+#define GICD_CIDR1     0x0ff4
+#define GICD_CIDR2     0x0ff8
+#define GICD_CIDR3     0x0ffc
+
+/*
+ * CPU Interface layout
+ */
+#define GICC_CTLR      0x0000
+#define GICC_PMR       0x0004
+#define GICC_BPR       0x0008
+#define GICC_IAR       0x000c
+#define GICC_EOIR      0x0010
+#define GICC_RPR       0x0014
+#define GICC_HPPIR     0x0018
+#define GICC_ABPR      0x001c
+#define GICC_AIAR      0x0020
+#define GICC_AEOIR     0x0024
+#define GICC_AHPPIR    0x0028
+#define GICC_APR0      0x00d0
+#define GICC_NSAPR0    0x00e0
+#define GICC_IIDR      0x00fc
+#define GICC_DIR       0x1000
+#endif
+
+#define MAX_SPIS            480
+
+#define MAX_PPIS            14
+#define MAX_SGIS            16
+
+#define MIN_SGI_ID          0
+#define MIN_PPI_ID          16
+#define MIN_SPI_ID          32
+
+#define GRP0                0
+#define GRP1                1
+
+#define _GICD_              0x1000
+#define _GICC_              0x2000
+#define _GICH_              0x4000
+#define _GICV_              0x6000
+
+#define GIC_PRI_MASK                0xff
+#define GIC_HIGHEST_SEC_PRIORITY    0
+#define GIC_LOWEST_SEC_PRIORITY     127
+#define GIC_HIGHEST_NS_PRIORITY     128
+#define GIC_LOWEST_NS_PRIORITY      254 /* 255 would disable an interrupt */
+#define GIC_SPURIOUS_INTERRUPT      1023
+#define GIC_TARGET_CPU_MASK 0xff
+
+/* Distributor interface definitions */
+#define GICD_CTLR           _GICD_ + 0x0
+#define GICD_TYPER          _GICD_ + 0x4
+#define GICD_IGROUPR        _GICD_ + 0x80
+#define GICD_ISENABLER      _GICD_ + 0x100
+#define GICD_ICENABLER      _GICD_ + 0x180
+#define GICD_ISPENDR        _GICD_ + 0x200
+#define GICD_ICPENDR        _GICD_ + 0x280
+#define GICD_ISACTIVER      _GICD_ + 0x300
+#define GICD_ICACTIVER      _GICD_ + 0x380
+#define GICD_IPRIORITYR     _GICD_ + 0x400
+#define GICD_ITARGETSR      _GICD_ + 0x800
+#define GICD_ICFGR          _GICD_ + 0xC00
+#define GICD_SGIR           _GICD_ + 0xF00
+#define GICD_CPENDSGIR      _GICD_ + 0xF10
+#define GICD_SPENDSGIR      _GICD_ + 0xF20
+
+#define IGROUPR_SHIFT       5
+#define ISENABLER_SHIFT     5
+#define ICENABLER_SHIFT     ISENABLER_SHIFT
+#define ISPENDR_SHIFT       5
+#define ICPENDR_SHIFT       ISPENDR_SHIFT
+#define ISACTIVER_SHIFT     5
+#define ICACTIVER_SHIFT     ISACTIVER_SHIFT
+#define IPRIORITYR_SHIFT    2
+#define ITARGETSR_SHIFT     2
+#define ICFGR_SHIFT         4
+#define CPENDSGIR_SHIFT     2
+#define SPENDSGIR_SHIFT     CPENDSGIR_SHIFT
+
+/* GICD_TYPER bit definitions */
+#define IT_LINES_NO_MASK    0x1f
+
+/* GICD_ICFGR bit definitions */
+#define LEVEL_SENSITIVE     0x0
+#define TRIGGER_SENSITIVE   0x1
+
+/* Physical CPU Interface registers */
+#define GICC_CTLR           _GICC_ + 0x0
+#define GICC_PMR            _GICC_ + 0x4
+#define GICC_BPR            _GICC_ + 0x8
+#define GICC_IAR            _GICC_ + 0xC
+#define GICC_EOIR           _GICC_ + 0x10
+#define GICC_RPR            _GICC_ + 0x14
+#define GICC_HPPIR          _GICC_ + 0x18
+#define GICC_AHPPIR         _GICC_ + 0x28
+#define GICC_IIDR           _GICC_ + 0xFC
+#define GICC_DIR            _GICC_ + 0x1000
+#define GICC_PRIODROP       _GICC_ + GICC_EOIR
+
+/* GICC_CTLR bit definitions */
+#define EOI_MODE_NS         (1 << 10)
+#define EOI_MODE_S          (1 << 9)
+#define IRQ_BYP_DIS_GRP1    (1 << 8)
+#define FIQ_BYP_DIS_GRP1    (1 << 7)
+#define IRQ_BYP_DIS_GRP0    (1 << 6)
+#define FIQ_BYP_DIS_GRP0    (1 << 5)
+#define CBPR                (1 << 4)
+#define FIQ_EN              (1 << 3)
+#define ACK_CTL             (1 << 2)
+#define ENABLE_GRP1         (1 << 1)
+#define ENABLE_GRP0         (1 << 0)
+
+/* GICC_IIDR bit masks and shifts */
+#define GICC_IIDR_PID_SHIFT     20
+#define GICC_IIDR_ARCH_SHIFT    16
+#define GICC_IIDR_REV_SHIFT     12
+#define GICC_IIDR_IMP_SHIFT     0
+
+#define GICC_IIDR_PID_MASK  0xfff
+#define GICC_IIDR_ARCH_MASK 0xf
+#define GICC_IIDR_REV_MASK  0xf
+#define GICC_IIDR_IMP_MASK  0xfff
+
+/* HYP view virtual CPU Interface registers */
+#define GICH_CTL            0x0
+#define GICH_VTR            0x4
+#define GICH_ELRSR0         0x30
+#define GICH_ELRSR1         0x34
+#define GICH_APR0           0xF0
+#define GICH_LR_BASE        0x100
+
+/* Virtual CPU Interface registers */
+#define GICV_CTL            0x0
+#define GICV_PRIMASK        0x4
+#define GICV_BP             0x8
+#define GICV_INTACK         0xC
+#define GICV_EOI            0x10
+#define GICV_RUNNINGPRI     0x14
+#define GICV_HIGHESTPEND    0x18
+#define GICV_DEACTIVATE     0x1000
+
+extern void     nvt_enable_irq(int number);
+extern void     nvt_disable_irq(int number);
+extern void     arm_gic_cpuif_setup(void);
+extern void     arm_gic_distif_setup(void);
+extern void     gicd_write_igroupr(UINT32 id, UINT32 val);
+extern void     gicd_write_ipriorityr(UINT32 id, UINT32 val);
+
+extern UINT32   gicc_get_IAR(void);
+extern void     gicc_set_EOIR(UINT32 val);
+
+
+
+
+#endif /* _ASM_ARMV8_GIC_H_ */

loader/Include/global.h

@@ -0,0 +1,66 @@
+/**
+    Global utility header file
+
+    Global utility header file
+
+    @file       global.h
+    @ingroup    mISYSUtil
+    @note       Nothing
+*/
+
+#ifndef _GLOBAL_H
+#define _GLOBAL_H
+
+#include "constant.h"
+
+#define BOOT_SOURCE_SPI                0x00
+#define BOOT_SOURCE_CARD               0x01
+#define BOOT_SOURCE_SPI_NAND_2K        0x02
+#define BOOT_SOURCE_SPI_NAND_RS_2K     0x03
+#define BOOT_SOURCE_ETHERNET           0x04
+#define BOOT_SOURCE_USB                0x05
+#define BOOT_SOURCE_SPI_NAND_4K        0x06
+#define BOOT_SOURCE_RESERVED           0x07
+#define BOOT_SOURCE_EMMC_4BIT          0x08
+#define BOOT_SOURCE_EMMC_8BIT          0x09
+#define BOOT_SOURCE_SPI_NAND_RS_4K     0x0A
+#define BOOT_SOURCE_USB_FULL           0x0B
+#define BOOT_SOURCE_UART               0x0C
+
+#define CHIPVER_A                       0x0
+
+/**
+    @addtogroup mISYSUtil
+*/
+//@{
+
+extern UINT32   bitCount(UINT32 data);
+extern void     UTL_setDrvTmpBufferAddress(UINT32 addr);
+extern UINT32   UTL_getDrvTmpBufferAddress(void);
+extern char*    Dec2HexStr(UINT32 data);
+//extern void     PrintDec2Hex(UINT32 data) __attribute__ ((section (".part1")));
+extern void     rom_Dec2HexStr(UINT32 data) __attribute__ ((section (".part1")));
+#define PrintDec2Hex(m)	rom_Dec2HexStr(m)
+extern char*    Dec2HexStr2Bytes(UINT32 data);
+extern void     PrintDec2HexStr2Bytes(UINT32 data) __attribute__ ((section (".part1")));
+extern UINT32   DecStr2Int(char* str);
+extern BOOL     UTL_canUpdateSecKey(void);
+extern BOOL     utl_is_sram_fw(UINT32 fw_addr);
+extern void     utl_test_checksum(UINT32 addr, UINT32 size);
+extern void     utl_dram_protect_enable(UINT32 addr, UINT32 size);
+extern void     utl_dram_protect_disable(void);
+extern UINT32   utl_dram_protect_check(void);
+extern UINT32   utl_get_bootsrc(void);
+extern UINT32   utl_get_chipversion(void);
+
+#if (_ROM_PUBLIC_API_ == 1)
+extern void 	rom_debug_msg(char* str);
+extern void 	rom_debug_msg_var(char *str, int var);
+extern void 	rom_Dec2HexStr(UINT32 data);
+#endif
+extern void load_dram_scan(UINT32 addr, UINT32 size)   __attribute__ ((section (".dram_text")));
+extern void timer_delay(UINT32 US)   __attribute__ ((section (".part1")));
+
+//@}
+
+#endif

loader/Include/limits.h

@@ -0,0 +1,31 @@
+
+
+#ifndef __NVT_LIBC_LIMITS_H
+#define __NVT_LIBC_LIMITS_H
+
+#define CHAR_BIT      8         /* number of bits in a char */
+#define SCHAR_MIN   (-128)      /* minimum signed char value */
+#define SCHAR_MAX     127       /* maximum signed char value */
+#define UCHAR_MAX     0xff      /* maximum unsigned char value */
+
+#ifndef _CHAR_UNSIGNED
+#define CHAR_MIN    SCHAR_MIN   /* mimimum char value */
+#define CHAR_MAX    SCHAR_MAX   /* maximum char value */
+#else
+#define CHAR_MIN      0
+#define CHAR_MAX    UCHAR_MAX
+#endif  /* _CHAR_UNSIGNED */
+
+#define MB_LEN_MAX    2             /* max. # bytes in multibyte char */
+#define SHRT_MIN    (-32768)        /* minimum (signed) short value */
+#define SHRT_MAX      32767         /* maximum (signed) short value */
+#define USHRT_MAX     0xffff        /* maximum unsigned short value */
+#define INT_MIN     (-2147483647 - 1) /* minimum (signed) int value */
+#define INT_MAX       2147483647    /* maximum (signed) int value */
+#define UINT_MAX      0xffffffff    /* maximum unsigned int value */
+#define LONG_MIN    (-2147483647L - 1) /* minimum (signed) long value */
+#define LONG_MAX      2147483647L   /* maximum (signed) long value */
+#define ULONG_MAX     0xffffffffUL  /* maximum unsigned long value */
+
+#endif
+

loader/Include/loader.h

@@ -0,0 +1,99 @@
+/**
+    Global loader header file
+
+    Global loader header file
+
+    @file       loader.h
+    @ingroup    mISYSUtil
+    @note       Nothing
+*/
+
+#ifndef _LOADER_H
+#define _LOADER_H
+
+#include "constant.h"
+#include "StorageDef.h"
+
+/**
+    @name Special key detect CallBack
+
+    Special key detect Prototype
+
+    Project layer can detect special key in this callback.
+    If callback returns TRUE, loader will try to find files on SD card.
+
+    @return
+        - @b TRUE: special key is pressed
+        - @b FALSE: special key is NOT pressed
+*/
+//@{
+typedef BOOL (*LDR_SPECIAL_KEY_CB)(void);
+//@}
+
+/**
+    @name Card detect CallBack
+
+    Card detect Prototype
+
+    Project layer can detect SD card existence in this callback.
+    If callback returns TRUE, loader will consider SD is plugged
+
+    @return
+        - @b TRUE: SD exist
+        - @b FALSE: SD NOT exist
+*/
+//@{
+typedef BOOL (*LDR_CARD_DETECT_CB)(void);
+//@}
+/**
+    @name Recovery Trigger CallBack
+
+    Recovery trigger Prototype
+
+    Project layer can detect if the recovery flow should started.
+    If callback returns TRUE, recovery flow will start.
+
+    @return
+        - @b TRUE: Recovery flow is triggered.
+        - @b FALSE: Recovery flow is NOT triggered.
+*/
+//@{
+typedef BOOL (*LDR_RECOVERY_TRIGGER_CB)(void);
+//@}
+
+/**
+    @name Fastboot key detect CallBack
+
+    Fastboot key detect Prototype
+
+    Project layer can detect fastboot key in this callback.
+    If callback returns TRUE, loader will run the fastboot flow.
+
+    @return
+        - @b TRUE: fastboot key is pressed
+        - @b FALSE: fastboot key is NOT pressed
+*/
+//@{
+typedef BOOL (*LDR_FASTBOOT_KEY_CB)(void);
+
+typedef enum _STORAGEINT {
+	STORAGEINT_UNOKNOWN,
+	STORAGEINT_SPI_NAND,
+	STORAGEINT_SPI_NOR,
+	STORAGEINT_EMMC,
+} STORAGEINT;
+
+extern void loader_setUpdateFwName(char* fileName);
+extern void loader_setUpdateLdrName(char* fileName);
+extern void loader_setRunFwName(char* fileName);
+extern void loader_setRecoveryFwName(char *fileName);
+extern void loader_setRecoveryPartitionID(UINT32 partition_id);
+extern void loader_setVersion(UINT32 version);
+extern void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj);
+extern void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback);
+extern void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback);
+extern void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback);
+extern void loader_installFastbootKeyCB(LDR_FASTBOOT_KEY_CB callback);
+
+#endif
+