diff --git a/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h b/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h index 18e3d9afa..1e2bfbf30 100644 --- a/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h +++ b/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h @@ -917,8 +917,8 @@ #define DZOOM_FUNC ENABLE #define HUNTING_MCU_I2C DISABLE #define HUNTING_MCU_UART ENABLE -#define HUNTING_IR_LED_940 DISABLE -#define SF_BASE_VERSION "7MD4RCwD3T6" +#define HUNTING_IR_LED_940 ENABLE//DISABLE +#define SF_BASE_VERSION "7MD4RCwD3T8" #define HW_S530 1 #define DCF_DIR_NAME "MEDIA" /* 100HUNTI */ #define DCF_FILE_NAME "SYFW" /* IMAG0001.JPG */ diff --git a/code/application/source/cardv/SrcCode/System/SysStrg_Exe.c b/code/application/source/cardv/SrcCode/System/SysStrg_Exe.c index 5bdb126d1..6daac99ed 100644 --- a/code/application/source/cardv/SrcCode/System/SysStrg_Exe.c +++ b/code/application/source/cardv/SrcCode/System/SysStrg_Exe.c @@ -851,6 +851,7 @@ INT32 System_OnStrgAttach(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) DCF_ScanObj(); // } #endif + FileSys_GetDiskInfo(FST_INFO_DISK_SIZE); System_SetState(SYS_STATE_FS, FS_INIT_OK); #if defined(__FREERTOS) diff --git a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c old mode 100755 new mode 100644 index 0d70eaca9..1409afc2b --- a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c +++ b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c @@ -34,8 +34,8 @@ #define VDO_MAIN_SIZE_W 2560 #define VDO_MAIN_SIZE_H 1440 -#define VDO_CLONE_SIZE_W 848 -#define VDO_CLONE_SIZE_H 480 +#define VDO_CLONE_SIZE_W 1920 +#define VDO_CLONE_SIZE_H 1080 #endif @@ -183,7 +183,7 @@ void Movie_CommPoolInit(void) mem_cfg.pool_info[id].blk_cnt = 4; #endif #else - mem_cfg.pool_info[id].blk_cnt = 6; + mem_cfg.pool_info[id].blk_cnt = 4; #endif mem_cfg.pool_info[id].ddr_id = DDR_ID0; #endif diff --git a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_Exe.c b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_Exe.c index c0534c9f7..1fc60fb70 100644 --- a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_Exe.c +++ b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_Exe.c @@ -244,7 +244,7 @@ INT32 Set_Cur_Day_Night_Status(BOOL OnOff, UINT8 isSnapVideo) vendor_isp_set_iq(IQT_ITEM_NIGHT_MODE, &night_mode); if (OnOff){ - vos_util_delay_ms(100); + vos_util_delay_ms(330); } if ((hd_ret = vendor_isp_uninit()) != HD_OK) { DBG_ERR("vendor_isp_uninit() fail(%d)\r\n", hd_ret); @@ -1328,11 +1328,11 @@ static void MovieExe_UserEventCb(UINT32 id, MOVIE_USER_CB_EVENT event_id, UINT32 // DCF_AddDBfile(info->path); // DBG_DUMP("%s added to DCF\r\n", info->path); #if HUNTING_CAMERA_MCU == ENABLE - DBG_IND(" ===== MOVIE_USER_CB_EVENT_CLOSE_FILE_COMPLETED ===== \r\n"); + DBG_IND(" ===== MOVIE_USER_CB_EVENT_CLOSE_FILE_COMPLETED ===== id:%d \r\n", id); UIMenuStoreInfo *puiPara = sf_ui_para_get(); - if(SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode) + if((SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode) && (id == _CFG_REC_ID_1)) { - sf_share_mem_file_down(0); + sf_share_mem_file_down(0, 0); } #endif @@ -1855,7 +1855,11 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) MovieExe_SetIMECrop(i); #endif } - MovieMapping_GetStreamInfo(UI_GetData(FL_MOVIE_SIZE), (UINT32) &gMovie_Strm_Info); + + MovieMapping_GetStreamInfo(UI_GetData(FL_MOVIE_SIZE), (UINT32) &gMovie_Strm_Info); + + DBG_DUMP("****** gMovie_Strm_Info {%lu, %lu}", gMovie_Strm_Info.size.w, gMovie_Strm_Info.size.h); + ImageApp_MovieMulti_Config(MOVIE_CONFIG_STREAM_INFO, (UINT32)&gMovie_Strm_Info); ImageApp_MovieMulti_Config(MOVIE_CONFIG_AUDIO_INFO, (UINT32)&gMovie_Audio_Info); ImageApp_MovieMulti_Config(MOVIE_CONFIG_DISP_INFO, (UINT32)&gMovie_Disp_Info); @@ -1867,7 +1871,7 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) ImageApp_MovieMulti_RegUserCB(MovieExe_UserEventCb); //ImageApp_MovieMulti_SetParam(_CFG_DISP_ID_1, MOVIEMULTI_PARAM_DISP_REG_CB, (UINT32)MovieExe_DispCB); - //ImageApp_MovieMulti_SetParam(_CFG_STRM_ID_1, MOVIEMULTI_PARAM_WIFI_REG_CB, (UINT32)MovieExe_WifiCB); + ImageApp_MovieMulti_SetParam(_CFG_STRM_ID_1, MOVIEMULTI_PARAM_WIFI_REG_CB, (UINT32)MovieExe_WifiCB); ImageApp_MovieMulti_SetParam(_CFG_DISP_ID_1, MOVIEMULTI_PARAM_DISP_REG_CB, (UINT32)MovieExe_PipCB); #if (MOVIE_DIRECT_FUNC == ENABLE) @@ -2065,10 +2069,14 @@ INT32 MovieExe_OnOpen(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) #endif #endif #if(WIFI_AP_FUNC==ENABLE) - if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) { - Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id); - Ux_PostEvent(NVTEVT_WIFI_EXE_MODE_DONE,1,E_OK); - } + // if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) { + // Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id); + // Ux_PostEvent(NVTEVT_WIFI_EXE_MODE_DONE,1,E_OK); + // } + + DBG_DUMP("****NVTEVT_EXE_MOVIE_STRM_START"); + Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_START, 1,gMovie_Strm_Info.strm_id); + #endif #if MOVIE_UVAC_FUNC Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_UVAC_START, 0); @@ -2281,9 +2289,9 @@ INT32 MovieExe_OnClose(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) #endif #if(WIFI_AP_FUNC==ENABLE) - if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) { + // if (System_GetState(SYS_STATE_CURRSUBMODE) == SYS_SUBMODE_WIFI) { Ux_SendEvent(&CustomMovieObjCtrl, NVTEVT_EXE_MOVIE_STRM_STOP, 1,gMovie_Strm_Info.strm_id); - } + // } #endif ImageApp_MovieMulti_Close(); diff --git a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c index eb8edbbef..aa16b5435 100755 --- a/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c +++ b/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c @@ -106,7 +106,7 @@ MOVIE_RECODE_INFO gMovie_Clone_Info[SENSOR_MAX_NUM] = { #endif 30, //MOVIE_CFG_FRAME_RATE 250 * 1024, //MOVIE_CFG_TARGET_RATE - _CFG_CODEC_H264, //MOVIE_CFG_CODEC + _CFG_CODEC_H265, //MOVIE_CFG_CODEC _CFG_AUD_CODEC_AAC, //MOVIE_CFG_AUD_CODEC _CFG_REC_TYPE_AV, //MOVIE_CFG_REC_MODE #if (defined(_NVT_ETHREARCAM_TX_)) diff --git a/code/application/source/cardv/SrcCode/UIApp/MovieStamp/MovieStamp.c b/code/application/source/cardv/SrcCode/UIApp/MovieStamp/MovieStamp.c index abe9f2a50..5ddad76af 100644 --- a/code/application/source/cardv/SrcCode/UIApp/MovieStamp/MovieStamp.c +++ b/code/application/source/cardv/SrcCode/UIApp/MovieStamp/MovieStamp.c @@ -601,11 +601,13 @@ void MovieStamp_Setup(UINT32 uiVEncOutPortId, UINT32 uiFlag, UINT32 uiImageWidth break; } -#endif - -#if 0//MOVIE_ISP_LOG +#if MOVIE_ISP_LOG g_VsFontIn[uiVEncOutPortId].pFont=(FONT *)gDateStampFontTbl12x20; #endif + +#endif + + /* do water logo scaling*/ #if defined (WATERLOGO_FUNCTION) && (WATERLOGO_FUNCTION == ENABLE) { diff --git a/code/application/source/cardv/SrcCode/UIApp/Network/UIAppNetwork.c b/code/application/source/cardv/SrcCode/UIApp/Network/UIAppNetwork.c old mode 100755 new mode 100644 index 25ab62642..263c5a962 --- a/code/application/source/cardv/SrcCode/UIApp/Network/UIAppNetwork.c +++ b/code/application/source/cardv/SrcCode/UIApp/Network/UIAppNetwork.c @@ -1527,8 +1527,8 @@ INT32 UINet_WifiInit(UINT32 mode, UINT32 security) #if _TODO WiFiIpc_interface_config("wlan0", gCurrIP, "255.255.255.0"); #else - //WiFiIpc_interface_up("wlan0"); - sf_wifi_hw_init(); + WiFiIpc_interface_up("wlan0"); + //sf_wifi_hw_init(); #endif if (_g_bFirstWifi) { @@ -1660,7 +1660,7 @@ INT32 sf_net_wifi_uninit(UINT32 mode) //WifiCmd_UninstallID(); //UINet_RtspUnInit(); - ImageApp_Common_RtspStop(0); + // ImageApp_Common_RtspStop(0); return ret; } diff --git a/code/application/source/cardv/SrcCode/UIApp/Photo/UIAppPhoto_Exe.c b/code/application/source/cardv/SrcCode/UIApp/Photo/UIAppPhoto_Exe.c index 8d26ef6cd..1b7e7587a 100644 --- a/code/application/source/cardv/SrcCode/UIApp/Photo/UIAppPhoto_Exe.c +++ b/code/application/source/cardv/SrcCode/UIApp/Photo/UIAppPhoto_Exe.c @@ -6127,7 +6127,7 @@ INT32 PhotoExe_Preview_SliceEncode_CB2(void* user_data) } /* thumbnail date stamp */ - if(PhotoExe_Preview_SliceEncode_DateStamp(&video_frame_out_thumbnail, CAP_DS_EVENT_THUMB) != E_OK){ + if(PhotoExe_Preview_SliceEncode_DateStamp(&video_frame_out_thumbnail, CAP_DS_EVENT_QV) != E_OK){ goto EXIT; } @@ -6325,11 +6325,11 @@ INT32 PhotoExe_Preview_SliceEncode_CB3(void* user_data) #if HUNTING_CAMERA_MCU == ENABLE char folder[4], number[5]; - strncpy(folder, file_path + length - 21, 3); // 复制到目标数组 - folder[3] = '\0'; // 添加结尾符 + strncpy(folder, file_path + length - 21, 3); + folder[3] = '\0'; - strncpy(number, file_path + length - 8, 4); // 复制到目标数组 - number[4] = '\0'; // 添加结尾符 + strncpy(number, file_path + length - 8, 4); + number[4] = '\0'; snprintf(tmp, sizeof(tmp), "%sW%s%s.JPG", PHOTO_THUMB_PATH, folder, number); /* DCF 8.3 naming rule */ @@ -6354,7 +6354,7 @@ INT32 PhotoExe_Preview_SliceEncode_CB3(void* user_data) UIMenuStoreInfo *puiPara = sf_ui_para_get(); if(SF_CAM_MODE_PHOTO == puiPara->CamMode) { - sf_share_mem_file_down(0); + sf_share_mem_file_down(0, 0); } #endif } diff --git a/code/application/source/cardv/SrcCode/UIApp/Setup/UISetup_Exe.c b/code/application/source/cardv/SrcCode/UIApp/Setup/UISetup_Exe.c old mode 100755 new mode 100644 index 734d9c86c..1e86db183 --- a/code/application/source/cardv/SrcCode/UIApp/Setup/UISetup_Exe.c +++ b/code/application/source/cardv/SrcCode/UIApp/Setup/UISetup_Exe.c @@ -944,7 +944,7 @@ INT32 SetupExe_OnWifiStop(VControl *pCtrl, UINT32 paramNum, UINT32 *paramArray) } // stop live555 service - ImageApp_Common_RtspStop(0); + // ImageApp_Common_RtspStop(0); UINet_WifiUnInit(UI_GetData(FL_NetWorkMode)); #if ONVIF_FUNC diff --git a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIFlowLVGL/UIFlowWifiLinkOK/UIFlowWifiLinkOKEventCallback.c b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIFlowLVGL/UIFlowWifiLinkOK/UIFlowWifiLinkOKEventCallback.c old mode 100755 new mode 100644 index 852d14294..a9f3ba9d1 --- a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIFlowLVGL/UIFlowWifiLinkOK/UIFlowWifiLinkOKEventCallback.c +++ b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIFlowLVGL/UIFlowWifiLinkOK/UIFlowWifiLinkOKEventCallback.c @@ -46,12 +46,12 @@ static void UIFlowWiFiLinkOK_DHCP_REQ(lv_obj_t* obj, const LV_USER_EVENT_NVTMSG_ static void UIFlowWiFiLinkOK_DEAUTHENTICATED(lv_obj_t* obj, const LV_USER_EVENT_NVTMSG_DATA* msg) { -UINT32 Live555_rtcp_support; +// UINT32 Live555_rtcp_support; // stop live555 service - ImageApp_Common_GetParam(0,IACOMMON_PARAM_SUPPORT_RTCP,&Live555_rtcp_support); - if (Live555_rtcp_support==0) - ImageApp_Common_RtspStop(0); + // ImageApp_Common_GetParam(0,IACOMMON_PARAM_SUPPORT_RTCP,&Live555_rtcp_support); + // if (Live555_rtcp_support==0) + // ImageApp_Common_RtspStop(0); //#NT#2016/03/23#Isiah Chang -begin //#NT#add new Wi-Fi UI flow. diff --git a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h index dc0d6a27e..f17a1359f 100644 --- a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h +++ b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h @@ -220,5 +220,6 @@ #define DEFAULT_TIMESEND3_SWITCH SF_OFF #define DEFAULT_TIMESEND4_SWITCH SF_OFF #define DEFAULT_FTP_SWITCH SF_FTP_ON +#define DEFAULT_MULTISHOT_INTEVEL SF_MULTISHOT_INTEVEL_1S #endif diff --git a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c index 433f1409f..6e26133f3 100644 --- a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c +++ b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c @@ -1705,6 +1705,7 @@ void SysResetFlag(void) puiPara->GpsAntiTheftSwitch = DEFAULT_GPS_ANTI_THEFT_SWITCH; puiPara->BatteryLogSwitch = DEFAULT_BATTRERY_LOG_SWITCH; puiPara->FtpSwitch = DEFAULT_FTP_SWITCH; + puiPara->MultiShotIntevel = DEFAULT_MULTISHOT_INTEVEL; memset(puiPara ->FtpIp,'\0', sizeof(puiPara ->FtpIp)); memset(puiPara ->FtpPort, '\0', sizeof(puiPara ->FtpPort)); diff --git a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h index 63bd7a88b..0d701b496 100644 --- a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h +++ b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h @@ -1979,6 +1979,13 @@ typedef enum SF_FTP_MAX, } SF_FTP; +typedef enum { + SF_MULTISHOT_INTEVEL_0S = 0, + SF_MULTISHOT_INTEVEL_1S, + SF_MULTISHOT_INTEVEL_2S, + SF_MULTISHOT_INTEVEL_MAX, +} SF_MULTISHOT_INTEVEL_e; + extern void Load_SysInfo(void); extern void Save_SysInfo(void); extern void Init_SysInfo(void); diff --git a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIMovieMapping.c b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIMovieMapping.c index 2d335f2b8..7ea2883b2 100644 --- a/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIMovieMapping.c +++ b/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIMovieMapping.c @@ -62,7 +62,7 @@ typedef struct { #if (_BOARD_DRAM_SIZE_ == 0x04000000 || (defined(_NVT_ETHREARCAM_RX_) && ETH_REARCAM_CAPS_COUNT >=2)) #define MOVIE_SIZE_WIFI_STREAMING MOVIE_SIZE_640x360P30//MOVIE_SIZE_848x480P30_WIFI // always use 848x480 for WiFi streaming temporarily #else -#define MOVIE_SIZE_WIFI_STREAMING MOVIE_SIZE_848x480P30 // always use 848x480 for WiFi streaming temporarily +#define MOVIE_SIZE_WIFI_STREAMING MOVIE_SIZE_640x480P30 // always use 848x480 for WiFi streaming temporarily #endif typedef struct { @@ -195,9 +195,9 @@ static MOVIE_SIZE_ITEM g_MovieSizeTable[] = { }, [MOVIE_SIZE_640x480P30] = { - { 640, 480, 30, 150 * 1024, MEDIAREC_DAR_DEFAULT, IMAGERATIO_4_3}, + { 640, 480, 30, 200 * 1024, MEDIAREC_DAR_DEFAULT, IMAGERATIO_4_3}, {1, 3, 36, 8, -8, 0}, - {1, 4, 30, 150 * 1024, 30, 26, 15, 45, 26, 15, 45, 0, 1, 8, 4}, + {1, 4, 30, 200 * 1024, 30, 26, 15, 45, 26, 15, 45, 0, 1, 8, 4}, }, [MOVIE_SIZE_320x240P30] = { diff --git a/code/application/source/sf_app/code/include/sf_commMng.h b/code/application/source/sf_app/code/include/sf_commMng.h index aa7ec388c..edcf4f611 100644 --- a/code/application/source/sf_app/code/include/sf_commMng.h +++ b/code/application/source/sf_app/code/include/sf_commMng.h @@ -20,8 +20,7 @@ SINT32 sf_sem_up(SINT32 semid, SINT32 who); SINT32 sf_sem_deinit(SINT32 semid); SINT32 sf_share_mem_file_init(void); -SINT32 sf_share_mem_file_down(UINT32 to); - +SINT32 sf_share_mem_file_down(UINT32 to, SINT32 param); SINT32 sf_share_mem_file_deinit(void); SINT32 sf_share_mem_customer_update(void); diff --git a/code/application/source/sf_app/code/include/sf_wifi_svr.h b/code/application/source/sf_app/code/include/sf_wifi_svr.h index 529406f8c..5b19e86ef 100644 --- a/code/application/source/sf_app/code/include/sf_wifi_svr.h +++ b/code/application/source/sf_app/code/include/sf_wifi_svr.h @@ -940,6 +940,7 @@ void sf_get_wifi_ssid(char *ssid); int sf_is_ip_in_list(char *macbuf); UINT8 sf_get_wifi_type(void); void sf_wifi_app_start(void); +UINT8 sf_wifi_server_stop_shoot_respond(UINT8 errCode); diff --git a/code/application/source/sf_app/code/source/app/sf_service.c b/code/application/source/sf_app/code/source/app/sf_service.c index 01d5ede36..6d6a7aa16 100644 --- a/code/application/source/sf_app/code/source/app/sf_service.c +++ b/code/application/source/sf_app/code/source/app/sf_service.c @@ -996,9 +996,9 @@ static SINT16 app_file_transfer_Error_return_server(SF_FN_PARAM_S *pfnParam) return s32ret; } -static SINT16 app_file_transfer(SF_FN_PARAM_S *pfnParam) +static SINT32 app_file_transfer(SF_FN_PARAM_S *pfnParam) { - SINT16 s32ret = 0; + SINT32 s32ret = 0; SF_MESSAGE_BUF_S stMessageBuf = {0}; UIMenuStoreInfo *pCustomerParam = pfnParam->pstParam; SF_PDT_PARAM_STATISTICS_S *pStaticParam = pfnParam->pstaticParam; @@ -1087,7 +1087,7 @@ static SINT16 app_file_transfer(SF_FN_PARAM_S *pfnParam) SINT32 app_FileSend_thread(void) { - SINT16 s32ret = 0; + SINT32 s32ret = 0; SF_FN_PARAM_S stpfncallback = { 0 }; stpfncallback.pstParam = sf_customer_param_get(); stpfncallback.pstaticParam = sf_app_ui_para_get(); @@ -1104,7 +1104,7 @@ SINT32 app_FileSend_thread(void) MLOGE("ERROR:%#x\n", s32ret); ThumbSend.IsRun = 0; sf_file_thumb_cfg_clear(); - sf_share_mem_file_down(1); + sf_share_mem_file_down(1, s32ret); return s32ret; } @@ -1113,7 +1113,7 @@ SINT32 app_FileSend_thread(void) // app_file_transfer_Error_return_server(&stpfncallback); ThumbSend.IsRun = 0; sf_file_thumb_cfg_clear(); - sf_share_mem_file_down(1); + sf_share_mem_file_down(1, s32ret); return s32ret; diff --git a/code/application/source/sf_app/code/source/commMng/sf_share_mem.c b/code/application/source/sf_app/code/source/commMng/sf_share_mem.c index 0ee2c5c08..31737260a 100644 --- a/code/application/source/sf_app/code/source/commMng/sf_share_mem.c +++ b/code/application/source/sf_app/code/source/commMng/sf_share_mem.c @@ -188,7 +188,7 @@ SINT32 sf_share_mem_file_init(void) } -SINT32 sf_share_mem_file_down(UINT32 to) +SINT32 sf_share_mem_file_down(UINT32 to, SINT32 param) { SF_SRCFILE_ATTR_S *pThumbFileCfg = sf_file_thumb_cfg_get(); @@ -202,6 +202,7 @@ SINT32 sf_share_mem_file_down(UINT32 to) //sf_file_thumb_cfg_set_down(pThumbFileCfg); shmdt(pThumbFileCfg); SF_MESSAGE_BUF_S stMessageBuf = {0}; + stMessageBuf.arg2 = param; stMessageBuf.arg1 = SF_PARA_CMD_UPDATE; stMessageBuf.cmdId = CMD_FILE; if(to)//to cardv diff --git a/code/application/source/sf_app/code/source/wifi/sf_wifi_svr.c b/code/application/source/sf_app/code/source/wifi/sf_wifi_svr.c index c6f592f64..1ac5999ac 100644 --- a/code/application/source/sf_app/code/source/wifi/sf_wifi_svr.c +++ b/code/application/source/sf_app/code/source/wifi/sf_wifi_svr.c @@ -575,7 +575,7 @@ void appsvr_getFileList(UINT8 *dirPath, UINT8 *startFileKey) //printf("[appsvr_getFileList]nFileNums:%d, idx:%d, %s %d\n",nFileNums,idx,fname,gDevFileListNums); // printf("[appsvr_getFileList]nFileNums:%d, %d\n",nFileNums,gDevFileListNums); strcpy((char *)gDevFileList[nFileNums + gDevFileListNums].fileNameString, (char *)ptr->d_name); - gDevFileList[nFileNums + gDevFileListNums].srcFileType = ptr->d_name[3] - '0'; + gDevFileList[nFileNums + gDevFileListNums].srcFileType = (ptr->d_name[0] == 'W' ? 0 : (ptr->d_name[0] == 'S' ? 1 : 1));//ptr->d_name[3] - '0'; //printf("%s\n", g3g75DevFileList[nFileNums - idx + gDevFileListNums].fileName); nFileNums ++ ; //printf("[appsvr_getFileList]%d,%s\n",nFileNums - idx, gDevFileList[nFileNums - idx].fileName); @@ -927,7 +927,7 @@ void sf_app_Get_Camera_Para(MSG_DEV_Param_Get_Rsp_T *CamPara) //CamPara->imageSize = puiPara->ImgSize; - CamPara->multiShot = puiPara->Multishot-1; + CamPara->multiShot = puiPara->Multishot; CamPara->multiInterval = puiPara->MultiShotIntevel; CamPara->sendMulti = puiPara->SendMulti; CamPara->PirSensitivity = puiPara->PirSensitivity; @@ -1764,7 +1764,7 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8 *pAppData, UINT16 dataLen) DCF_DIR_FREE_CHAR, DCF_FILE_FREE_CHAR, tempbuf+4, - (tempbuf[3] == '0' ? ".JPG" : (tempbuf[3] == '1' ? ".MP4" : ".MP4"))); + (tempbuf[0] == 'W' ? ".JPG" : (tempbuf[0] == 'S' ? ".MP4" : ".MP4"))); } else { @@ -1788,7 +1788,7 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8 *pAppData, UINT16 dataLen) memcpy((char *)&msgParse.msgBuf.rctrlFileTransferInfo.filePath[0], (char *)fileName, strlen((char *)fileName)-12); //msgParse.msgBuf.rctrlFileTransferInfo.fileName[13]=0; // msgParse.msgBuf.rctrlFileTransferInfo.filePath[13]=0; - msgParse.msgBuf.rctrlFileTransferInfo.type = (tempbuf[3] == '0' ? 0 : (tempbuf[3] == '1' ? 1 : 1)); + msgParse.msgBuf.rctrlFileTransferInfo.type = (tempbuf[0] == 'W' ? 0 : (tempbuf[0] == 'S' ? 1 : 1)); } // printf("Send File:%s,function:%d,len:%d\n",msgParse.msgBuf.rctrlFileTransferInfo.fileName,function,strlen((char *)msgParse.msgBuf.rctrlFileTransferInfo.fileName)); if(function == 2)//download @@ -2079,6 +2079,41 @@ SINT32 sf_svr_packet_proc(SINT32 fd, UINT8 *pAppData, UINT16 dataLen) return ntohs(pMsgStruct->cmd); } + +void appSvrResponseSocketSet(SINT32 socket) +{ + //printf("appSvrResponseSocketSet socket=%d\n", socket); + gSendSocket = socket; +} + +UINT8 sf_wifi_server_stop_shoot_respond(UINT8 errCode) +{ + APP_SVR_PACKET_T msgParse; + UINT32 tmp = 0; + printf("sf_wifi_server_StopShootRespond errCode = %d gSendSocket=%d\n", errCode,gSendSocket); + + if(gSendSocket > 0) + { + //if(respFlag == 2) + { + //appUIParaSave(); + msgParse.msgBuf.rctrlReset.cmdRet = 0;//errCode; + msgParse.msgBuf.rctrlReset.suffix = htons(MSG_END_FIX); + msgParse.msglen = htons(sizeof(MSG_DEV_Reset_Ctrl_RSP_T) + 2*sizeof(UINT16) ); + } + + /* used for response */ + msgParse.magicNum = htons(MSG_PRE_FIX); + msgParse.cmd = htons(CurrentWifiCmd); + msgParse.rsp = htons(MSG_WIFI_2_APP); + /* add the magic + len total 2*2 bytes; */ + tmp=ntohs(msgParse.msglen); + send( gSendSocket,(void *)(&msgParse), (tmp + sizeof(UINT16)*2), 0); + } + + return 0; +} + static int connectNum=0; static char clientMacList[24]={0}; #if 0 @@ -2262,7 +2297,7 @@ void *sf_server_accept_thread(void *pData) } pClient = pClientContextHead ; - //appSvrResponseSocketSet(pClient->socket); //bad method it will error at socket over one---oliver + appSvrResponseSocketSet(pClient->socket); //bad method it will error at socket over one---oliver while(pClient != NULL) { diff --git a/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi b/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi old mode 100755 new mode 100644 index ec3058692..ceb7a44ad --- a/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi +++ b/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi @@ -7,7 +7,7 @@ version-info = [00 01 00 01]; ae_expect_lum { size = [b0 00 00 00]; - data = [3c 00 00 00 3c 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 44 00 00 00 44 00 00 00 44 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00]; + data = [3c 00 00 00 3c 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 27 00 00 00 2c 00 00 00 32 00 00 00 3a 00 00 00 44 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00]; }; ae_la_clamp { size = [50 01 00 00]; diff --git a/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi b/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi old mode 100755 new mode 100644 index dbeef5544..99eab2a2a --- a/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi +++ b/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi @@ -15,7 +15,7 @@ }; awb_ct_weight { size = [78 00 00 00]; - data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 05 00 00 00 10 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00]; + data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 04 00 00 00 08 00 00 00 09 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00]; }; awb_target { size = [24 00 00 00]; diff --git a/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi b/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi old mode 100755 new mode 100644 index afcda0174..975d30e65 --- a/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi +++ b/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi @@ -11,7 +11,7 @@ }; iq_nr { size = [f4 12 00 00]; - data = [01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 00 01 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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3c 00 00 00 3c 00 00 00 08 00 00 00 10 00 00 00 14 00 00 00 b4 00 00 00 e6 00 00 00 02 00 00 00 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 00 00 00 6e 00 00 00 78 00 00 00 82 00 00 00 80 00 00 00 40 00 00 00 b0 04 00 00 d0 07 00 00 14 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 14 00 00 00 18 00 00 00 18 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 00 00 00 00 20 00 00 00 80 00 00 00 ff 00 00 00 20 00 00 00 02 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 02 00 00 00 03 00 00 00 04 00 00 00 40 00 00 00 20 00 00 00 00 00 00 00 06 00 00 00 0b 00 00 00 0b 00 00 00 13 00 00 00 18 00 00 00 21 00 00 00 34 00 00 00 40 00 00 00 20 00 00 00 04 01 00 00]; }; iq_wdr { size = [e4 02 00 00]; - data = [01 00 00 00 01 00 00 00 20 00 00 00 12 00 00 00 80 00 00 00 05 00 00 00 03 00 00 00 00 00 00 00 01 00 00 00 03 00 00 00 07 00 00 00 0f 00 00 00 17 00 00 00 1f 00 00 00 23 00 00 00 27 00 00 00 29 00 00 00 2a 00 00 00 2b 00 00 00 2c 00 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00 fb 05 00 00 9c 05 00 00 46 05 00 00 f8 04 00 00 b0 04 00 00 70 04 00 00 35 04 00 00 00 04 00 00 a4 03 00 00 57 03 00 00 e4 02 00 00 94 02 00 00 5b 02 00 00 31 02 00 00 12 02 00 00 fb 01 00 00 e9 01 00 00 dc 01 00 00 d1 01 00 00 c8 01 00 00 c1 01 00 00 bb 01 00 00 b7 01 00 00 b3 01 00 00 b0 01 00 00 ad 01 00 00 ab 01 00 00 a9 01 00 00 a7 01 00 00 a6 01 00 00 a4 01 00 00 a3 01 00 00 a2 01 00 00 14 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00]; + data = 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0b 00 00 81 0b 00 00 2e 0b 00 00 da 0a 00 00 86 0a 00 00 33 0a 00 00 e1 09 00 00 90 09 00 00 41 09 00 00 f3 08 00 00 a7 08 00 00 5e 08 00 00 16 08 00 00 d1 07 00 00 8e 07 00 00 4d 07 00 00 0f 07 00 00 d3 06 00 00 99 06 00 00 62 06 00 00 fb 05 00 00 9c 05 00 00 46 05 00 00 f8 04 00 00 b0 04 00 00 70 04 00 00 35 04 00 00 00 04 00 00 a4 03 00 00 57 03 00 00 e4 02 00 00 94 02 00 00 5b 02 00 00 31 02 00 00 12 02 00 00 fb 01 00 00 e9 01 00 00 dc 01 00 00 d1 01 00 00 c8 01 00 00 c1 01 00 00 bb 01 00 00 b7 01 00 00 b3 01 00 00 b0 01 00 00 ad 01 00 00 ab 01 00 00 a9 01 00 00 a7 01 00 00 a6 01 00 00 a4 01 00 00 a3 01 00 00 a2 01 00 00 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00]; }; iq_shdr { size = [ec 01 00 00]; diff --git a/code/hdal/vendor/output/libvendor_ai2_pub.a b/code/hdal/vendor/output/libvendor_ai2_pub.a index 31e3181df..5c2365748 100644 Binary files a/code/hdal/vendor/output/libvendor_ai2_pub.a and b/code/hdal/vendor/output/libvendor_ai2_pub.a differ diff --git a/code/hdal/vendor/output/libvendor_ai2_pub2.a b/code/hdal/vendor/output/libvendor_ai2_pub2.a index ea3bc1a47..0f329b92d 100644 Binary files a/code/hdal/vendor/output/libvendor_ai2_pub2.a and b/code/hdal/vendor/output/libvendor_ai2_pub2.a differ diff --git a/code/lib/source/ImageApp/Common/libimageapp_common.a b/code/lib/source/ImageApp/Common/libimageapp_common.a index ddf99af3e..8c052ff74 100644 Binary files a/code/lib/source/ImageApp/Common/libimageapp_common.a and b/code/lib/source/ImageApp/Common/libimageapp_common.a differ diff --git a/code/lib/source/ImageApp/Common/libimageapp_common.so b/code/lib/source/ImageApp/Common/libimageapp_common.so index 2c73f8e4a..d0e3a2036 100755 Binary files a/code/lib/source/ImageApp/Common/libimageapp_common.so and b/code/lib/source/ImageApp/Common/libimageapp_common.so differ diff --git a/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.a b/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.a index 20953f12e..639070553 100644 Binary files a/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.a and b/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.a differ diff --git a/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.so b/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.so index 47a86da85..3b2ed4f3e 100755 Binary files a/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.so and b/code/lib/source/ImageApp/MovieMulti/libimageapp_moviemulti.so differ diff --git a/code/lib/source/ImageApp/Photo/libimageapp_photo.a b/code/lib/source/ImageApp/Photo/libimageapp_photo.a index 3c7ac177c..479f299bb 100644 Binary files a/code/lib/source/ImageApp/Photo/libimageapp_photo.a and b/code/lib/source/ImageApp/Photo/libimageapp_photo.a differ diff --git a/code/lib/source/ImageApp/Photo/libimageapp_photo.so b/code/lib/source/ImageApp/Photo/libimageapp_photo.so index 05ad5221f..8adb2ff3c 100755 Binary files a/code/lib/source/ImageApp/Photo/libimageapp_photo.so and b/code/lib/source/ImageApp/Photo/libimageapp_photo.so differ diff --git a/code/lib/source/nvtlive555/release/nvtlive555/lib/libnvtlive555.a b/code/lib/source/nvtlive555/release/nvtlive555/lib/libnvtlive555.a index 23223a5f4..19d6a8302 100644 Binary files a/code/lib/source/nvtlive555/release/nvtlive555/lib/libnvtlive555.a and b/code/lib/source/nvtlive555/release/nvtlive555/lib/libnvtlive555.a differ diff --git a/code/lib/source/sifar/code/source/common/sf_battery.c b/code/lib/source/sifar/code/source/common/sf_battery.c index f253c2e96..d23412315 100644 --- a/code/lib/source/sifar/code/source/common/sf_battery.c +++ b/code/lib/source/sifar/code/source/common/sf_battery.c @@ -159,7 +159,7 @@ UINT32 sf_adc_value_get(UINT32 mux, UINT32 *pval) gpio_set_value(P_GPIO_1, 1);//adc_muxb } - vos_util_delay_us(1000); + vos_util_delay_ms(3); *pval = adc_readData(0); //printf("[%s:%d] *pval:%d\n", __FUNCTION__, __LINE__,*pval); @@ -479,7 +479,7 @@ signed int sf_battery_adc_value_get(void) if((sf_get_mode_flag() == 0) || (needCheckFirst == TRUE)) { - //printf("[%s:%d]ConfigureModeFlag=%d,needCheckFirst=%d\n",__FUNCTION__,__LINE__,ConfigureModeFlag,needCheckFirst); + printf("[%s:%d]ConfigureModeFlag=%d,needCheckFirst=%d\n",__FUNCTION__,__LINE__,sf_get_mode_flag(),needCheckFirst); needCheckFirst = FALSE; for(readBatCnt = 0; readBatCnt < 5;) //get max value of 5 times. @@ -763,6 +763,7 @@ THREAD_RETTYPE sf_battery_check_thread(void *arg) { THREAD_ENTRY(); printf("[%s:%d] s\n", __FUNCTION__, __LINE__); + sf_battery_check_init(); while(sf_while_flag()) { diff --git a/code/lib/source/sifar/code/source/common/sf_common.c b/code/lib/source/sifar/code/source/common/sf_common.c index 2325e2ff5..dc0a103a4 100644 --- a/code/lib/source/sifar/code/source/common/sf_common.c +++ b/code/lib/source/sifar/code/source/common/sf_common.c @@ -59,6 +59,7 @@ #include #include #include "UIAppNetwork.h" +#include BOOL isGoing2PowerOff = FALSE; UINT16 AutoOfftime = 0; @@ -1121,14 +1122,14 @@ UINT32 sf_set_pir_sensitivity(UINT8 pirs) puiPara->DigitPirCnt = digPirCount[pirs]; puiPara->DigitPirWindowTime = 0; - if(puiPara->PirSensitivity) + /*if(puiPara->PirSensitivity) { puiPara->TimelapseSwitch = SF_OFF; puiPara->TimelapseTime.Hour = 0; puiPara->TimelapseTime.Min = 0; puiPara->TimelapseTime.Sec = 0; //Save_MenuInfo(); - } + }*/ return SUCCESS; } @@ -1401,6 +1402,27 @@ static SINT32 sf_cardv_proccess_cmd_wifi(SF_MESSAGE_BUF_S *pMessageBuf) return SF_SUCCESS; } +static SINT32 sf_cardv_proccess_cmd_file(SF_MESSAGE_BUF_S *pMessageBuf) +{ + printf("[%s:%d] ID = %#x\n", __FUNCTION__, __LINE__,pMessageBuf->arg1); + //UIMenuStoreInfo *puiPara = sf_ui_para_get(); + + switch(pMessageBuf->arg1) + { + case SF_PARA_CMD_UPDATE: + sf_share_mem_file_init(); + //if(SF_CAM_MODE_PHOTO_VIDEO == puiPara->CamMode) + { + sf_wifi_server_stop_shoot_respond((UINT8)pMessageBuf->arg2); + } + break; + + default: + break; + } + return SF_SUCCESS; +} + void* sf_cardv_message_thread(void *argv) { SINT32 ret = 0; @@ -1412,7 +1434,7 @@ void* sf_cardv_message_thread(void *argv) { continue; } - printf("cmdId:%#x,paramBuf[%d]\n",stMessagebuf.cmdId,stMessagebuf.arg1); + printf("[%s:%d]cmdId:%#x,paramBuf[%d]\n", __FUNCTION__, __LINE__,stMessagebuf.cmdId,stMessagebuf.arg1); switch(stMessagebuf.cmdId) { case CMD_MCU: @@ -1428,7 +1450,7 @@ void* sf_cardv_message_thread(void *argv) //sf_cardv_proccess_cmd_gprs(&stMessagebuf); break; case CMD_FILE: - sf_share_mem_file_init(); + sf_cardv_proccess_cmd_file(&stMessagebuf); break; case CMD_WIFI: sf_cardv_proccess_cmd_wifi(&stMessagebuf); diff --git a/code/na51089_linux_sdk_app_filelist.txt b/code/na51089_linux_sdk_app_filelist.txt index 07d245461..a7176f2f7 100644 --- a/code/na51089_linux_sdk_app_filelist.txt +++ b/code/na51089_linux_sdk_app_filelist.txt @@ -1,6 +1,6 @@ ; Source Insight Project File List ; Project Name: s530_app -; Generated by Source Insight 4.00.0107 at 2023/5/22 16:12:40 +; Generated by Source Insight 4.00.0107 at 2023/5/29 17:59:28 ; Version=4.00.0107 ; ; Each line should contain either a file name, a wildcard, or a sub-directory name. @@ -604,9 +604,7 @@ application\source\sf_app\code\include\sf_system.h application\source\sf_app\code\include\sf_systemMng.h application\source\sf_app\code\include\sf_transdata1.h application\source\sf_app\code\include\sf_type.h -application\source\sf_app\code\include\sf_wifi_data_transfer.h application\source\sf_app\code\include\sf_wifi_svr.h -application\source\sf_app\code\include\sf_wifi_svr_send.h application\source\sf_app\code\include\sha256.h application\source\sf_app\code\include\split.h application\source\sf_app\code\source\4gMng\sf_4G_auto_operation.c @@ -670,9 +668,7 @@ application\source\sf_app\code\source\utils\sf_qrutils.c application\source\sf_app\code\source\wifi\sf_data_transfer.c application\source\sf_app\code\source\wifi\sf_getapinfo.c application\source\sf_app\code\source\wifi\sf_svr_send.c -application\source\sf_app\code\source\wifi\sf_wifi_data_transfer.c application\source\sf_app\code\source\wifi\sf_wifi_svr.c -application\source\sf_app\code\source\wifi\sf_wifi_svr_send.c application\source\sf_app\component\liveMng\inc\exports\aiot_authorize_api.h application\source\sf_app\component\liveMng\inc\exports\iot_export_awss.h application\source\sf_app\component\liveMng\inc\exports\iot_export_coap.h diff --git a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/ModelConfig.mk b/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/ModelConfig.mk deleted file mode 100644 index 5687ccfbf..000000000 --- a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/ModelConfig.mk +++ /dev/null @@ -1,63 +0,0 @@ -#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -#!automatically-generated file. do not edit!! -#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - -BOARD_DRAM_ADDR = 0x00000000 -BOARD_DRAM_SIZE = 0x08000000 -BOARD_SHMEM_ADDR = 0x00007E00 -BOARD_SHMEM_SIZE = 0x00000200 -BOARD_LOADER_ADDR = 0x01000000 -BOARD_LOADER_SIZE = 0x00080000 -BOARD_FDT_ADDR = 0x01800000 -BOARD_FDT_SIZE = 0x00040000 -BOARD_RTOS_ADDR = 0x01840000 -BOARD_RTOS_SIZE = 0x00FC0000 -BOARD_LINUXTMP_ADDR = 0x02800000 -BOARD_LINUXTMP_SIZE = 0x04000000 -BOARD_UBOOT_ADDR = 0x06800000 -BOARD_UBOOT_SIZE = 0x01640000 -BOARD_LOGO-FB_ADDR = 0x07E40000 -BOARD_LOGO-FB_SIZE = 0x001C0000 -BOARD_LINUX_ADDR = 0x00000000 -BOARD_LINUX_SIZE = 0x01800000 -BOARD_LINUX_MAXBLK_ADDR = 0x00000000 -BOARD_LINUX_MAXBLK_SIZE = 0x01800000 -BOARD_MEDIA_ADDR = 0x03600000 -BOARD_MEDIA_SIZE = 0x04A00000 -BIN_NAME = FW98565A -BIN_NAME_T = FW98565T -RTOS_APP_MAIN = cardv -EMBMEM_BLK_SIZE = 0x10000 -EMBMEM = EMBMEM_SPI_NOR -FW_TYPE = FW_TYPE_PARTIAL -UI_STYLE = UI_STYLE_LVGL -NVT_CFG_APP_EXTERNAL = hostapd wireless_tool iperf-3 wpa_supplicant dhd_priv -NVT_CFG_APP = mem cardv memcpy isp_demon sf_app -NVT_ROOTFS_ETC = -NVT_BINARY_FILE_STRIP = yes -NVT_CFG_KERNEL_CFG = na51089_evb_cardv_defconfig_release -NVT_MAKE_POST = make_post.sh -NVT_SAMPLES_INSTALL = DISABLE -NVT_CFG_UBOOT_CFG = -NVT_LINUX_SMP = NVT_LINUX_SMP_OFF -NVT_CHIP_ID = CHIP_NA51089 -NVT_LINUX_COMPRESS = NVT_LINUX_COMPRESS_GZ -NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP -NVT_ROOTFS_TYPE = NVT_ROOTFS_TYPE_RAMDISK -LCD1 = disp_if8b_lcd1_psd200_st7789v -SENSOR1 = sen_os05b10 -SENSOR1_CFG = sen_os05b10_565 -SENSOR2 = sen_off -SENSOR2_CFG = sen_off -NVT_ROOTFS_RW_PART_EN = NVT_ROOTFS_RW_PART_EN_ON -NVT_ETHERNET = NVT_ETHERNET_NONE -NVT_SDIO_WIFI = NVT_SDIO_WIFI_RTK -NVT_USB_WIFI = NVT_USB_WIFI_NONE -NVT_USB_4G = NVT_USB_4G_NONE -WIFI_RTK_MDL = WIFI_RTK_MDL_8189 -WIFI_BRCM_MDL = WIFI_BRCM_MDL_43456c5_ampk6256c5 -WIFI_NVT_MDL = WIFI_NVT_MDL_18211 -NVT_CURL_SSL = NVT_CURL_SSL_OPENSSL -NVT_UBOOT_ENV_IN_STORG_SUPPORT = NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF -TOUCH = TOUCH_OFF -UBOOT_ONLY_LOAD_LINUX = UBOOT_ONLY_LOAD_LINUX_ON diff --git a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.dtb b/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.dtb deleted file mode 100644 index 58540b0c9..000000000 Binary files a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.dtb and /dev/null differ diff --git a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.tmp.dts b/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.tmp.dts deleted file mode 100644 index fa2e3c18e..000000000 --- a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-evb.tmp.dts +++ /dev/null @@ -1,1181 +0,0 @@ -# 1 "nvt-evb.dts" -# 1 "" -# 1 "" -# 1 "nvt-evb.dts" - - - - - - - -/dts-v1/; -# 1 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/gpio/nvt-gpio.h" 1 -# 13 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/gpio/nvt-gpio.h" -# 1 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/gpio/gpio.h" 1 -# 14 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/gpio/nvt-gpio.h" 2 -# 10 "nvt-evb.dts" 2 -# 1 "nvt-peri.dtsi" 1 -# 10 "nvt-peri.dtsi" -# 1 "nvt-basic.dtsi" 1 -# 9 "nvt-basic.dtsi" -# 1 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/interrupt-controller/arm-gic.h" 1 -# 9 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/interrupt-controller/arm-gic.h" -# 1 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/interrupt-controller/irq.h" 1 -# 10 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/interrupt-controller/arm-gic.h" 2 -# 10 "nvt-basic.dtsi" 2 - -/ { - model = "Novatek NA51089"; - compatible = "novatek,na51089", "nvt,ca9"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - clock-frequency = <960000000>; - }; - }; - - cg@f0020000 { - compatible = "nvt,core_clk"; - reg = <0xf0020000 0x1000>; - }; - - - periph_clk: periph_clk { - compatible = "nvt,periph_clk"; - #clock-cells = <0>; - clock-output-names = "periph_clk"; - }; - - global_timer@ffd00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xffd00200 0x20>; - interrupts = <1 11 0xf01>; - clocks = <&periph_clk>; - }; - - private_timer@ffd00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffd00600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&periph_clk>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 112 4>; - interrupt-affinity = <&cpu0>; - }; - - L2: cache-controller@ffe00000 { - compatible = "arm,pl310-cache"; - reg = <0xffe00000 0x1000>; - interrupts = <0 96 4>; - cache-unified; - arm,shared-override; - cache-level = <2>; - arm,data-latency = <2 2 2>; - arm,tag-latency = <2 2 2>; - }; - - gic: interrupt-controller@0xffd00000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffd01000 0x1000>, - <0xffd00100 0x1000>; - }; - - scu: snoop-control-unit@0xffd00000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xffd00000 0x100>; - }; -}; -# 11 "nvt-peri.dtsi" 2 - -/ { - chosen { - bootargs = " "; - }; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - }; - - uart@f0290000 { - compatible = "ns16550a"; - reg = <0xf0290000 0x1000>; - interrupts = <0 43 4>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - clock-frequency = <24000000>; - fifo-size = <64>; - uart_id = <0>; - }; - - uart@f0300000 { - compatible = "ns16550a"; - reg = <0xf0300000 0x1000>; - interrupts = <0 44 4>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - clock-frequency = <48000000>; - fifo-size = <64>; - hw_flowctrl = <0>; - rx_trig_level = <3>; - uart_id = <1>; - }; - - uart@f0310000 { - compatible = "ns16550a"; - reg = <0xf0310000 0x1000>; - interrupts = <0 45 4>; - baud = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - no-loopback-test = <1>; - clock-frequency = <48000000>; - fifo-size = <64>; - hw_flowctrl = <0>; - rx_trig_level = <3>; - uart_id = <2>; - }; - - kdrv_rpc: cc@f0090000 { - compatible = "kdrv_rpc"; - reg = <0xf0090000 0x300>; - interrupts = <0 59 4>; - }; - - mmc0: mmc@f0420000 { - compatible = "nvt,nvt_mmc"; - reg = <0xf0420000 0x1000>; - interrupts = <0 30 4>; - max-frequency = <48000000>; - voltage-switch = <0>; - max-voltage = <3300>; - bus-width = <4>; - neg-sample-edge = <0>; - driving = <15 15 15 20 15 15 25 25 25 25 25 25>; - cd_gpio = <(9) 0x0 0x0>; - card_power_gpio = <(7 + 0x20) 0x0>; - - - }; - - mmc1: mmc@f0500000 { - compatible = "nvt,nvt_mmc2"; - reg = <0xf0500000 0x1000>; - interrupts = <0 31 4>; - max-frequency = <48000000>; - voltage-switch = <0>; - max-voltage = <3300>; - bus-width = <4>; - neg-sample-edge = <0>; - driving = <15 8 8 20 8 8 20 8 8 20 8 8>; - cd_gpio = <0 0x0 0x1>; - - - - }; - - nand: nand@f0400000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "nvt,nvt_spinand"; - reg = <0xf0400000 0x1000>; - interrupts = <0 29 4>; - clock-frequency = <96000000>; - nvt-devname = "spi_nand.0"; - }; - - nor: nor@f0400000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "nvt,nvt_spinor"; - reg = <0xf0400000 0x1000>; - interrupts = <0 29 4>; - clock-frequency = <120000000>; - nvt-devname = "spi_nor.0"; - trace-stdtable = <0>; - }; - - gpio: gpio@f0070000 { - compatible = "nvt,nvt_gpio"; - reg = <0xf0070000 0x10000>; - interrupts = <0 24 4>; - #gpio-cells = <2>; - }; - - eth@f02b0000 { - compatible = "nvt,synopsys_eth"; - reg = <0xf02b0000 0x3800>; - interrupts = <0 34 4>; - sp-clk = <0>; - ref-clk-out = <0>; - }; - - phy@f02b3800 { - compatible = "nvt,eth_phy"; - reg = <0xf02b3800 0x400>; - }; - - wdt@f0050000 { - compatible = "nvt,nvt_wdt"; - reg = <0xf0050000 0x10000>; - interrupts = <0 57 4>; - }; - - pwm: pwm@f0210000 { - compatible = "nvt,nvt_kdrv_pwm"; - reg = <0xf0210000 0x2000>; - interrupts = <0 26 4>; - }; - - adc@f0260000 { - compatible = "nvt,nvt_adc"; - reg = <0xf0260000 0x1000>; - interrupts = <0 47 4>; - #io-channel-cells = <1>; - }; - - rtc@f0060000 { - compatible = "nvt,nvt_rtc"; - reg = <0xf0060000 0x100>; - interrupts = <0 56 4>; - }; - - drtc@f00b0000 { - compatible = "nvt,nvt_drtc"; - reg = <0xf00b0000 0x100>; - }; - - crypto: crypto@f0620000 { - compatible = "nvt,nvt_crypto"; - reg = <0xf0620000 0x100>; - interrupts = <0 38 4>; - mclk = <1>; - }; - - hash: hash@f0670000 { - compatible = "nvt,nvt_hash"; - reg = <0xf0670000 0x100>; - interrupts = <0 28 4>; - mclk = <1>; - }; - - rsa: rsa@f06a0000 { - compatible = "nvt,nvt_rsa"; - reg = <0xf06a0000 0x100>; - interrupts = <0 20 4>; - mclk = <1>; - }; - - top: top@f0010000 { - compatible = "nvt,nvt_top"; - reg = <0xf0010000 0x2000 - 0xf0030000 0x2000 - 0xf0070000 0x10000>; - }; - - sie@f0c00000 { - compatible = "nvt,drv_sie"; - reg = <0xf0c00000 0x900 - 0xf0d20000 0x900 - 0xF0D30000 0x900>; - interrupts = <0 1 4 - 0 2 4 - 0 3 4>; - - }; - - tge@f0cc0000 { - compatible = "nvt,kdrv_tge"; - reg = <0xf0cc0000 0x150>; - interrupts = <0 22 4>; - }; - - rhe@f0ce0000 { - compatible = "nvt,kdrv_rhe"; - reg = <0xf0ce0000 0x900>; - interrupts = <0 13 4>; - }; - - ime@f0c40000 { - compatible = "nvt,kdrv_ime"; - reg = <0xf0c40000 0x1000>; - interrupts = <0 6 4>; - }; - - ife2@f0d00000 { - compatible = "nvt,kdrv_ife2"; - reg = <0xf0d00000 0x100>; - interrupts = <0 9 4>; - }; - - ise@f0c90000 { - compatible = "nvt,kdrv_ise"; - reg = <0xf0c90000 0x100>; - interrupts = <0 21 4 - 0 85 4>; - }; - - ipe@f0c30000 { - compatible = "nvt,kdrv_ipe"; - reg = <0xf0c30000 0x900>; - interrupts = <0 5 4>; - }; - - ife@f0c70000 { - compatible = "nvt,kdrv_ife"; - reg = <0xf0c70000 0x800>; - interrupts = <0 8 4>; - }; - - vpe@f0cd0000 { - compatible = "nvt,kdrv_vpe"; - reg = <0xf0cd0000 0x1040>; - interrupts = <0 62 4>; - }; - - ai@f0c60000 { - compatible = "nvt,kdrv_ai"; - reg = <0xf0c60000 0x23c - 0xf0d50000 0x114 - 0xf0cb0000 0x22c>; - interrupts = <0 14 4 - 0 13 4 - 0 11 4>; - clock-frequency = <600000000 480000000 600000000>; - }; - - md@f0c10000 { - compatible = "nvt,kdrv_md"; - reg = <0xf0c10000 0x150>; - interrupts = <0 46 4>; - clock-frequency = <240000000>; - }; - dis@f0c50000 { - compatible = "nvt,kdrv_dis"; - reg = <0xf0c50000 0x114>; - interrupts = <0 10 4>; - }; - - coe@f0a11000 { - compatible = "nvt,nvt_coe"; - reg = <0xf0a11000 0x2c0>; - }; - - dce@f0c20000 { - compatible = "nvt,kdrv_dce"; - reg = <0xf0c20000 0x650>; - interrupts = <0 7 4>; - }; - - ive@f0d70000 { - compatible = "nvt,kdrv_ive"; - reg = <0xf0d70000 0x6c>; - interrupts = <0 53 4>; - }; - - sde@f0d90000 { - compatible = "nvt,kdrv_sde"; - reg = <0xf0d90000 0x90>; - interrupts = <0 74 4>; - }; - - ide@f0800000 { - compatible = "nvt,nvt_ide"; - reg = <0xf0800000 0x1000>; - interrupts = <0 48 4>; - }; - - dsi@f0840000 { - compatible = "nvt,nvt_dsi"; - reg = <0xf0840000 0x1000>; - interrupts = <0 50 4>; - }; - - csi@f0280000 { - compatible = "nvt,nvt_csi"; - reg = <0xf0280000 0x100 - 0xf0330000 0x100>; - interrupts = <0 54 4 - 0 55 4>; - }; - - lvds@f0270000 { - compatible = "nvt,nvt_lvds"; - reg = <0xF0270000 0x200 - 0xF0370000 0x200>; - interrupts = <0 54 4 - 0 55 4>; - }; - - senphy@f06b0000 { - compatible = "nvt,nvt_senphy"; - reg = <0xF06B0000 0x100>; - }; - - ssenif@f0xx0000 { - compatible = "nvt,nvt_ssenif"; - reg = <0xF02C0000 0x2000>; - interrupts = <0 61 4>; - }; - - sif@f0240000 { - compatible = "nvt,nvt_sif"; - reg = <0xf0240000 0x200>; - interrupts = <0 40 4>; - clock-frequency = <1000000>; - }; - - graphic@f0c80000 { - compatible = "nvt,nvt_graphic"; - reg = <0xF0C80000 0x300 - 0xF0D10000 0x100>; - interrupts = <0 18 4 - 0 19 4>; - }; - - affine@f0ca0000 { - compatible = "nvt,nvt_affine"; - reg = <0xF0CA0000 0x100>; - interrupts = <0 52 4>; - }; - - h26x@f0a10000 { - compatible = "nvt,nvt_h26x"; - reg = <0xf0a10000 0xa00>; - interrupts = <0 16 4>; - power_saving = <0>; - }; - - timer@f0040000 { - compatible = "nvt,nvt_timer"; - reg = <0xf0040000 0x300>; - interrupts = <0 0 4>; - }; - - eac@f0640000 { - compatible = "nvt,nvt_eac"; - reg = <0xF0640000 0x200>; - }; - - jpg@f0a00000 { - compatible = "nvt,nvt_jpg"; - reg = <0xf0a00000 0x100>; - interrupts = <0 17 4>; - }; - - nvt_usb2host@f0600000 { - compatible = "nvt,ehci-nvtivot"; - reg = <0xf0600000 0x10000>; - interrupts = <0 27 4>; - }; - - nvt_usb2dev@f0600000 { - compatible = "nvt,fotg200_udc"; - reg = <0xf0600000 0x10000>; - interrupts = <0 27 4>; - }; - - nvt_usb_chrg@f0600000 { - compatible = "nvt,nvt_usb_chrgdet"; - reg = <0xf0600000 0x10000>; - }; - - dai@f0630000 { - compatible = "nvt,nvt_dai"; - reg = <0xF0630000 0xbc>; - interrupts = <0 15 4>; - }; - - rotate@f0cf0000 { - compatible = "nvt,nvt_rotation"; - reg = <0xF0CF0000 0x100>; - interrupts = <0 81 4>; - }; - - drvdump@0 { - compatible = "nvt,nvt_drvdump"; - }; - - dsp@f1430000 { - compatible = "nvt,nvt_dsp"; - reg = <0xF1430000 0x200 - 0xF2000000 0x1000000 - 0xF1440000 0x200 - 0xF3000000 0x1000000>; - interrupts = <0 76 4 - 0 77 4>; - }; - - spi0: spi@f0230000 { - compatible = "nvt,nvt_spi"; - reg = <0xf0230000 0x10000>; - interrupts = <0 35 4>; - dma-support = <0>; - nvt-devname = <0>; - }; - - spi1: spi@f0320000 { - compatible = "nvt,nvt_spi"; - reg = <0xf0320000 0x10000>; - interrupts = <0 36 4>; - dma-support = <0>; - nvt-devname = <1>; - }; - - spi2: spi@f0340000 { - compatible = "nvt,nvt_spi"; - reg = <0xf0340000 0x10000>; - interrupts = <0 37 4>; - dma-support = <0>; - nvt-devname = <2>; - }; - - sdp@f0390000 { - compatible = "nvt,nvt_sdp"; - reg = <0xf0390000 0x28>; - interrupts = <0 12 4>; - }; - - tse@f0650000 { - compatible = "nvt,nvt_tse"; - reg = <0xF0650000 0x90>; - interrupts = <0 23 4>; - }; - - remote@f0250000 { - compatible = "nvt,nvt_remote"; - reg = <0xf0250000 0x28>; - interrupts = <0 25 4>; - }; - - rng: rng@f0680000 { - compatible = "nvt,nvt_rng"; - reg = <0xf0680000 0x100>; - }; - - nvt_arb@f0000000 { - compatible = "nvt,nvt_arb"; - reg = <0xF0000000 0xA000 - 0xF0FE0000 0x300>; - interrupts = <0 33 4>; - }; - - nvt_otp@f0660000 { - compatible = "nvt,nvt_otp"; - reg = <0xF0660000 0x70>; - }; - - kdrv_ipp { - clock-frequency = <240000000>; - }; - - uvcp: uvcp@f0690000 { - compatible = "nvt,nvt_uvcp"; - reg = <0xf0690000 0x200>; - interrupts = <0 59 4>; - }; - pll_preset@0 { - pll3{pll_config = <3 0 0>;}; - pll4{pll_config = <4 0 0>;}; - pll5{pll_config = <5 297000000 1>;}; - pll6{pll_config = <6 0 0>;}; - pll7{pll_config = <7 0 0>;}; - pll8{pll_config = <8 0 0>;}; - pll9{pll_config = <9 0 0>;}; - pll11{pll_config = <11 0 0>;}; - pll12{pll_config = <12 0 1>;}; - }; -}; -# 11 "nvt-evb.dts" 2 -# 1 "nvt-top.dtsi" 1 -&top { - sdio{pinmux = <0x5>;}; - sdio2{pinmux = <0x5>;}; - sdio3{pinmux = <0x0>;}; - nand{pinmux = <0x5>;}; - sensor{pinmux = <0x0>;}; - sensor2{pinmux = <0x0>;}; - mipi_lvds{pinmux = <0x0>;}; - i2c{pinmux = <0x40>;}; - sif{pinmux = <0x0>;}; - uart{pinmux = <0x1021>;}; - spi{pinmux = <0x0>;}; - sdp{pinmux = <0x0>;}; - remote{pinmux = <0x0>;}; - pwm{pinmux = <0x8000>;}; - pwm2{pinmux = <0x000000>;}; - ccnt{pinmux = <0x0>;}; - audio{pinmux = <0x0>;}; - lcd{pinmux = <0x0>;}; - tv{pinmux = <0x0>;}; - eth{pinmux = <0x0>;}; - misc{pinmux = <0x0>;}; -}; -# 12 "nvt-evb.dts" 2 -# 1 "nvt-i2c.dtsi" 1 - - - - - - - -/ { - i2c0: i2c@f0220000 { compatible = "nvt,nvt_i2c"; reg = <0xf0220000 0x100>; interrupts = <0 41 4>; clock-frequency = <400000>; id = <0>; }; - i2c1: i2c2@f0350000 { compatible = "nvt,nvt_i2c"; reg = <0xf0350000 0x100>; interrupts = <0 42 4>; clock-frequency = <400000>; id = <1>; }; - i2c2: i2c3@f03a0000 { compatible = "nvt,nvt_i2c"; reg = <0xf03a0000 0x100>; interrupts = <0 60 4>; clock-frequency = <50000>; id = <2>; }; -}; -# 13 "nvt-evb.dts" 2 -# 1 "nvt-gpio.dtsi" 1 -&top { -# 201 "nvt-gpio.dtsi" - pgpio11{gpio_config = <(11 + 0x20) 1>;}; - - pgpio2{gpio_config = <(2 + 0x20) 1>;}; -}; -# 14 "nvt-evb.dts" 2 -# 1 "nvt-peri-dev.dtsi" 1 -# 11 "nvt-peri-dev.dtsi" -&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - - - - - - -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; -}; - -&i2c2 { - #address-cells = <1>; - #size-cells = <0>; -}; - -&spi0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; -# 44 "nvt-peri-dev.dtsi" -}; - -&spi1 { - status = "okay"; -}; - -&spi2 { - status = "okay"; -}; -# 15 "nvt-evb.dts" 2 -# 1 "nvt-audio.dtsi" 1 - - - - - - - -/ { - audio@1 { type = "none"; i2s_ctrl = <0>; sif_channel = <0>; gpio_cold_reset = <0>; gpio_data = <0>; gpio_clk = <0>; gpio_cs = <0>; adc_zero = <0>; }; - audio@2 { type = "embedded"; i2s_ctrl = <4>; sif_channel = <0>; gpio_cold_reset = <0>; gpio_data = <0>; gpio_clk = <0>; gpio_cs = <0>; adc_zero = <0>; }; -}; -# 16 "nvt-evb.dts" 2 -# 1 "nvt-display.dtsi" 1 - - - - - - - -# 1 "/home/payton/S530/BSP/linux-kernel/include/dt-bindings/pinctrl/nvt_lcd.h" 1 -# 9 "nvt-display.dtsi" 2 -# 25 "nvt-display.dtsi" -/ { - display { type = "lcd"; lcd_ctrl = <1>; sif_channel = <4>; gpio_cs = <(7 + 0x20)>; gpio_clk = <(8 + 0x20)>; gpio_data = <(9 + 0x20)>; }; - logo { enable = <1>; lcd_type = <5>; lcd_rotate = <270>; lcd_reset = <(1 + 0x60)>; lcd_bl_gpio = <(11 + 0x20) 1>; lcd_power = <(8 + 0x20) 1>;}; -}; -# 17 "nvt-evb.dts" 2 -# 1 "nvt-media.dtsi" 1 -# 10 "nvt-media.dtsi" -# 1 "nvt-basic.dtsi" 1 -# 11 "nvt-basic.dtsi" -/ { - model = "Novatek NA51089"; - compatible = "novatek,na51089", "nvt,ca9"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0x0>; - next-level-cache = <&L2>; - clock-frequency = <960000000>; - }; - }; - - cg@f0020000 { - compatible = "nvt,core_clk"; - reg = <0xf0020000 0x1000>; - }; - - - periph_clk: periph_clk { - compatible = "nvt,periph_clk"; - #clock-cells = <0>; - clock-output-names = "periph_clk"; - }; - - global_timer@ffd00200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0xffd00200 0x20>; - interrupts = <1 11 0xf01>; - clocks = <&periph_clk>; - }; - - private_timer@ffd00600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffd00600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&periph_clk>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 112 4>; - interrupt-affinity = <&cpu0>; - }; - - L2: cache-controller@ffe00000 { - compatible = "arm,pl310-cache"; - reg = <0xffe00000 0x1000>; - interrupts = <0 96 4>; - cache-unified; - arm,shared-override; - cache-level = <2>; - arm,data-latency = <2 2 2>; - arm,tag-latency = <2 2 2>; - }; - - gic: interrupt-controller@0xffd00000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffd01000 0x1000>, - <0xffd00100 0x1000>; - }; - - scu: snoop-control-unit@0xffd00000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xffd00000 0x100>; - }; -}; -# 11 "nvt-media.dtsi" 2 - -/ { - nvtmpp { - compatible = "nvt,nvtmpp"; - }; - - isf_stream { - compatible = "nvt,isf_stream"; - }; - - isf_flow { - compatible = "nvt,isf_flow"; - }; - - isf_vdocap { - compatible = "nvt,isf_vdocap"; - }; - - isf_vdoprc { - compatible = "nvt,isf_vdoprc"; - }; - - isf_dummy { - compatible = "nvt,isf_dummy"; - }; - - isf_vdoenc { - compatible = "nvt,isf_vdoenc"; - }; - - isf_vdodec { - compatible = "nvt,isf_vdodec"; - }; - - isf_vdoout { - compatible = "nvt,isf_vdoout"; - }; - - dispobj { - compatible = "nvt,nvt_dispobj"; - }; - - dispdev { - compatible = "nvt,nvt_dispdev"; - }; - - audio { - compatible = "nvt,nvt_audio"; - }; - - msdcnvt { - compatible = "nvt,msdcnvt"; - }; - - msdcnvt_adj { - compatible = "nvt,msdcnvt_adj"; - }; - - msdcnvt_custom_si { - compatible = "nvt,msdcnvt_custom_si"; - }; - - wavstudio { - compatible = "nvt,wavstudio"; - }; - - isf_audenc { - compatible = "nvt,isf_audenc"; - }; - - isf_auddec { - compatible = "nvt,isf_auddec"; - }; - - isf_audcap { - compatible = "nvt,isf_audcap"; - }; - - isf_audout { - compatible = "nvt,isf_audout"; - }; - - nvt_ipc { - compatible = "nvt,nvt_ipc"; - }; -}; -# 18 "nvt-evb.dts" 2 -# 1 "nvt-mem-tbl.dtsi" 1 - - - - - - -/ { - - nvt_memory_cfg { - #address-cells = <1>; - #size-cells = <1>; - dram { reg = <0x00000000 0x08000000>; }; - shmem{ reg = <0x00007E00 0x00000200>; }; - loader { reg = <0x01000000 0x00080000>; }; - fdt { reg = <0x01800000 0x00040000>; }; - rtos { reg = <0x01840000 0x00FC0000>; }; - linuxtmp{ reg = <0x02800000 0x04000000>; }; - uboot{ reg = <0x06800000 0x01640000>; }; - logo-fb{ reg = <0x07E40000 0x001C0000>; }; - }; - - - memory { device_type = "memory"; reg = <0x00000000 0x01800000 0x02000000 0x01600000>; }; - - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - - - - - - libc-heap { size = <0x00200000>; }; - - hdal-memory { - #address-cells = <1>; - #size-cells = <1>; - media { reg = <0x03600000 0x04A00000>; }; - }; - - hdal-maxpath-cfg { - - vdocap_active_list = <1 0 0 0 0 0 0 0>; - vdoprc_maxdevice = <2>; - vdoenc_maxpath = <4>; - vdodec_maxpath = <3>; - vdoout_maxdevice = <1>; - adocap_maxdevice = <1>; - adoout_maxdevice = <2>; - adoenc_maxpath = <1>; - adodec_maxpath = <1>; - - gfx_maxjob = <2>; - - stamp_maximg = <9>; - - vdoprc_maxstamp = <4 4>; - - vdoprc_maxmask = <4 4>; - vdoenc_maxstamp = <9 9>; - vdoenc_maxmask = <0 64>; - vdoout_maxstamp = <0 16>; - vdoout_maxmask = <0 64>; - }; -}; -# 19 "nvt-evb.dts" 2 -# 1 "nvt-storage-partition.dtsi" 1 - - - - - - - -&nor { - partition_loader { label = "loader"; reg = <0x0 0x0000000 0x0 0x10000>; }; - partition_fdt { label = "fdt"; reg = <0x0 0x10000 0x0 0x10000>; }; - partition_fdt.restore { label = "fdt.restore"; reg = <0x0 0x20000 0x0 0x10000>; }; - partition_fdt.app { label = "fdt.app"; reg = <0x0 0x30000 0x0 0x20000>; }; - partition_uboot { label = "uboot"; reg = <0x0 0x50000 0x0 0xA0000>; }; - partition_uenv { label = "uenv"; reg = <0x0 0xF0000 0x0 0x10000>; }; - partition_kernel { label = "kernel"; reg = <0x0 0x100000 0x0 0x290000>; }; - partition_rootfs { label = "rootfs"; reg = <0x0 0x390000 0x0 0x3E0000>; }; - partition_rootfs1 { label = "rootfs1"; reg = <0x0 0x770000 0x0 0xB00000>; }; - partition_rtos { label = "rtos"; reg = <0x0 0x1270000 0x0 0x900000>; }; - partition_app { label = "app"; reg = <0x0 0x1B70000 0x0 0x50000>; }; - partition_sys { label = "sys"; reg = <0x0 0x1CC0000 0x0 0x10000>; }; - partition_all { label = "all"; reg = <0x0 0x0000000 0x0 0x2000000>; }; -}; -# 20 "nvt-evb.dts" 2 -# 1 "nvt-info.dtsi" 1 - - - - - - - -/ { - nvt_info { - BIN_NAME = "FW98565A"; - BIN_NAME_T = "FW98565T"; - RTOS_APP_MAIN = "cardv"; - - EMBMEM_BLK_SIZE = "0x10000"; -# 24 "nvt-info.dtsi" - EMBMEM = "EMBMEM_SPI_NOR"; -# 34 "nvt-info.dtsi" - FW_TYPE = "FW_TYPE_PARTIAL"; - - - - - - UI_STYLE = "UI_STYLE_LVGL"; - - - - - - NVT_CFG_APP_EXTERNAL = "hostapd wireless_tool iperf-3 wpa_supplicant dhd_priv"; - - NVT_CFG_APP = "mem cardv memcpy isp_demon sf_app"; - - NVT_ROOTFS_ETC = ""; - - NVT_BINARY_FILE_STRIP = "yes"; - - NVT_CFG_KERNEL_CFG = "na51089_evb_cardv_defconfig_release"; - - NVT_MAKE_POST = "make_post.sh"; - - NVT_SAMPLES_INSTALL = "DISABLE"; - - NVT_CFG_UBOOT_CFG = ""; - - - - - - - - NVT_LINUX_SMP = "NVT_LINUX_SMP_OFF"; - - - - - - - - NVT_CHIP_ID = "CHIP_NA51089"; - - - - - - - - NVT_LINUX_COMPRESS = "NVT_LINUX_COMPRESS_GZ"; - - - - - - - - NVT_DEFAULT_NETWORK_BOOT_PROTOCOL = "NVT_DEFAULT_NETWORK_BOOT_PROTOCOL_STATIC_IP"; -# 103 "nvt-info.dtsi" - NVT_ROOTFS_TYPE = "NVT_ROOTFS_TYPE_RAMDISK"; -# 113 "nvt-info.dtsi" - LCD1 = "disp_if8b_lcd1_psd200_st7789v"; -# 126 "nvt-info.dtsi" - SENSOR1 = "sen_os05b10"; - SENSOR1_CFG = "sen_os05b10_565"; - SENSOR2 = "sen_off"; - SENSOR2_CFG = "sen_off"; - - - - - - NVT_ROOTFS_RW_PART_EN = "NVT_ROOTFS_RW_PART_EN_ON"; - - - - - - - NVT_ETHERNET = "NVT_ETHERNET_NONE"; -# 151 "nvt-info.dtsi" - NVT_SDIO_WIFI = "NVT_SDIO_WIFI_RTK"; - - - - - - NVT_USB_WIFI = "NVT_USB_WIFI_NONE"; - - - - - - NVT_USB_4G = "NVT_USB_4G_NONE"; - - - - - - - WIFI_RTK_MDL = "WIFI_RTK_MDL_8189"; - - - - - - - - WIFI_BRCM_MDL = "WIFI_BRCM_MDL_43456c5_ampk6256c5"; - - - - - - - WIFI_NVT_MDL = "WIFI_NVT_MDL_18211"; - - - - - - - NVT_CURL_SSL = "NVT_CURL_SSL_OPENSSL"; -# 201 "nvt-info.dtsi" - NVT_UBOOT_ENV_IN_STORG_SUPPORT = "NVT_UBOOT_ENV_IN_STORG_SUPPORT_OFF"; - - - - - - - TOUCH = "TOUCH_OFF"; - - - - - - - UBOOT_ONLY_LOAD_LINUX = "UBOOT_ONLY_LOAD_LINUX_ON"; - - }; -}; -# 21 "nvt-evb.dts" 2 -# 1 "nvt-nvtpack.dtsi" 1 - - - - - - - -&nor { - - - - - nvtpack { - ver = "NVTPACK_FW_INI_16072017"; - method = <1>; - index { - id0 { partition_name = "loader"; source_file = ""; }; - id1 { partition_name = "fdt"; source_file = "nvt-evb.bin"; }; - id2 { partition_name = "fdt.restore"; source_file = ""; }; - id3 { partition_name = "fdt.app"; source_file = "../application.bin"; }; - id4 { partition_name = "uboot"; source_file = "u-boot.bin"; }; - id5 { partition_name = "uenv"; source_file = ""; }; - id6 { partition_name = "kernel"; source_file = "uImage.bin"; }; - id7 { partition_name = "rootfs"; source_file = "rootfs.ramdisk.bin"; }; - id8 { partition_name = "rootfs1"; source_file = "rootfs_1.squash.bin"; }; - id9 { partition_name = "rtos"; source_file = "../rtos-main.bin"; }; - id10 { partition_name = "app"; source_file = "appfs.cardv.jffs2.nor.bin"; }; - id11 { partition_name = "sys"; source_file = ""; }; - }; - }; -}; -# 21 "nvt-evb.dts" 2 diff --git a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-i2c.dtsi b/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-i2c.dtsi index d8309d842..19e6d5586 100644 --- a/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-i2c.dtsi +++ b/configs/Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530/nvt-i2c.dtsi @@ -6,7 +6,7 @@ */ / { - i2c0: i2c@f0220000 { compatible = "nvt,nvt_i2c"; reg = <0xf0220000 0x100>; interrupts = ; clock-frequency = <400000>; id = <0>; /*gsr = <2>;*/ /* tsr = <1>; */}; - i2c1: i2c2@f0350000 { compatible = "nvt,nvt_i2c"; reg = <0xf0350000 0x100>; interrupts = ; clock-frequency = <400000>; id = <1>; /*gsr = <2>;*/ /* tsr = <1>; */}; + i2c0: i2c@f0220000 { compatible = "nvt,nvt_i2c"; reg = <0xf0220000 0x100>; interrupts = ; clock-frequency = <1000000>; id = <0>; /*gsr = <2>;*/ /* tsr = <1>; */}; + i2c1: i2c2@f0350000 { compatible = "nvt,nvt_i2c"; reg = <0xf0350000 0x100>; interrupts = ; clock-frequency = <1000000>; id = <1>; /*gsr = <2>;*/ /* tsr = <1>; */}; i2c2: i2c3@f03a0000 { compatible = "nvt,nvt_i2c"; reg = <0xf03a0000 0x100>; interrupts = ; clock-frequency = <50000>; id = <2>; /*gsr = <2>;*/ /* tsr = <1>; */}; }; diff --git a/configs/cfg_gen b/configs/cfg_gen deleted file mode 120000 index b62750d24..000000000 --- a/configs/cfg_gen +++ /dev/null @@ -1 +0,0 @@ -Linux/cfg_565_HUNTING_EVB_LINUX_4G_S530 \ No newline at end of file diff --git a/loader/.cproject b/loader/.cproject new file mode 100755 index 000000000..41c8dde17 --- /dev/null +++ b/loader/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/loader/.project b/loader/.project new file mode 100755 index 000000000..3ae0e7671 --- /dev/null +++ b/loader/.project @@ -0,0 +1,27 @@ + + + na51089_loader_cardv + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/loader/ARC/Lib/Release/CA9.a b/loader/ARC/Lib/Release/CA9.a new file mode 100644 index 000000000..5391b35a1 Binary files /dev/null and b/loader/ARC/Lib/Release/CA9.a differ diff --git a/loader/ARC/Lib/Release/Common_exFAT.a b/loader/ARC/Lib/Release/Common_exFAT.a new file mode 100644 index 000000000..dc2cd6d58 Binary files /dev/null and b/loader/ARC/Lib/Release/Common_exFAT.a differ diff --git a/loader/ARC/Lib/Release/Common_normal.a b/loader/ARC/Lib/Release/Common_normal.a new file mode 100644 index 000000000..91b5e91df Binary files /dev/null and b/loader/ARC/Lib/Release/Common_normal.a differ diff --git a/loader/ARC/Lib/Release/Compress.a b/loader/ARC/Lib/Release/Compress.a new file mode 100644 index 000000000..2ea7d7219 Binary files /dev/null and b/loader/ARC/Lib/Release/Compress.a differ diff --git a/loader/ARC/Lib/Release/Debug.a b/loader/ARC/Lib/Release/Debug.a new file mode 100644 index 000000000..f49a8d5e7 Binary files /dev/null and b/loader/ARC/Lib/Release/Debug.a differ diff --git a/loader/ARC/Lib/Release/Driver.a b/loader/ARC/Lib/Release/Driver.a new file mode 100644 index 000000000..5431d3c45 Binary files /dev/null and b/loader/ARC/Lib/Release/Driver.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ560.a b/loader/ARC/Lib/Release/Remap_LZ560.a new file mode 100644 index 000000000..bc0017fee Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ560.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ561.a b/loader/ARC/Lib/Release/Remap_LZ561.a new file mode 100755 index 000000000..532d46a18 Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ561.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ562.a b/loader/ARC/Lib/Release/Remap_LZ562.a new file mode 100644 index 000000000..d1482de49 Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ562.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ563.a b/loader/ARC/Lib/Release/Remap_LZ563.a new file mode 100644 index 000000000..01bc4f781 Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ563.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ565.a b/loader/ARC/Lib/Release/Remap_LZ565.a new file mode 100644 index 000000000..78be5e366 Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ565.a differ diff --git a/loader/ARC/Lib/Release/Remap_LZ566.a b/loader/ARC/Lib/Release/Remap_LZ566.a new file mode 100644 index 000000000..078338f22 Binary files /dev/null and b/loader/ARC/Lib/Release/Remap_LZ566.a differ diff --git a/loader/ARC/Lib/Release/Reset_560.a b/loader/ARC/Lib/Release/Reset_560.a new file mode 100644 index 000000000..0b1862f63 Binary files /dev/null and b/loader/ARC/Lib/Release/Reset_560.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_Eth.a b/loader/ARC/Lib/Release/STRGEXT_Eth.a new file mode 100644 index 000000000..de15a1f10 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_Eth.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_NONE.a b/loader/ARC/Lib/Release/STRGEXT_NONE.a new file mode 100644 index 000000000..d642babfa Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_NONE.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_Sdio1.a b/loader/ARC/Lib/Release/STRGEXT_Sdio1.a new file mode 100644 index 000000000..25e7d189d Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_Sdio1.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_Sdio2.a b/loader/ARC/Lib/Release/STRGEXT_Sdio2.a new file mode 100644 index 000000000..c4e3b4dcb Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_Sdio2.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_Uart.a b/loader/ARC/Lib/Release/STRGEXT_Uart.a new file mode 100644 index 000000000..37e867207 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_Uart.a differ diff --git a/loader/ARC/Lib/Release/STRGEXT_Usb.a b/loader/ARC/Lib/Release/STRGEXT_Usb.a new file mode 100644 index 000000000..37e867207 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGEXT_Usb.a differ diff --git a/loader/ARC/Lib/Release/STRGINT_EMMC.a b/loader/ARC/Lib/Release/STRGINT_EMMC.a new file mode 100644 index 000000000..5c9a05c07 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGINT_EMMC.a differ diff --git a/loader/ARC/Lib/Release/STRGINT_NandSpi.a b/loader/ARC/Lib/Release/STRGINT_NandSpi.a new file mode 100644 index 000000000..15960f885 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGINT_NandSpi.a differ diff --git a/loader/ARC/Lib/Release/STRGINT_SpiFlash.a b/loader/ARC/Lib/Release/STRGINT_SpiFlash.a new file mode 100644 index 000000000..f12747811 Binary files /dev/null and b/loader/ARC/Lib/Release/STRGINT_SpiFlash.a differ diff --git a/loader/ARC/Lib/Release/fdt.a b/loader/ARC/Lib/Release/fdt.a new file mode 100644 index 000000000..336148933 Binary files /dev/null and b/loader/ARC/Lib/Release/fdt.a differ diff --git a/loader/ARC/Lib/Release/nvtpack.a b/loader/ARC/Lib/Release/nvtpack.a new file mode 100644 index 000000000..dcf2170ec Binary files /dev/null and b/loader/ARC/Lib/Release/nvtpack.a differ diff --git a/loader/Document/autodoc/BuildDoc.bat b/loader/Document/autodoc/BuildDoc.bat new file mode 100755 index 000000000..cf0c5da61 --- /dev/null +++ b/loader/Document/autodoc/BuildDoc.bat @@ -0,0 +1,39 @@ +@echo off + +if not exist General.cfg ( +echo. +echo ----------------------------------------------------------------- +echo Missing General.cfg +echo ----------------------------------------------------------------- +echo. +goto quit +) + +call RemoveBuildDoc.bat + +echo. +echo ----------------------------------------------------------------- +echo Start to build document +echo ----------------------------------------------------------------- +echo. + +md Library +md CHM + +if exist DriverDoc.cfg ( +doxygen DriverDoc.cfg +) + +echo. +echo ----------------------------------------------------------------- +echo Done. +echo ----------------------------------------------------------------- +goto quit + +echo. +echo ----------------------------------------------------------------- +echo Done. +echo Go to Cygwin to run MakePDF.sh to create PDF version. +echo ----------------------------------------------------------------- + +:quit \ No newline at end of file diff --git a/loader/Document/autodoc/DoxygenLayout.xml b/loader/Document/autodoc/DoxygenLayout.xml new file mode 100755 index 000000000..d2c4de74a --- /dev/null +++ b/loader/Document/autodoc/DoxygenLayout.xml @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/loader/Document/autodoc/DriverDoc.cfg b/loader/Document/autodoc/DriverDoc.cfg new file mode 100755 index 000000000..f2d232fc0 --- /dev/null +++ b/loader/Document/autodoc/DriverDoc.cfg @@ -0,0 +1,31 @@ +# Doxyfile 1.7.4 + +@INCLUDE = General.cfg + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +PROJECT_NAME = "NT96650 SDK Loader Library" +PROJECT_NUMBER = +OUTPUT_DIRECTORY = ./Library/Loader +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +WARN_LOGFILE = Log_DriverDoc.txt +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +INCLUDE_PATH = ../../Include \ + ../../LIB/LIB_Src +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT = ../../Include/Driver650 \ + ../../Include \ + ../../LIB/LIB_Src +EXCLUDE = +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +# related to OUTPUT_DIRECTORY/html +CHM_FILE = "../../../CHM/NT96650 SDK Loader Library.chm" diff --git a/loader/Document/autodoc/General.cfg b/loader/Document/autodoc/General.cfg new file mode 100755 index 000000000..1d20696b1 --- /dev/null +++ b/loader/Document/autodoc/General.cfg @@ -0,0 +1,330 @@ +# Doxyfile 1.7.4 + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- +DOXYFILE_ENCODING = UTF-8 +CREATE_SUBDIRS = YES +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the +ALWAYS_DETAILED_SEC = YES +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = NO +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 4 +ALIASES = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VHDL = NO +EXTENSION_MAPPING = +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = NO +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +INLINE_GROUPED_CLASSES = NO +TYPEDEF_HIDES_STRUCT = NO +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- +EXTRACT_ALL = NO +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = NO +EXTRACT_LOCAL_CLASSES = NO +EXTRACT_LOCAL_METHODS = NO +EXTRACT_ANON_NSPACES = NO +HIDE_UNDOC_MEMBERS = YES +HIDE_UNDOC_CLASSES = YES +HIDE_FRIEND_COMPOUNDS = YES +HIDE_IN_BODY_DOCS = YES +INTERNAL_DOCS = NO +CASE_SENSE_NAMES = NO +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = NO +FORCE_LOCAL_INCLUDES = NO +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_MEMBERS_CTORS_1ST = NO +SORT_GROUP_NAMES = NO +SORT_BY_SCOPE_NAME = NO +STRICT_PROTO_MATCHING = NO +GENERATE_TODOLIST = NO +GENERATE_TESTLIST = NO +GENERATE_BUGLIST = NO +GENERATE_DEPRECATEDLIST= NO +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = NO +SHOW_DIRECTORIES = NO +SHOW_FILES = YES +SHOW_NAMESPACES = NO +FILE_VERSION_FILTER = +LAYOUT_FILE = DoxygenLayout.xml + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- +QUIET = NO +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = YES +WARN_FORMAT = "$file:$line: $text" + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- +INPUT_ENCODING = UTF-8 +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.d \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.idl \ + *.odl \ + *.cs \ + *.php \ + *.php3 \ + *.inc \ + *.m \ + *.mm \ + *.dox \ + *.py \ + *.f90 \ + *.f \ + *.for \ + *.vhd \ + *.vhdl +RECURSIVE = YES +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXCLUDE_SYMBOLS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = * +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +FILTER_SOURCE_PATTERNS = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- +SOURCE_BROWSER = NO +INLINE_SOURCES = NO +STRIP_CODE_COMMENTS = YES +REFERENCED_BY_RELATION = NO +REFERENCES_RELATION = NO +REFERENCES_LINK_SOURCE = YES +USE_HTAGS = NO +VERBATIM_HEADERS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- +ALPHABETICAL_INDEX = YES +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_EXTRA_FILES = +HTML_COLORSTYLE_HUE = 220 +HTML_COLORSTYLE_SAT = 100 +HTML_COLORSTYLE_GAMMA = 80 +HTML_TIMESTAMP = YES +HTML_ALIGN_MEMBERS = YES +HTML_DYNAMIC_SECTIONS = YES +GENERATE_DOCSET = NO +DOCSET_FEEDNAME = "Doxygen generated docs" +DOCSET_BUNDLE_ID = org.doxygen.Project +DOCSET_PUBLISHER_ID = org.doxygen.Publisher +DOCSET_PUBLISHER_NAME = Publisher +GENERATE_HTMLHELP = YES +#--------------------------------------------------------------------------- +# Set HHC_LOCATION to empty to disable chm file generation +#--------------------------------------------------------------------------- +#HHC_LOCATION = +HHC_LOCATION = "C:/Program Files/HTML Help Workshop/hhc.exe" +GENERATE_CHI = NO +CHM_INDEX_ENCODING = +BINARY_TOC = NO +TOC_EXPAND = YES +GENERATE_QHP = NO +QCH_FILE = +QHP_NAMESPACE = org.doxygen.Project +QHP_VIRTUAL_FOLDER = doc +QHP_CUST_FILTER_NAME = +QHP_CUST_FILTER_ATTRS = +QHP_SECT_FILTER_ATTRS = +QHG_LOCATION = +GENERATE_ECLIPSEHELP = NO +ECLIPSE_DOC_ID = org.doxygen.Project +DISABLE_INDEX = NO +ENUM_VALUES_PER_LINE = 0 +GENERATE_TREEVIEW = YES +USE_INLINE_TREES = NO +TREEVIEW_WIDTH = 250 +EXT_LINKS_IN_WINDOW = NO +FORMULA_FONTSIZE = 10 +FORMULA_TRANSPARENT = YES +USE_MATHJAX = NO +MATHJAX_RELPATH = http://www.mathjax.org/mathjax +SEARCHENGINE = YES +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4 +EXTRA_PACKAGES = +LATEX_HEADER = +LATEX_FOOTER = +PDF_HYPERLINKS = YES +USE_PDFLATEX = YES +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- +GENERATE_XML = NO +XML_OUTPUT = xml +XML_SCHEMA = +XML_DTD = +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = NO +EXPAND_ONLY_PREDEF = NO +SEARCH_INCLUDES = YES +INCLUDE_FILE_PATTERNS = +PREDEFINED = +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- +CLASS_DIAGRAMS = YES +MSCGEN_PATH = +HIDE_UNDOC_RELATIONS = YES +HAVE_DOT = NO +DOT_NUM_THREADS = 0 +DOT_FONTNAME = Helvetica +DOT_FONTSIZE = 10 +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = NO +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = NO +CALLER_GRAPH = NO +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +DOT_PATH = +DOTFILE_DIRS = +MSCFILE_DIRS = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = NO +GENERATE_LEGEND = YES +DOT_CLEANUP = YES diff --git a/loader/Document/autodoc/RemoveBuildDoc.bat b/loader/Document/autodoc/RemoveBuildDoc.bat new file mode 100755 index 000000000..0f5399d5b --- /dev/null +++ b/loader/Document/autodoc/RemoveBuildDoc.bat @@ -0,0 +1,11 @@ +@echo off + +echo. +echo ----------------------------------------------------------------- +echo Remove build directory +echo ----------------------------------------------------------------- +echo. + +del Log_*.txt /f/q +rd /s/q Library +rd /s/q CHM \ No newline at end of file diff --git a/loader/Document/loader_build_option.txt b/loader/Document/loader_build_option.txt new file mode 100755 index 000000000..b090f49e3 --- /dev/null +++ b/loader/Document/loader_build_option.txt @@ -0,0 +1,73 @@ +.Loader package with +├── admin +│   ├─────────────────────────────In house auto build +├── ARC +│   └─────────────────────────────Library +├── Document +│   └─────────────────────────────Document +├── Include +├── LibExt +│   ├── LIBExt_src +│   │   └── Ctrl_Flow +│   │   ├── bl_func.c ────────Main flow +│   │   ├── bl_func.h +│   │   ├── main.c +│   │   ├── main.h +│   │   └── Makefile +│   └── Makefile +├── MakeCommon +│   ├── dump_tmp +│   ├── InputSource.txt +│   ├── make_combo_loader.sh────+─Build combination Loader(52x+528)<------------------------------------------------+ +│   ├── MakeCommon.txt │ | +│   ├── Makefile │ | +│   ├── MakeOption.txt │ | +│   ├── OutputImg.txt │ | +│   └── OutputLib.txt │ | +├── output<─────────────────────└───>Combination loader will copy here | +│ | +├── Project | +│   └── Model | +│   ├── Debug_R.bat | +│   ├── IceMode_R.bat | +│   ├── IceMode.ttl | +│   ├── init.gdb | +│   ├── init_IceMode.gdb | +│   ├── LDS_LZ_528.lds | +│   ├── LDS_LZ.lds | +│   ├── LDS_NM.lds | +│   ├── LoadCode.ttl | +│   ├── MakeConfig.txt | +│   ├── Makefile | +│ │ | +│   ├── ModelConfig_EMU_EVB_528.txt──────────────────────────────────(2)[CHIP=528's configuration] | +│   ├── ModelConfig_EMU_EVB.txt ─────────────────────────────────────(1)[CHIP=52x's configuration] | +│ │ | +│   ├── ModelConfig.txt───────────Choose which model want to build(1) or (2) <<<<< | +│ │ ├─────────────────> MODEL = EMU_EVB ─────────(1) | +│ │ └─────────────────> MODEL = EMU_EVB_528 ─────(2) | +│ │ └─>After choose -> entry MakeCommon folder | +│ │ └─>type -> make release or ---use shell script to generate combo loader-----+ +│   ├── Run_R.bat +│   └── Src +│   ├── prj_main.c +│   └── prj_main.h +├── sdk-maker.sh +├── Tools +│   ├── Bin +│   └── ConfigRam────────────────────Dram parameter + +Example +1. Compiler stand-alone loader 52x -----------------------------------------------------> Configuration [1] + [1]. ModelConfig.txt ----> MODEL = EMU_EVB + [2]. Modify configuration of CHIP 52x @ ModelConfig_EMU_EVB.txt──────────────────────────────────────(1) + [3]. Entry MakeCommon folder and type >>> make release + +2. Compiler stand-alone loader 528 -----------------------------------------------------> Configuration [2] + [1]. ModelConfig.txt ----> MODEL = EMU_EVB_528 + [2]. Modify configuration of CHIP 528 @ ModelConfig_EMU_EVB_528.txt──────────────────────────────────(2) + [3]. Entry MakeCommon folder and type >>> make release + +3. Compiler combination loader 52x + 528 + [1]. Configured chip 52x & 528 respectively.(Configuration [1] & Configuration [2] for example + [2]. Entry MakeCommon folder and type > ./make_combo_loader.sh -> choose 3(make combo loader) diff --git a/loader/History.txt b/loader/History.txt new file mode 100755 index 000000000..241cf5df5 --- /dev/null +++ b/loader/History.txt @@ -0,0 +1,14 @@ +I. History +(+) -> New +(*) -> Modified +(@) -> TODO(wait to find out) +[2021/06/02] + (+) Add exFAT ON/OFF option configure at ModelConfig_EMU.txt(default OFF) + +[2018/03/30] + (+) Add L2 cache operation + +[2018/03/23] + (+) Add 1st loader for NT98520, + (-) rename of makefile to _Makefile for temporarily disable(eMMC/usb/ethernet) + diff --git a/loader/Include/CMacro.h b/loader/Include/CMacro.h new file mode 100755 index 000000000..956cd8ec9 --- /dev/null +++ b/loader/Include/CMacro.h @@ -0,0 +1,35 @@ +/*++ + +Copyright (c) 2005 Novatek Microelectronics Corporation + +Module Name: + StdCMac.h + +Abstract: + Standard C Macros for shared header file of ARM ASM and C + You should include this file first and then include the shared header file + For more information, please refer to http://www.arm.com/support/faqdev/1208.html + +Environment: + For nt96610 + +Notes: + Copyright (c) 2005 Novatek Microelectronics Corporation. All Rights Reserved. + +Revision History: + ??/??/??: Created by ARM + 03/17/05: Modify by Chris Hsu for NT96610 uITRON project +--*/ + +#ifndef __C_MACRO_H +#define __C_MACRO_H + + +/* Comment */ +#define COMMENT + +/* end */ +#define END + +#endif // __C_MACRO_H + diff --git a/loader/Include/Driver/CC.h b/loader/Include/Driver/CC.h new file mode 100755 index 000000000..ca7133187 --- /dev/null +++ b/loader/Include/Driver/CC.h @@ -0,0 +1,41 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#ifndef _CC_H +#define _CC_H + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#define CC_CORE_CA53_CORE1 0 +#define CC_CORE_CA53_CORE2 1 +#define CC_CORE_DSP 2 +#define CC_CORE_DSP2 3 + +typedef enum +{ + DMA_ID_1, ///< DMA Controller + DMA_ID_2, ///< DMA Controller 2 + + DMA_ID_COUNT, //< DMA controller count + + ENUM_DUMMY4WORD(DMA_ID) +} DMA_ID; + +extern void cc_setCore2Base(UINT32 uiBaseAddr); +extern ER cc_startCore(UINT32 uiCoreID); +extern void cc_stopCore(UINT32 uiCoreID); +extern UINT32 dma_get_dram_capacity(DMA_ID id); + + + +#endif diff --git a/loader/Include/Driver/Cache.h b/loader/Include/Driver/Cache.h new file mode 100755 index 000000000..e840ce007 --- /dev/null +++ b/loader/Include/Driver/Cache.h @@ -0,0 +1,511 @@ +/** + CPU module driver. + + This file is the driver of CPU module. + + @file Cache.h + @ingroup mIHALCore + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2005. All rights reserved. +*/ + +#ifndef _CACHE_H +#define _CACHE_H +#include "constant.h" + + +/* + csselrcache level & type selection + + Detailed reference to [trm p4-177 CSSELR] +*/ +typedef enum _CACHE_LV_TYPE_ +{ + LEVEL_1_DCACHE = 0x0, //< Level 1 data cache + LEVEL_1_ICACHE, //< Level 1 instruction cache + LEVEL_2_DCACHE, //< Level 2 data cache +} CACHE_LV_TYPE; + + +/* + Values for Ctype fields in CLIDR +*/ + +typedef enum _CLIDR_CTYPE_ +{ + CLIDR_CTYPE_NO_CACHE = 0x0, + CLIDR_CTYPE_INSTRUCTION_ONLY= 0x1, + CLIDR_CTYPE_DATA_ONLY = 0x2, + CLIDR_CTYPE_INSTRUCTION_DATA= 0x3, + CLIDR_CTYPE_UNIFIED = 0x4, +}CLIDR_CTYPE; + + +//Instruction Synchronization Barrier. +#define _ISB() \ + __asm__ __volatile__("isb\n\t") + +//Data Synchronization Barrier +#define _DSB() \ + __asm__ __volatile__("dsb\n\t") + +//Data Memory Barrier +#define _DMB() \ + __asm__ __volatile__("dmb\n\t") + + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_DC_SETS 8 +#define S_DC_W 2 +#define S_DC_LS 5 + +#define _DC_SETS (1 << S_DC_SETS) /* 256 sets */ +#define _DC_W (1 << S_DC_W) /* 4 way */ +#define _DC_LS (1 << S_DC_LS) /* 32 byte line size */ + +#define S_IC_SETS 8 +#define S_IC_W 2 +#define S_IC_LS 5 + +#define _IC_SETS (1 << S_IC_SETS) /* 256 sets */ +#define _IC_W (1 << S_IC_W) /* 4 way */ +#define _IC_LS (1 << S_IC_LS) /* 32 byte line size */ + +#define S_DC_W_L2 4 /* L2 way shift*/ + +#define S_SC_SETS 9 +#define S_SC_W 3 +#define S_SC_LS 5 + +#define _SC_SETS (1 << S_SC_SETS) /* 512 sets */ +#define _SC_W (1 << S_SC_W) /* 8 way */ +#define _SC_LS (1 << S_SC_LS) /* 32 byte line size */ + + +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + + +/* + * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +#define SCTLR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + +#define LEVEL_1 (1 - 1) +#define LEVEL_2 (2 - 1) + +#define CCSIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__( \ + "mrc p15, 1, %0, c0, c0, 0\n\t" \ + : "=r" (val)); \ + val; \ + }) + + +#define sel_CSSELR(InD) \ + __asm__ __volatile__( \ + "mcr p15, 2, %0, c0, c0, 0\n\t" \ + : \ + : "r"(InD)); + +#define _ICACHE_INV_ALL() _ICIALLU() \ + _BPIALL() + +/* + ICIALLU, Instruction Cache Invalidate All to PoU + The ICIALLU characteristics are: + + Invalidate all instruction caches to PoU. If branch predictors are + architecturally visible, also flush branch predictors. + + This register is part of the Cache maintenance instructions functional group. + + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _ICIALLU() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); + +/* + Branch Predictor Invalidate All + The BPIALL characteristics are: + + Invalidate all entries from branch predictors. + This register is part of the Cache maintenance instructions functional group. + Usage constraints + If EL3 is implemented and is using AArch32, this operation can be performed at the following + exception levels: +*/ +#define _BPIALL() \ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); + + +/* + ICIMVAU : Instruction Cache line Invalidate by VA to PoU +*/ +#define _ICACHE_INV_MVAU(addr) _ICIMVAU(addr) +#define _ICIMVAU(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c5, 1\n\t" \ + : \ + : "r"(addr)); + +#define _DCACHE_INV_MVAC(addr) _DCIMVAC(addr) +#define _DCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c6, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCMVAC Clean data cache line by VA to PoC +#define _DCACHE_WBACK_MVAC(addr) _DCCMVAC(addr) +#define _DCCMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c10, 1\n\t" \ + : \ + : "r"(addr)); + +//_DCCIMVAC Clean and invalidate data cache line by VA to PoC +#define _DCACHE_WBACK_INV_MVAC(addr) _DCCIMVAC(addr) +#define _DCCIMVAC(addr) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7, c14, 1\n\t" \ + : \ + : "r"(addr)); + +//DCCISW Clean and invalidate data cache line by set/way +#define _DCCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c14, 2\n\t" \ + : \ + : "r"(way_set)); + +//DCISW Invalidate data cache line by set/way +/* + The DCISW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCISW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c6, 2\n\t" \ + : \ + : "r"(way_set)); + + +//DCCSW Clean data cache line by set/way +/* + The DCCSW input value bit assignments are: + + |31......................4 | 3...1 | 0 | + Setway level rsv + bit[3..1] = 0x0 = Level 1 + bit[3..1] = 0x1 = Level 2 + ... +*/ +#define _DCCSW(way_set) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c7 ,c10, 2\n\t" \ + : \ + : "r"(way_set)) + + + + +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* Get CPU ID */ +#define read_MPIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c0, c0, 5\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +/* ead current CP15 Cache Level ID Register */ +#define read_CLIDR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 1, %0, c0, c0, 1\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) + +#define change_property() \ + ({ \ + __asm__ __volatile__( \ + ".arch_extension sec\n\t" \ + "smc #123\n\t" \ + : \ + : \ + ); \ + }) + +#define CLEAR_MMU() \ + __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0\n\t"); + + +#define DISABLE_MMU() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_DCACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x4\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define DISABLE_ICACHE() \ + ({ \ + unsigned long val = 0; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0\n\t" \ + "bic %0, %0, #0x1000\n\t" \ + "mcr p15, 0, %0, c1, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) + +#define SETUP_TTBR0(val) \ + ({ \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c2, c0, 0\n\t" \ + : \ + : "r" (val) \ + ); \ + }) +/* Cache dirty register () */ +#define read_CDSR() \ + ({ \ + unsigned long val; \ + __asm__ __volatile__(\ + "mrc p15, 0, %0, c7, c10, 6\n\t" \ + : "=r"(val) \ + );\ + val;\ + }) +/** + @addtogroup mIHALCore +*/ +//@{ + +/** + @name CPU clean invalidate all DCache + + Clean and invalidate all data cache + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheAll() cpu_cleanInvalidateDCacheAll() ///< clean invalidate all DCache +//@} + +/** + @name CPU clean invalidate DCache + + Clean and invalidate data cache + Cache line associated with input address will be clean and invalidated + + @param[in] addr data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCache(addr) cpu_cleanInvalidateDCache(addr) ///< clean invalidate DCache +//@} + +/** + @name CPU clean invalidate DCache block + + Clean and invalidate data cache block + Cache line associated with input region will be clean and invalidated + + @param[in] m starting data address to be clean and invalidated + @param[in] n end data address to be clean and invalidated + + @return void +*/ +//@{ +#define CPUCleanInvalidateDCacheBlock(m,n) cpu_cleanInvalidateDCacheBlock(m, n) ///< clean invalidate DCache block +//@} + +/** + @name CPU invalidate DCache + + Invalidate data cache + Cache line associated with input address will be invalidated + + @param[in] addr data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCache(m) cpu_invalidateDCache(m) ///< invalidate DCache +//@} + +/** + @name CPU invalidate DCache block + + Invalidate data cache block + Cache line associated with input region will be invalidated + + @param[in] m starting data address to be invalidated + @param[in] n end data address to be invalidated + + @return void +*/ +//@{ +#define CPUInvalidateDCacheBlock(m,n) cpu_invalidateDCacheBlock(m,n) ///< invalidate DCache block +//@} + +/** + @name CPU clean DCache + + Clean data cache + Cache line associated with input address will be clean + + @param[in] addr data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCache(m) cpu_cleanDCache(m) ///< clean DCache +//@} + +/** + @name CPU clean DCache block + + Clean data cache block + Cache line associated with input region will be clean + + @param[in] m starting data address to be clean + @param[in] n end data address to be clean + + @return void +*/ +//@{ +#define CPUCleanDCacheBlock(m, n) cpu_cleanDCacheBlock(m, n) ///< clean DCache block +//@} + +/** + @name CPU invalidate all DCache + + Invalidate all data cache + + @return void +*/ +//@{ +#define CPUInvalidateDCacheAll() cpu_invalidateDCacheAll() ///< invalidate all DCache +//@} + + +extern BOOL CPUChkDCacheEnabled(UINT32 addr); +extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"))); +//extern void CPUInvalidateICacheAll(void) __attribute__ ((section (".part1"), far)); +//extern void CPUInvalidateICache(UINT32 addr); +extern void CPUInvalidateICacheBlock(UINT32 start, UINT32 end); + +#if 0 +extern void CPUInvalidateDCacheAll(void); +extern void CPUInvalidateDCache(UINT32 addr); +extern void CPUInvalidateDCacheBlock(UINT32 start, UINT32 end); +#endif +extern void cpu_invalidateDCacheBlock(UINT32 start, UINT32 end); +extern void cpu_invalidateDCache(UINT32 addr); +extern void cpu_invalidateDCacheAll(void)__attribute__ ((section (".part1"))); +extern void cpu_cleanDCache(UINT32 addr); +extern void cpu_cleanDCacheBlock(UINT32 start, UINT32 end); +extern void _cache_clean_d_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_invalidate_data_cache_all(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); +extern void _cache_clean_invalidate_d_cache_All(UINT32 level_type, BOOL DSB)__attribute__ ((section (".part1"))); + + + +extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"))); +//extern void cpu_cleanInvalidateDCacheAll(void)__attribute__ ((section (".part1"), far)); +extern void cpu_cleanInvalidateDCache(UINT32 addr); +extern void cpu_cleanInvalidateDCacheBlock(UINT32 start, UINT32 end); + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + + + +#endif + +//@} diff --git a/loader/Include/Driver/Clock.h b/loader/Include/Driver/Clock.h new file mode 100755 index 000000000..92be645d8 --- /dev/null +++ b/loader/Include/Driver/Clock.h @@ -0,0 +1,26 @@ +/** + System Clock APIs header file + + System Clock APIs header. + + @file clock.h + @ingroup mIHALSysCG + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __CLOCK_H +#define __CLOCK_H + +#include "IOReg.h" + +/** \addtogroup mIHALSysCG */ +//@{ + + + + +//@} + +#endif // __CLOCK_H diff --git a/loader/Include/Driver/GPIO.h b/loader/Include/Driver/GPIO.h new file mode 100755 index 000000000..6f6e4d36f --- /dev/null +++ b/loader/Include/Driver/GPIO.h @@ -0,0 +1,316 @@ +/** + General Purpose I/O controller header file + + General Purpose I/O controller header file + + @file GPIO.h + @ingroup mIIOGPIO + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _GPIO_H +#define _GPIO_H + +#include "IOReg.h" + +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +/** + @addtogroup mIDrvIO_GPIO +*/ +//@{ + +/** + GPIO direction + + GPIO direction definition for gpio_setDir() and gpio_getDir() +*/ +typedef enum { + GPIO_DIR_INPUT = 0, ///< GPIO is input direction + GPIO_DIR_OUTPUT = 1, ///< GPIO is output direction + + ENUM_DUMMY4WORD(GPIO_DIR) +} GPIO_DIR; + +/** + GPIO interrupt type + + GPIO interrupt type definition for type argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTTYPE_EDGE = 0, ///< GPIO interrupt is edge trigger + GPIO_INTTYPE_LEVEL = 1, ///< GPIO interrupt is level trigger + + ENUM_DUMMY4WORD(GPIO_INTTYPE) +} GPIO_INTTYPE; + +/** + GPIO interrupt polarity + + GPIO interrupt polarity definition for pol argument of gpio_setIntTypePol() +*/ +typedef enum { + GPIO_INTPOL_POSHIGH = 0, ///< GPIO interrupt polarity is \n + ///< - @b positvie edge for edge trigger + ///< - @b high level for level trigger + GPIO_INTPOL_NEGLOW = 1, ///< GPIO interrupt polarity is \n + ///< - @b negative edge for edge trigger + ///< - @b low level for level trigger + GPIO_INTPOL_BOTHEDGE = 2, ///< GPIO interrupt polarity is \n + ///< - @b both edge for edge trigger + ENUM_DUMMY4WORD(GPIO_INTPOL) +} GPIO_INTPOL; + + + +/** + @name GPIO pins ID + + GPIO pins ID definition + + For detail GPIO pin out, please refer to NT96520 data sheet. +*/ +//@{ +/*Storage GPIO - CGPIO*/ +#define C_GPIO_0 0 ///< C_GPIO[0] +#define C_GPIO_1 1 ///< C_GPIO[1] +#define C_GPIO_2 2 ///< C_GPIO[2] +#define C_GPIO_3 3 ///< C_GPIO[3] +#define C_GPIO_4 4 ///< C_GPIO[4] +#define C_GPIO_5 5 ///< C_GPIO[5] +#define C_GPIO_6 6 ///< C_GPIO[6] +#define C_GPIO_7 7 ///< C_GPIO[7] +#define C_GPIO_8 8 ///< C_GPIO[8] +#define C_GPIO_9 9 ///< C_GPIO[9] +#define C_GPIO_10 10 ///< C_GPIO[10] +#define C_GPIO_11 11 ///< C_GPIO[11] +#define C_GPIO_12 12 ///< C_GPIO[12] +#define C_GPIO_13 13 ///< C_GPIO[13] +#define C_GPIO_14 14 ///< C_GPIO[14] +#define C_GPIO_15 15 ///< C_GPIO[15] +#define C_GPIO_16 16 ///< C_GPIO[16] +#define C_GPIO_17 17 ///< C_GPIO[17] +#define C_GPIO_18 18 ///< C_GPIO[18] +#define C_GPIO_19 19 ///< C_GPIO[19] +#define C_GPIO_20 20 ///< C_GPIO[20] +#define C_GPIO_21 21 ///< C_GPIO[21] +#define C_GPIO_22 22 ///< C_GPIO[22] + +/*Peripheral GPIO - PGPIO*/ +#define P_GPIO_SHIFT_BASE 32 +#define P_GPIO_0 (0 +P_GPIO_SHIFT_BASE) ///< P_GPIO[0] +#define P_GPIO_1 (1 +P_GPIO_SHIFT_BASE) ///< P_GPIO[1] +#define P_GPIO_2 (2 +P_GPIO_SHIFT_BASE) ///< P_GPIO[2] +#define P_GPIO_3 (3 +P_GPIO_SHIFT_BASE) ///< P_GPIO[3] +#define P_GPIO_4 (4 +P_GPIO_SHIFT_BASE) ///< P_GPIO[4] +#define P_GPIO_5 (5 +P_GPIO_SHIFT_BASE) ///< P_GPIO[5] +#define P_GPIO_6 (6 +P_GPIO_SHIFT_BASE) ///< P_GPIO[6] +#define P_GPIO_7 (7 +P_GPIO_SHIFT_BASE) ///< P_GPIO[7] +#define P_GPIO_8 (8 +P_GPIO_SHIFT_BASE) ///< P_GPIO[8] +#define P_GPIO_9 (9 +P_GPIO_SHIFT_BASE) ///< P_GPIO[9] +#define P_GPIO_10 (10+P_GPIO_SHIFT_BASE) ///< P_GPIO[10] +#define P_GPIO_11 (11+P_GPIO_SHIFT_BASE) ///< P_GPIO[11] +#define P_GPIO_12 (12+P_GPIO_SHIFT_BASE) ///< P_GPIO[12] +#define P_GPIO_13 (13+P_GPIO_SHIFT_BASE) ///< P_GPIO[13] +#define P_GPIO_14 (14+P_GPIO_SHIFT_BASE) ///< P_GPIO[14] +#define P_GPIO_15 (15+P_GPIO_SHIFT_BASE) ///< P_GPIO[15] +#define P_GPIO_16 (16+P_GPIO_SHIFT_BASE) ///< P_GPIO[16] +#define P_GPIO_17 (17+P_GPIO_SHIFT_BASE) ///< P_GPIO[17] +#define P_GPIO_18 (18+P_GPIO_SHIFT_BASE) ///< P_GPIO[18] +#define P_GPIO_19 (19+P_GPIO_SHIFT_BASE) ///< P_GPIO[19] +#define P_GPIO_20 (20+P_GPIO_SHIFT_BASE) ///< P_GPIO[20] +#define P_GPIO_21 (21+P_GPIO_SHIFT_BASE) ///< P_GPIO[21] +#define P_GPIO_22 (22+P_GPIO_SHIFT_BASE) ///< P_GPIO[22] +#define P_GPIO_23 (23+P_GPIO_SHIFT_BASE) ///< P_GPIO[23] +#define P_GPIO_24 (24+P_GPIO_SHIFT_BASE) ///< P_GPIO[24] +#define P_GPIO_25 (25+P_GPIO_SHIFT_BASE) ///< P_GPIO[25] + +/*Sensor GPIO - SGPIO*/ +#define S_GPIO_SHIFT_BASE 64 +#define S_GPIO_0 (0 +S_GPIO_SHIFT_BASE) ///< S_GPIO[0] +#define S_GPIO_1 (1 +S_GPIO_SHIFT_BASE) ///< S_GPIO[1] +#define S_GPIO_2 (2 +S_GPIO_SHIFT_BASE) ///< S_GPIO[2] +#define S_GPIO_3 (3 +S_GPIO_SHIFT_BASE) ///< S_GPIO[3] +#define S_GPIO_4 (4 +S_GPIO_SHIFT_BASE) ///< S_GPIO[4] +#define S_GPIO_5 (5 +S_GPIO_SHIFT_BASE) ///< S_GPIO[5] +#define S_GPIO_6 (6 +S_GPIO_SHIFT_BASE) ///< S_GPIO[6] +#define S_GPIO_7 (7 +S_GPIO_SHIFT_BASE) ///< S_GPIO[7] +#define S_GPIO_8 (8 +S_GPIO_SHIFT_BASE) ///< S_GPIO[8] +#define S_GPIO_9 (9 +S_GPIO_SHIFT_BASE) ///< S_GPIO[9] +#define S_GPIO_10 (10+S_GPIO_SHIFT_BASE) ///< S_GPIO[10] +#define S_GPIO_11 (11+S_GPIO_SHIFT_BASE) ///< S_GPIO[11] +#define S_GPIO_12 (12+S_GPIO_SHIFT_BASE) ///< S_GPIO[11] + + +/*LCD GPIO - LGPIO*/ +#define L_GPIO_SHIFT_BASE 96 +#define L_GPIO_0 (0 +L_GPIO_SHIFT_BASE) ///< L_GPIO[0] +#define L_GPIO_1 (1 +L_GPIO_SHIFT_BASE) ///< L_GPIO[1] +#define L_GPIO_2 (2 +L_GPIO_SHIFT_BASE) ///< L_GPIO[2] +#define L_GPIO_3 (3 +L_GPIO_SHIFT_BASE) ///< L_GPIO[3] +#define L_GPIO_4 (4 +L_GPIO_SHIFT_BASE) ///< L_GPIO[4] +#define L_GPIO_5 (5 +L_GPIO_SHIFT_BASE) ///< L_GPIO[5] +#define L_GPIO_6 (6 +L_GPIO_SHIFT_BASE) ///< L_GPIO[6] +#define L_GPIO_7 (7 +L_GPIO_SHIFT_BASE) ///< L_GPIO[7] +#define L_GPIO_8 (8 +L_GPIO_SHIFT_BASE) ///< L_GPIO[8] +#define L_GPIO_9 (9 +L_GPIO_SHIFT_BASE) ///< L_GPIO[9] +#define L_GPIO_10 (10+L_GPIO_SHIFT_BASE) ///< L_GPIO[10] +#define L_GPIO_11 (11+L_GPIO_SHIFT_BASE) ///< L_GPIO[11] +#define L_GPIO_12 (12+L_GPIO_SHIFT_BASE) ///< L_GPIO[12] +#define L_GPIO_13 (13+L_GPIO_SHIFT_BASE) ///< L_GPIO[13] +#define L_GPIO_14 (14+L_GPIO_SHIFT_BASE) ///< L_GPIO[14] +#define L_GPIO_15 (15+L_GPIO_SHIFT_BASE) ///< L_GPIO[15] +#define L_GPIO_16 (16+L_GPIO_SHIFT_BASE) ///< L_GPIO[16] +#define L_GPIO_17 (17+L_GPIO_SHIFT_BASE) ///< L_GPIO[17] +#define L_GPIO_18 (18+L_GPIO_SHIFT_BASE) ///< L_GPIO[18] +#define L_GPIO_19 (19+L_GPIO_SHIFT_BASE) ///< L_GPIO[19] +#define L_GPIO_20 (20+L_GPIO_SHIFT_BASE) ///< L_GPIO[20] +#define L_GPIO_21 (21+L_GPIO_SHIFT_BASE) ///< L_GPIO[21] +#define L_GPIO_22 (22+L_GPIO_SHIFT_BASE) ///< L_GPIO[22] +#define L_GPIO_23 (23+L_GPIO_SHIFT_BASE) ///< L_GPIO[23] +#define L_GPIO_24 (24+L_GPIO_SHIFT_BASE) ///< L_GPIO[24] + +/*Dedicated GPIO - DGPIO*/ +// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " +#define D_GPIO_SHIFT_BASE 128 +#define D_GPIO_0 (0 +D_GPIO_SHIFT_BASE) ///< DGPIO[0] +#define D_GPIO_1 (1 +D_GPIO_SHIFT_BASE) ///< DGPIO[1] +#define D_GPIO_2 (2 +D_GPIO_SHIFT_BASE) ///< DGPIO[2] +#define D_GPIO_3 (3 +D_GPIO_SHIFT_BASE) ///< DGPIO[3] +#define D_GPIO_4 (4 +D_GPIO_SHIFT_BASE) ///< DGPIO[4] +#define D_GPIO_5 (5 +D_GPIO_SHIFT_BASE) ///< DGPIO[5] +#define D_GPIO_6 (6 +D_GPIO_SHIFT_BASE) ///< DGPIO[6] +#define D_GPIO_7 (7 +D_GPIO_SHIFT_BASE) ///< DGPIO[7] +#define D_GPIO_8 (8 +D_GPIO_SHIFT_BASE) ///< DGPIO[8] +#define D_GPIO_9 (9 +D_GPIO_SHIFT_BASE) ///< DGPIO[9] +#define D_GPIO_10 (10+D_GPIO_SHIFT_BASE) ///< DGPIO[10] + +#define D_GPIO_16 (16 +D_GPIO_SHIFT_BASE) ///< D_GPIO[16] (USB Wakeup) (No pad instance) + +/*GPIO HSI Data register(High speed interface)*/ +#define H_GPIO_SHIFT_BASE 160 +#define H_GPIO_0 (0 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[0] +#define H_GPIO_1 (1 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[1] +#define H_GPIO_2 (2 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[2] +#define H_GPIO_3 (3 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[3] +#define H_GPIO_4 (4 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[4] +#define H_GPIO_5 (5 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[5] +#define H_GPIO_6 (6 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[6] +#define H_GPIO_7 (7 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[7] +#define H_GPIO_8 (8 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[8] +#define H_GPIO_9 (9 +H_GPIO_SHIFT_BASE) ///< HSI_GPIO[9] +#define H_GPIO_10 (10+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[10] +#define H_GPIO_11 (11+H_GPIO_SHIFT_BASE) ///< HSI_GPIO[11] + +/*GPIO ADC Data register*/ +#define A_GPI_SHIFT_BASE 192 +#define A_GPIO_0 (0 + A_GPI_SHIFT_BASE) ///< A_GPIO[0] +#define A_GPIO_1 (1 + A_GPI_SHIFT_BASE) ///< A_GPIO[1] +#define A_GPIO_2 (2 + A_GPI_SHIFT_BASE) ///< A_GPIO[2] + +#define DSI_GPIO_2 0xE2 + +//@} + +/*For temporary usage as passing build codes*/ +#define C_GPIO_23 23 +#define C_GPIO_24 24 +#define C_GPIO_25 25 +#define C_GPIO_26 26 +#define C_GPIO_27 27 +#define C_GPIO_28 28 +#define C_GPIO_29 29 +#define C_GPIO_30 30 +#define C_GPIO_31 31 +#define C_GPIO_32 32 +#define C_GPIO_33 33 +#define L_GPIO_30 (30+L_GPIO_SHIFT_BASE) +#define L_GPIO_31 (31+L_GPIO_SHIFT_BASE) +#define L_GPIO_32 (32+L_GPIO_SHIFT_BASE) +#define GPIO_INT_USBPLUGIN (GPIO_INT_39) + + + + +/** + @name GPIO Interrupt ID + + GPIO interrupt ID definition + + GPIO interrupt ID for interrupt related APIs. +*/ +//@{ +#define GPIO_INT_00 0 ///< GPIO INT[0]: C_GPIO[3] +#define GPIO_INT_01 1 ///< GPIO INT[1]: C_GPIO[5] +#define GPIO_INT_02 2 ///< GPIO INT[2]: C_GPIO[7] +#define GPIO_INT_03 3 ///< GPIO INT[3]: C_GPIO[9] +#define GPIO_INT_04 4 ///< GPIO INT[4]: C_GPIO[12] +#define GPIO_INT_05 5 ///< GPIO INT[5]: C_GPIO[14] +#define GPIO_INT_06 6 ///< GPIO INT[6]: C_GPIO[16] +#define GPIO_INT_07 7 ///< GPIO INT[7]: C_GPIO[18] +#define GPIO_INT_08 8 ///< GPIO INT[8]: C_GPIO[20] +#define GPIO_INT_09 9 ///< GPIO INT[9]: C_GPIO[22] +#define GPIO_INT_10 10 ///< GPIO INT[10]: H_GPIO[0] +#define GPIO_INT_11 11 ///< GPIO INT[11]: H_GPIO[11] +#define GPIO_INT_12 12 ///< GPIO INT[12]: S_GPIO[1] +#define GPIO_INT_13 13 ///< GPIO INT[13]: S_GPIO[4] +#define GPIO_INT_14 14 ///< GPIO INT[14]: S_GPIO[6] +#define GPIO_INT_15 15 ///< GPIO INT[15]: S_GPIO[10] +#define GPIO_INT_16 16 ///< GPIO INT[16]: S_GPIO[12] +#define GPIO_INT_17 17 ///< GPIO INT[17]: P_GPIO[3] +#define GPIO_INT_18 18 ///< GPIO INT[18]: P_GPIO[7] +#define GPIO_INT_19 19 ///< GPIO INT[19]: P_GPIO[8] +#define GPIO_INT_20 20 ///< GPIO INT[20]: P_GPIO[9] +#define GPIO_INT_21 21 ///< GPIO INT[21]: P_GPIO[11] +#define GPIO_INT_22 22 ///< GPIO INT[22]: P_GPIO[15] +#define GPIO_INT_23 23 ///< GPIO INT[23]: P_GPIO[17] +#define GPIO_INT_24 24 ///< GPIO INT[24]: P_GPIO[18] +#define GPIO_INT_25 25 ///< GPIO INT[25]: P_GPIO[24] +#define GPIO_INT_26 26 ///< GPIO INT[26]: L_GPIO[1] +#define GPIO_INT_27 27 ///< GPIO INT[27]: L_GPIO[6] +#define GPIO_INT_28 28 ///< GPIO INT[28]: L_GPIO[11] +#define GPIO_INT_29 29 ///< GPIO INT[29]: L_GPIO[14] +#define GPIO_INT_30 30 ///< GPIO INT[30]: P_GPIO[18] +#define GPIO_INT_31 31 ///< GPIO INT[31]: L_GPIO[22] +#define GPIO_INT_32 32 ///< DGPIO INT[0]: D_GPIO[0] +#define GPIO_INT_33 33 ///< DGPIO INT[1]: D_GPIO[1] +#define GPIO_INT_34 34 ///< DGPIO INT[2]: D_GPIO[2] +#define GPIO_INT_35 35 ///< DGPIO INT[3]: D_GPIO[3] +#define GPIO_INT_36 36 ///< DGPIO INT[4]: D_GPIO[4] +#define GPIO_INT_37 37 ///< DGPIO INT[5]: D_GPIO[5] +#define GPIO_INT_38 38 ///< DGPIO INT[6]: D_GPIO[6] +#define GPIO_INT_39 39 ///< DGPIO INT[7]: D_GPIO[7] + +#define GPIO_INT_48 48 ///< DGPIO INT[16]: USB wakeup + +#define GPIO_INT_USBWAKEUP (GPIO_INT_48) ///< DGPIO INT[16]: USB wakeup +//@} + +// In order to backward comaptible, DGPIO is used as " GPIO_IS_DGPIO | D_GPIO_* " or "D_GPIO_*" +#define GPIO_IS_DGPIO (128) + + +// +// The general api for the GPIO device driver +// +extern void gpio_setDir(UINT32 pin, UINT32 dir); +extern UINT32 gpio_getDir(UINT32 pin); +extern void gpio_setPin(UINT32 pin); +extern void gpio_clearPin(UINT32 pin); +extern UINT32 gpio_getPin(UINT32 pin); +extern void gpio_pullSet(UINT32 pin); +extern void gpio_pullClear(UINT32 pin); +extern UINT32 gpio_readData(UINT32 dataidx); +extern void gpio_writeData(UINT32 dataidx, UINT32 value); +//extern UINT32 gpio_readDir(UINT32 dataidx); +//extern void gpio_writeDir(UINT32 dataidx, UINT32 value); +extern UINT32 dgpio_readData(void); +extern void dgpio_writeData(UINT32 value); +extern UINT32 top_get_bs(void); +//extern UINT32 dgpio_readDir(void); +//extern void dgpio_writeDir(UINT32 value); +//@} +#endif + diff --git a/loader/Include/Driver/Memory.h b/loader/Include/Driver/Memory.h new file mode 100755 index 000000000..633a93586 --- /dev/null +++ b/loader/Include/Driver/Memory.h @@ -0,0 +1,437 @@ +# ifndef _MEMORY_520_H +# define _MEMORY_520_H + +#ifndef __ASSEMBLY__ + COMMENT /* Memory Map */ /* # define BOOT_ROM_RAM_BASE_ADDR 0x20000000*/ +#endif +# define DRAM_BASE_ADDR (0x00000000) +# define DRAM_EXP_BASE_ADDR (DRAM_BASE_ADDR + 0x180) +# define DRAM_INT_BASE_ADDR (DRAM_BASE_ADDR + 0x200) + +# define StackSize_KNL 0x1000 /* 4KB */ +# define StackSize_INT 0x400 /* 1KB */ + +# define FAT_HEAP_BUFFER_SIZE 0xA0000//0x1E0000 //0x1E8000 +# define EXFAT_BITMAP_BUFFER_SIZE 0x20000 //0x18000 +# define LOADER_TMP_BUFFER_SIZE 0x80000 + +# define BOOT_ROM_SP_LIMIT_ADDR 0xF07F8FFC +# define BOOT_ROM_RAM_TEMP_ADDR 0xF0800200 +# define BOOT_ROM_CFG_TEMP_ADDR 0xF0800248 +# define BOOT_ROM_RAM_BASE_ADDR 0x00000000 +# define DMA2_CTRL_REG_BASE_ADDR 0xF0100000 +# define DMA2_PHY_REG_BASE_ADDR 0xF0101000 +# define USB_OTG_REG_BASE_ADDR 0//0xF0600000 +# define DDR_CTRL_REG_BASE_ADDR 0xF0000000 /* DDR phy base address */ +# define DDR_PHY_REG_BASE_ADDR 0xF0001000 +# define DDR_ARB_REG_BASE_ADDR 0xF0008000 +# define DMA2_ARB_REG_BASE_ADDR 0xF0108000 + +# define CLOCK_GEN_REG_BASE_ADDR 0xF0020000 +# define PMU_REG_BASE_ADDR 0xF0024000 +# define TOP_CTRL_REG_BASE_ADDR 0xF0010000 +# define PAD_CTRL_REG_BASE_ADDR 0xF0030000 +# define GPIO_CTRL_REG_BASE_ADDR 0xF0070000 +# define PMC_REG_BASE 0xF00A0000 + +# define TRNG_REG_BASE_ADDR 0xF0680000 + +# define CPU_REG_BASE_ADDR 0xF0FF0000 + +# define UART0_REG_BASE_ADDR 0xF0290000 +// Real board is UART3 +# define UART2_REG_BASE_ADDR 0xF0310000 +# define SM_HOST_REG_BASE_ADDR 0xF0400000 +# define MS_HOST_REG_BASE_ADDR 0xF0410000 +# define SD_HOST1_REG_BASE_ADDR 0xF0420000 +# define SD_HOST2_REG_BASE_ADDR 0xF0500000 +# define SD_HOST3_REG_BASE_ADDR 0xF0510000 +# define SPI_CTRL_REG_BASE_ADDR 0xF0230000 +# define ETH_CTRL_REG_BASE_ADDR 0xF02B0000 +# define EFUSE_CTRL_REG_BASE_ADDR 0xF0660000 +# define IDE_SRAM_BASE_ADDR 0xF07C0000 +# define IDE_CTRL_REG_BASE_ADDR 0xF0800000 +# define TIMER_REG_BASE_ADDR 0xF0040000 +# define WDT_REG_BASE_ADDR 0xF0050000 + +# define BOOT_LOADER_TMP_BUFFER 0x00001000 +# define CHIP_REMAP_REG_OFFSET 0x00000088 +# define CPE_RTC_BASE 0xF0060000 /* RTC controller */ +# define CPE_GPIO_BASE 0xF0070000 /* GPIO controller */ +# define INTERRUPT_BASE_ADDR 0xF0080000 /* Interrupt controller */ +# define CC_BASE_ADDR 0xF0090000 /* CC controller */ +# define IOADDR_GIC_REG_BASE 0xFFD00000 /* GIC Interrupt */ +# define configARM_TIMER_BASEADDR 0xFFD00200 +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ + + +# define BOOT_ROM_RAM_TEMP_ADDR2 0xF07E8000 //Eth +# define PAD_REG_BASE 0xF0030000 +# define L2_MEM_BASE 0xFFE00000 +# define IOADDR_HVYLOAD_REG_BASE 0xF0008000 + +# define CC_CPU2_CPU1_CMDBUF_REG1 0xF07F8000 //CC_CPU2_CPU1_CMDBUF_REG1 to store uboot starting address +# define CC_CPU2_CPU1_CMDBUF_REG2 0xF07F8004 //CC_CPU2_CPU1_CMDBUF_REG1 has used in core2_entry.s +# define NVT_CORE2_START CC_CPU2_CPU1_CMDBUF_REG2 //core2_entry.S 's entry point + +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +# define ARM_TIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ +# define ARM_TIMER_ISR_OFFSET 0x0C /**< Timer Interrupt Status Register */ +# define ARM_TIMER_COUNTER_OFFSET_L 0x00 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_OFFSET_H 0x04 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_L 0x10 /**< Timer Counter Register */ +# define ARM_TIMER_COUNTER_CMP_OFFSET_H 0x14 /**< Timer Counter Register */ +# define CYGHWR_HAL_RTC_PRESCALER 1 +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +# define ARM_TIMER_CONTROL_PRESCALER_SHIFT 8 +# define ARM_TIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ +# define ARM_TIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +# define ARM_TIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ + +#define ARM_TIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ +#define CRYPTO_REG_BASE_ADDR 0xF0620000 +#define HASH_REG_BASE_ADDR 0xF0670000 +#define RSA_REG_BASE_ADDR 0xF06A0000 + +#define CRYPTO_CONFIG_REG (CRYPTO_REG_BASE_ADDR + 0x00) +#define CRYPTO_CONTROL_REG (CRYPTO_REG_BASE_ADDR + 0x04) +#define CRYPTO_OUT_DATA_REG (CRYPTO_REG_BASE_ADDR + 0x08) +#define CRYPTO_STATUS_REG (CRYPTO_REG_BASE_ADDR + 0x0C) + +#define CRYPTO_PIO_INPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x30) +#define CRYPTO_PIO_INPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x34) +#define CRYPTO_PIO_INPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x38) +#define CRYPTO_PIO_INPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x3C) +#define CRYPTO_PIO_OUTPUT0_REG (CRYPTO_REG_BASE_ADDR + 0x40) +#define CRYPTO_PIO_OUTPUT1_REG (CRYPTO_REG_BASE_ADDR + 0x44) +#define CRYPTO_PIO_OUTPUT2_REG (CRYPTO_REG_BASE_ADDR + 0x48) +#define CRYPTO_PIO_OUTPUT3_REG (CRYPTO_REG_BASE_ADDR + 0x4C) + +// Hash +#define HASH_CONFIG_REG (HASH_REG_BASE_ADDR + 0x00) +#define HASH_STATUS_REG (HASH_REG_BASE_ADDR + 0x0C) +#define HASH_OUTPUT_DATA1_REG (HASH_REG_BASE_ADDR + 0x70) +#define HASH_INPUT_DATA_REG (HASH_REG_BASE_ADDR + 0x90) + +//RSA +#define RSA_CONFIG_REG (RSA_REG_BASE_ADDR + 0x00) +#define RSA_CONTROL_REG (RSA_REG_BASE_ADDR + 0x04) +#define RSA_STATUS_REG (RSA_REG_BASE_ADDR + 0x0C) +#define RSA_KEY_N_REG (RSA_REG_BASE_ADDR + 0x10) +#define RSA_KEY_N_ADDR_REG (RSA_REG_BASE_ADDR + 0x14) +#define RSA_KEY_ED_REG (RSA_REG_BASE_ADDR + 0x18) +#define RSA_KEY_ED_ADDR_REG (RSA_REG_BASE_ADDR + 0x1C) +#define RSA_DATA_REG (RSA_REG_BASE_ADDR + 0x20) +#define RSA_DATA_ADDR_REG (RSA_REG_BASE_ADDR + 0x24) +#define RSA_CRC32_DEFAULT_REG_OFS (RSA_REG_BASE_ADDR + 0x30) +#define RSA_CRC32_POLY_REG_OFS (RSA_REG_BASE_ADDR + 0x34) +#define RSA_CRC32_OUTPUT_REG_OFS (RSA_REG_BASE_ADDR + 0x38) + +// Crypto +#define CRYPTO_CONFREG_SWRST (1<<0) +#define CRYPTO_CONFREG_CRYPTO_EN (1<<1) +#define CRYPTO_CONFREG_AES128 (2<<4) +#define CRYPTO_CONFREG_DECRYPT (1<<8) + +#define CRYPTO_PIO_DONE (1<<0) + +// Hash +#define HASH_CONFREG_INITSTATE (1<<20) +#define HASH_CONFREG_SHA256 (1<<4) +#define HASH_CONFREG_ENABLE (1<<1) + +//RSA +#define RSA_ENABLE (1<<0) + +#define RSA_KEYWIDTH_256 (0x0<<1) +#define RSA_KEYWIDTH_512 (0x1<<1) +#define RSA_KEYWIDTH_1024 (0x2<<1) +#define RSA_KEYWIDTH_2048 (0x3<<1) +#define RSA_KEYWIDTH_4096 (0x4<<1) + +#define RSA_NORMAL_MODE (0x0<<4) +#define RSA_MODE_CRC_KEY_N (0x1<<4) +#define RSA_MODE_CRC_KEY_ED (0x2<<4) + + +#define RSA_TRANSFER_END (0x1<<0) +#define RSA_BUSY (0x1<<1) + +#define HASH_TRANSFER_END (0x1<<0) + + + +#define TOP_CTRL_SRAM_RESET_REG0 (TOP_CTRL_REG_BASE_ADDR + 0x1000) + +//Shut down SRAM SDIO1 mask +#define TOP_SRAM_SD_SDIO1 0x20000000 +//Shut down SRAM RSA mask +#define TOP_SRAM_SD_RSA 0x02000000 + + +#define reg0_cache_type_ofs 0x004 //reg0_cache_type +#define CACHE_CTRL_REG_OFS 0x100 +#define CACHE_AUX_CTRL_REG_OFS 0x104 + +#define CACHE_TAG_RAM_CTRL_OFS 0x108 +#define CACHE_DATA_RAM_CTRL_OFS 0x10C + + +#define reg2_int_clear_ofs 0x220 //reg2_int_clear +#define reg7_cache_sync 0x730 //reg7_cache_sync +#define reg7_inv_way 0x77C //reg7_inv_way + +#define CACHE_PREFETCH_REG_OFS 0xF60 + +#define L2_REG0_BASE (L2_MEM_BASE + 0x000) /* Cache ID and Cache Type */ +#define L2_REG1_BASE (L2_MEM_BASE + 0x100) /* Control */ +#define L2_REG2_BASE (L2_MEM_BASE + 0X200) /* Interrupt and Counter Control Registers */ +#define L2_REG7_BASE (L2_MEM_BASE + 0x700) /* Cache Maintenance Operations */ +#define L2_REG9_BASE (L2_MEM_BASE + 0x900) /* Cache Lockdown */ +#define L2_REG12_BASE (L2_MEM_BASE + 0xC00) /* Address Filtering */ +#define L2_REG15_BASE (L2_MEM_BASE + 0xF00) /* Debug, Prefetch and Power */ + +/** + * Cache ID and Cache Type + */ +#define L2_REG0_CACHE_ID (*((volatile unsigned long *)(L2_REG0_BASE + 0x00))) +#define L2_REG0_CACHE_TYPE (*((volatile unsigned long *)(L2_REG0_BASE + 0x04))) + +#define S_L2_REG0_CACHE_TYPE_DB (31) +#define M_L2_REG0_CACHE_TYPE_DB (0xf << S_L2_REG0_CACHE_TYPE_DB) +#define S_L2_REG0_CACHE_TYPE_CTYPE (25) +#define M_L2_REG0_CACHE_TYPE_CTYPE (0xf << S_L2_REG0_CACHE_TYPE_CTYPE) +#define S_L2_REG0_CACHE_TYPE_H (24) +#define M_L2_REG0_CACHE_TYPE_H (0x1 << S_L2_REG0_CACHE_TYPE_H) +#define S_L2_REG0_CACHE_TYPE_DWS (20) +#define M_L2_REG0_CACHE_TYPE_DWS (0x7 << S_L2_REG0_CACHE_TYPE_DWS) +#define S_L2_REG0_CACHE_TYPE_DA (18) +#define M_L2_REG0_CACHE_TYPE_DA (0x1 << S_L2_REG0_CACHE_TYPE_DA) +#define S_L2_REG0_CACHE_TYPE_DLS (12) +#define M_L2_REG0_CACHE_TYPE_DLS (0x3 << S_L2_REG0_CACHE_TYPE_DLS) +#define S_L2_REG0_CACHE_TYPE_IWS (8) +#define M_L2_REG0_CACHE_TYPE_IWS (0x7 << S_L2_REG0_CACHE_TYPE_IWS) +#define S_L2_REG0_CACHE_TYPE_IA (6) +#define M_L2_REG0_CACHE_TYPE_IA (0x1 << S_L2_REG0_CACHE_TYPE_IA) +#define S_L2_REG0_CACHE_TYPE_ILS (0) +#define M_L2_REG0_CACHE_TYPE_ILS (0x3 << S_L2_REG0_CACHE_TYPE_ILS) + +#define K_L2_REG0_CACHE_TYPE_DA_16WAY (1) +#define K_L2_REG0_CACHE_TYPE_DA_8WAY (0) + +/** + * Control + */ +#define L2_REG1_CONTROL (*((volatile unsigned long *)(L2_REG1_BASE + 0x00))) +#define L2_REG1_AUX_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x04))) +#define L2_REG1_TAG_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x08))) +#define L2_REG1_DATA_RAM_CTRL (*((volatile unsigned long *)(L2_REG1_BASE + 0x0C))) + +#define S_L2_REG1_CONTROL_EN (0) +#define M_L2_REG1_CONTROL_EN (0x1 << S_L2_REG1_CONTROL_EN) + +#define K_L2_REG1_CONTROL_EN_ON 1 +#define K_L2_REG1_CONTROL_EN_OFF 0 + +#define S_L2_REG1_AUX_CTRL_BRESP (30) +#define M_L2_REG1_AUX_CTRL_BRESP (0x1 << S_L2_REG1_AUX_CTRL_BRESP) +#define S_L2_REG1_AUX_CTRL_INSTR_PREF (29) +#define M_L2_REG1_AUX_CTRL_INSTR_PREF (0x1 << S_L2_REG1_AUX_CTRL_INSTR_PREF) +#define S_L2_REG1_AUX_CTRL_DATA_PERF (28) +#define M_L2_REG1_AUX_CTRL_DATA_PERF (0x1 << S_L2_REG1_AUX_CTRL_DATA_PERF) +#define S_L2_REG1_AUX_CTRL_NS_INT_CTRL (27) +#define M_L2_REG1_AUX_CTRL_NS_INT_CTRL (0x1 << S_L2_REG1_AUX_CTRL_NS_INT_CTRL) +#define S_L2_REG1_AUX_CTRL_NS_LOCK_EN (26) +#define M_L2_REG1_AUX_CTRL_NS_LOCK_EN (0x1 << S_L2_REG1_AUX_CTRL_NS_LOCK_EN) +#define S_L2_REG1_AUX_CTRL_CACHE_POLICY (25) +#define M_L2_REG1_AUX_CTRL_CACHE_POLICY (0x1 << S_L2_REG1_AUX_CTRL_CACHE_POLICY) +#define S_L2_REG1_AUX_CTRL_FORCE_WA (23) +#define M_L2_REG1_AUX_CTRL_FORCE_WA (0x3 << S_L2_REG1_AUX_CTRL_FORCE_WA) +#define S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (22) +#define M_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_OVERRIDE_EN) +#define S_L2_REG1_AUX_CTRL_PARITY_EN (21) +#define M_L2_REG1_AUX_CTRL_PARITY_EN (0x1 << S_L2_REG1_AUX_CTRL_PARITY_EN) +#define S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (20) +#define M_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN (0x1 << S_L2_REG1_AUX_CTRL_EVENT_MON_BUD_EN) +#define S_L2_REG1_AUX_CTRL_WAT_SIZE (17) +#define M_L2_REG1_AUX_CTRL_WAT_SIZE (0x7 << S_L2_REG1_AUX_CTRL_WAT_SIZE) +#define S_L2_REG1_AUX_CTRL_ASSOCIATIVITY (16) +#define M_L2_REG1_AUX_CTRL_ASSOCIATIVITY (0x1 << S_L2_REG1_AUX_CTRL_ASSOCIATIVITY) +#define S_L2_REG1_AUX_CTRL_SHARED_INV_EN (13) +#define M_L2_REG1_AUX_CTRL_SHARED_INV_EN (0x1 << S_L2_REG1_AUX_CTRL_SHARED_INV_EN) +#define S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (12) +#define M_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF (0x1 << S_L2_REG1_AUX_CTRL_EXCLUSIVE_CACHE_CONF) +#define S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (11) +#define M_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN (0x1 << S_L2_REG1_AUX_CTRL_STORE_BUD_DEV_LIMIT_EN) +#define S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (10) +#define M_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN (0x1 << S_L2_REG1_AUX_CTRL_HIGH_PRIO_SO_DEV_READS_EN) +#define S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0) +#define M_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN (0x1 << S_L2_REG1_AUX_CTRL_FULL_LINE_Z_EN) + +/** + * Interrupt and Counter Control Registers + */ +#define L2_REG2_EV_CNT_CTRL (*((volatile unsigned long *)(L2_REG2_BASE + 0x00))) +#define L2_REG2_EV_CNT1_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x04))) +#define L2_REG2_EV_CNT0_CFG (*((volatile unsigned long *)(L2_REG2_BASE + 0x08))) +#define L2_REG2_EV_CNT1 (*((volatile unsigned long *)(L2_REG2_BASE + 0x0C))) +#define L2_REG2_EV_CNT0 (*((volatile unsigned long *)(L2_REG2_BASE + 0x10))) +#define L2_REG2_INT_MASK (*((volatile unsigned long *)(L2_REG2_BASE + 0x14))) +#define L2_REG2_INT_MASK_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x18))) +#define L2_REG2_INT_RAW_STATUS (*((volatile unsigned long *)(L2_REG2_BASE + 0x1C))) +#define L2_REG2_INT_CLEAR (*((volatile unsigned long *)(L2_REG2_BASE + 0x20))) + +#define S_L2_REG2_INT_DECERR (8) +#define M_L2_REG2_INT_DECERR (0x1 << S_L2_REG2_INT_DECERR) /* Decode error */ +#define S_L2_REG2_INT_SLVERR (7) +#define M_L2_REG2_INT_SLVERR (0x1 << S_L2_REG2_INT_SLVERR) /* Slave error */ +#define S_L2_REG2_INT_ERRRD (6) +#define M_L2_REG2_INT_ERRRD (0x1 << S_L2_REG2_INT_ERRRD) /* Data RAM read error */ +#define S_L2_REG2_INT_ERRRT (5) +#define M_L2_REG2_INT_ERRRT (0x1 << S_L2_REG2_INT_ERRRT) /* Tag RAM read error */ +#define S_L2_REG2_INT_ERRWD (4) +#define M_L2_REG2_INT_ERRWD (0x1 << S_L2_REG2_INT_ERRWD) /* Data RAM write error */ +#define S_L2_REG2_INT_ERRWT (3) +#define M_L2_REG2_INT_ERRWT (0x1 << S_L2_REG2_INT_ERRWT) /* Tag RAM write error */ +#define S_L2_REG2_INT_PARRD (2) +#define M_L2_REG2_INT_PARRD (0x1 << S_L2_REG2_INT_PARRD) /* Parity error on data RAM read */ +#define S_L2_REG2_INT_PARRT (1) +#define M_L2_REG2_INT_PARRT (0x1 << S_L2_REG2_INT_PARRT) /* Pariry error on tag RAM read */ +#define S_L2_REG2_INT_ECNTR (0) +#define M_L2_REG2_INT_ECNTR (0x1 << S_L2_REG2_INT_ECNTR) /* Event counter1/0 overflow increment */ + +/** + * Cache Maintenance Operations + */ +#define L2_REG7_CACHE_SYNC (*((volatile unsigned long *)(L2_REG7_BASE + 0x30))) +#define L2_REG7_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0x70))) +#define L2_REG7_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0x7C))) +#define L2_REG7_CLEAN_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xB0))) +#define L2_REG7_CLEAN_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xB8))) +#define L2_REG7_CLEAN_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xBC))) +#define L2_REG7_CLEAN_INV_PA (*((volatile unsigned long *)(L2_REG7_BASE + 0xF0))) +#define L2_REG7_CLEAN_INV_INDEX (*((volatile unsigned long *)(L2_REG7_BASE + 0xF8))) +#define L2_REG7_CLEAN_INV_WAY (*((volatile unsigned long *)(L2_REG7_BASE + 0xFC))) + + +#define K_L2_REG7_CACHE_SYNC_C (0x1) + +#define K_L2_REG7_INV_WAY_8WAY (0x00ff) +#define K_L2_REG7_INV_WAY_16WAY (0xffff) +#define K_L2_REG7_CLEAN_WAY_8WAY (0x00ff) +#define K_L2_REG7_CLEAN_WAY_16WAY (0xffff) + + +/** + * Cache Lockdown + */ +#define L2_REG9_D_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x00))) +#define L2_REG9_I_LOCKDOWN0 (*((volatile unsigned long *)(L2_REG9_BASE + 0x04))) +#define L2_REG9_D_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x08))) +#define L2_REG9_I_LOCKDOWN1 (*((volatile unsigned long *)(L2_REG9_BASE + 0x0C))) +#define L2_REG9_D_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x10))) +#define L2_REG9_I_LOCKDOWN2 (*((volatile unsigned long *)(L2_REG9_BASE + 0x14))) +#define L2_REG9_D_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x18))) +#define L2_REG9_I_LOCKDOWN3 (*((volatile unsigned long *)(L2_REG9_BASE + 0x1C))) +#define L2_REG9_D_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x20))) +#define L2_REG9_I_LOCKDOWN4 (*((volatile unsigned long *)(L2_REG9_BASE + 0x24))) +#define L2_REG9_D_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x28))) +#define L2_REG9_I_LOCKDOWN5 (*((volatile unsigned long *)(L2_REG9_BASE + 0x2C))) +#define L2_REG9_D_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x30))) +#define L2_REG9_I_LOCKDOWN6 (*((volatile unsigned long *)(L2_REG9_BASE + 0x34))) +#define L2_REG9_D_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x38))) +#define L2_REG9_I_LOCKDOWN7 (*((volatile unsigned long *)(L2_REG9_BASE + 0x3C))) +#define L2_REG9_LOCK_LINE_EN (*((volatile unsigned long *)(L2_REG9_BASE + 0x50))) +#define L2_REG9_UNLOCK_WAY (*((volatile unsigned long *)(L2_REG9_BASE + 0x54))) + +/** + * Address Filtering + */ +#define L2_REG12_ADDR_FILTERING_START (*((volatile unsigned long *)(L2_REG12_BASE + 0x00))) +#define L2_REG12_ADDR_FILTERING_END (*((volatile unsigned long *)(L2_REG12_BASE + 0x04))) + +/** + * Debug, Prefetch and Power + */ +#define L2_REG15_DEBUG_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x40))) +#define L2_REG15_PREF_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x60))) +#define L2_REG15_POWER_CTRL (*((volatile unsigned long *)(L2_REG15_BASE + 0x80))) + +#define S_L2_REG15_DEBUG_CTRL_SPNIDEN (2) +#define M_L2_REG15_DEBUG_CTRL_SPNIDEN (0x1 << S_L2_REG15_DEBUG_CTRL_SPNIDEN) +#define S_L2_REG15_DEBUG_CTRL_DWB (1) +#define M_L2_REG15_DEBUG_CTRL_DWB (0x1 << S_L2_REG15_DEBUG_CTRL_DWB) +#define S_L2_REG15_DEBUG_CTRL_DCL (0) +#define M_L2_REG15_DEBUG_CTRL_DCL (0x1 << S_L2_REG15_DEBUG_CTRL_DCL) + +#define S_L2_REG15_PREF_CTRL_DL_FILL_EN (30) +#define M_L2_REG15_PREF_CTRL_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_INST_PREF_EN (29) +#define M_L2_REG15_PREF_CTRL_INST_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_INST_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DATA_PREF_EN (28) +#define M_L2_REG15_PREF_CTRL_DATA_PREF_EN (0x1 << S_L2_REG15_PREF_CTRL_DATA_PREF_EN) +#define S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (27) +#define M_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS (0x1 << S_L2_REG15_PREF_CTRL_DL_WRAP_READ_DIS) +#define S_L2_REG15_PREF_CTRL_PREF_DROP_EN (24) +#define M_L2_REG15_PREF_CTRL_PREF_DROP_EN (0x1 << S_L2_REG15_PREF_CTRL_PREF_DROP_EN) +#define S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (23) +#define M_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN (0x1 << S_L2_REG15_PREF_CTRL_INCR_DL_FILL_EN) +#define S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (21) +#define M_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN (0x1 << S_L2_REG15_PREF_CTRL_NOT_SAME_ID_EXCLU_SEQ_EN) +#define S_L2_REG15_PREF_CTRL_PREF_OFF (0) +#define M_L2_REG15_PREF_CTRL_PREF_OFF (0xf << S_L2_REG15_PREF_CTRL_PREF_OFF) + +// DDR phy duty configuration register bit +#define DDR_PHY_INCREASE_DUTY 0x40 // P < N +#define DDR_PHY_DECREASE_DUTY 0x00 // P > N +#define DDR_PHY_DUTY_TYPE_MSK 0x40 // bit mask for increase/decrease duty +#define DDR_PHY_CLK_ADJ_EN 0x80 + +// DDR phy duty calibration control register bit +#define DDR_PHY_CLK_OP_ONGOING 0x10 +#define DDR_PHY_CLK_OP_DONE 0x00 +#define DDR_PHY_DQS_OP_ONGOING 0x20 +#define DDR_PHY_DQS_OP_DONE 0x00 + + +# define DDR_PHY_CAL_CLK_ADJ_OFS 0x000 /* 0x00 */ +# define DDR_PHY_CAL_CMD_ADJ_OFS 0x01C /* 0x1C */ +# define DDR_PHY_CAL_CTRL_OFS 0x150 /* 0x54 */ +# define DDR_PHY_CAL_CLK_CFG_OFS 0x154 /* 0x55 */ +# define DDR_PHY_CAL_DQS_CFG_OFS 0x158 /* 0x56 */ +# define DDR_PHY_CAL_DTY_CNT_LB_OFS 0x15C /* 0x57 duty cnt low byte */ +# define DDR_PHY_CAL_DTY_CNT_HB_OFS 0x160 /* 0x58 duty cnt high byte */ +# define DDR_PHY_CAL_DQS0_ADJ_OFS 0x1D0 /* 0x1D0 */ +# define DDR_PHY_CAL_DQ_ADJ_OFS 0x1D4 /* 0x1D0 */ + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_CARD 0x01 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_RS_2K 0x03 +#define BOOT_SOURCE_ETHERNET 0x04 +#define BOOT_SOURCE_USB 0x05 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_BMC 0x07 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 +#define BOOT_SOURCE_SPI_NAND_RS_4K 0x0A +#define BOOT_SOURCE_USB_FULL 0x0B + +#define BOOT_SOURCE_MSK 0x0F + + +# define IDENTIFY_ERR 2 +# define MBR_ERR 3 +# define PBR_ERR 4 +# define READ512_ERR 5 +# define READ_ERR 7 +# define HPA_ERR 8 +# define CHECKSUM_ERR 9 +#ifndef __ASSEMBLY__ + END +#endif +# endif diff --git a/loader/Include/Driver/crypto.h b/loader/Include/Driver/crypto.h new file mode 100755 index 000000000..4ac5318aa --- /dev/null +++ b/loader/Include/Driver/crypto.h @@ -0,0 +1,98 @@ +/** + Header file for CC (Core Communicator) module. + + This file is the header file that define the API and data type + for CC module. + + @file CC.h + @ingroup mIDrvSys_CC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "constant.h" + +#ifndef _CRYPTO_H +#define _CRYPTO_H + +#define ROM_AES_SIZE (16) +#define ROM_SHA_SIZE (32) // unit: byte +#define ROM_RSA_SIZE (256) // RSA-2048 +#define ROM_RSA_EKEY_SIZE (32) +#define ROM_RSA_CRC32_SIZE (4) +/** + Crypto engine crypto mode +*/ +typedef enum { + CRYPTO_RSV0, + CRYPTO_RSV1, + CRYPTO_AES, ///< Select Crypto mode AES + CRYPTO_MODE_NUM, +} CRYPTO_MODE; + +/** + Crypto engine crypto Operating mode +*/ +typedef enum { + CRYPTO_EBC = 0x00, ///< Select Crypto opmode EBC + CRYPTO_CBC, ///< Select Crypto opmode CBC + CRYPTO_OPMODE_NUM, +} CRYPTO_OPMODE; + +/** + Crypto engine encrypt or decrypt +*/ +typedef enum { + CRYPTO_ENCRYPT = 0x00, ///< Select Crypto engine encrypt + CRYPTO_DECRYPT, ///< Select Crypto engine decrypt + CRYPTO_TYPE_NUM, + +} CRYPTO_TYPE; + +typedef enum { + EFUSE_OTP_1ST_KEY_SET_FIELD = 0x0, // This if for secure boot + EFUSE_OTP_2ND_KEY_SET_FIELD, + EFUSE_OTP_3RD_KEY_SET_FIELD, + EFUSE_OTP_4TH_KEY_SET_FIELD, + + EFUSE_OTP_TOTAL_KEY_SET_FIELD, +} EFUSE_OTP_KEY_SET_FIELD; + +typedef struct _CRYPT_OP { + CRYPTO_OPMODE op_mode; ///< Operation Mode (now support ECB only) + CRYPTO_TYPE en_de_crypt; ///< Encrypt or decrypt (CRYPTO_ENCRYPT or CRYPTO_DECRYPT) + UINT32 src_addr; ///< Source address + UINT32 dst_addr; ///< Destination address + UINT32 length; ///< length +} CRYPT_OP; + +/** + Crypto engine check +*/ +typedef enum { + SECUREBOOT_SECURE_EN = 0x00, ///< Quary if secure enable or not + SECUREBOOT_DATA_AREA_ENCRYPT, ///< Quary if data area encrypt to cypher text or not + SECUREBOOT_SIGN_RSA, ///< Quary if Signature methed is RSA or not(AES) + SECUREBOOT_SIGN_RSA_CHK, ///< Quary if Signature hash checksum RSA key correct or not + SECUREBOOT_STATUS_NUM, + +} SECUREBOOT_STATUS; + +#define is_secure_enable() quary_secure_boot(SECUREBOOT_SECURE_EN) //For backward compatitable +#define is_data_area_encrypted() quary_secure_boot(SECUREBOOT_DATA_AREA_ENCRYPT) //For backward compatitable +#define is_signature_rsa() quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +#define is_signature_aes() !quary_secure_boot(SECUREBOOT_SIGN_RSA) //For backward compatitable +BOOL quary_secure_boot(SECUREBOOT_STATUS scu_status); +UINT32 crypto_data_operation(EFUSE_OTP_KEY_SET_FIELD key_set, CRYPT_OP crypt_op_param); +void rsa_setConfig(UINT32 mode); +void rsa_setkey_n(UINT8* key, UINT32 len, UINT32 sram_size); +void rsa_setkey_ed(UINT8* key, UINT32 len, UINT32 sram_size); +INT32 rsa_pio_enable(UINT8* data, UINT32 len, UINT32 sram_size); +void rsa_getOutput(UINT8 * Output, UINT32 len, UINT32 sram_size); + +void shahw( const unsigned char *input, int ilen, UINT32 output[8]); +void rsa_decrypt(UINT32 *input ,UINT32 input_len, UINT32 *pRSAN, UINT32 RSAN_len, UINT32 *pRSAED, UINT32 RSAED_len , UINT32 *pShaOut); +BOOL rsa_keycheck(UINT32 *input , BOOL efuseCheck); + +#endif diff --git a/loader/Include/Driver/nand.h b/loader/Include/Driver/nand.h new file mode 100755 index 000000000..57c804d33 --- /dev/null +++ b/loader/Include/Driver/nand.h @@ -0,0 +1,121 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NAND_DEF_ +#define _NAND_DEF_ + +#include "IOReg.h" + +#define _SNAND_WINBOND_ID (0xEF) +#define _SNAND_ESMT_ID (0xC8) +#define _SNAND_GD_ID (0xC8) +#define _SNAND_MICRON_ID (0x2C) +#define _SNAND_ATO_ID (0x9B) +#define _SNAND_ETRON_ID (0xD5) +#define _SNAND_MXIC_ID (0xC2) +#define _SNAND_TOSHIBA_ID (0x98) +#define _SNAND_DOSILICON_ID (0xE5) + + + +#define _GD_SPI_NAND_1Gb (0xF1) +#define _MXIC_SPI_NAND_1Gb (0x12) +#define _DOSILICON_NAND_1Gb (0x71) +/** + SPI NAND flash QE(quid enable) identify type + +*/ + +//@{ +typedef enum { + SPINAND_QE_NONE = 0x0, ///< SPI NAND flash not with QE bit(only by quad command) + SPINAND_QE_FEATURE2_B0H_BIT0_TYPE1, ///< SPI NAND flash QE bit locate at feature field(0xB0H) bit[0] +} SPINAND_QE_TYPE; + + +/** + SPI NAND flash twp plane identify type + +*/ +//@{ +typedef enum { + SPINAND_2_PLANE_NONE = 0x0, ///< SPI NAND flash not 2 plane type + SPINAND_2_PLANE_COLUMN_ADDR_BIT_12_AS_PLANE_SEL,///< SPI NAND flash use column addr bit[12] as plane select +} SPINAND_PLANE_TYPE; + + + +/** + SPI flash identification structure + + @note For SPIFLASH_IDENTIFY_CB +*/ +typedef struct { + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} SPINAND_IDENTIFY, *PSPINAND_IDENTIFY; + +/** + SPIFLASH identify callback + + Callback routine to be invoked after JEDEC ID is read from spi flash. + Callback routine should check if read ID is supported. + + @note STRG_EXT_CMD_SPI_IDENTIFY_CB + + @param[in] first parameter (JEDEC) manufacturer ID read from spi flash + @param[in] second parameter (JEDEC) type ID read from spi flash + @param[in] third parameter (JEDEC) capacity ID read from spi flash + @param[out] forth parameter flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +typedef BOOL (*SPINAND_IDENTIFY_CB)(UINT32, UINT32, PSPINAND_IDENTIFY); + + + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: the device ID (the second byte of the full chip ID array) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @erasesize: NAND block size + * @qe_opt: Quad enable type(please reference document to select this option) + * @plane_opt: 2 plane nand option(please reference document to select this option) + * @options: stores various chip bit options + * + */ +typedef struct _nand_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 pagesize; + UINT32 erasesize; + UINT32 qe_opt; + UINT32 plane_opt; +} NAND_FLASH_DEV, *PNAND_FLASH_DEV; + +#define SPI_ID_NAND(mfrid, devid, pagesz, erasesz, opts, plane_opt_type)\ + { .mfr_id =(mfrid), .dev_id = (devid), .pagesize = (pagesz), \ + .erasesize = (erasesz), .qe_opt = (opts), .plane_opt=(plane_opt_type) } + +extern BOOL nand_identify(UINT32 uiMfgID, UINT32 uiTypeID, PSPINAND_IDENTIFY pIdentify); + +#endif + diff --git a/loader/Include/Driver/nor.h b/loader/Include/Driver/nor.h new file mode 100755 index 000000000..5c1128410 --- /dev/null +++ b/loader/Include/Driver/nor.h @@ -0,0 +1,51 @@ +/** + nand module driver. + + This file is the driver of storage module. + + @file nand.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _NOR_DEF_ +#define _NOR_DEF_ + +#include "IOReg.h" +#include "StorageDef.h" + + +/** + * struct nand_flash_dev - NAND Flash Device ID Structure + * @name: a human-readable name of the NAND chip + * @dev_id: the device ID (the second byte of the full chip ID array) + * @mfr_id: manufecturer ID part of the full chip ID array (refers the same + * memory address as @id[0]) + * @dev_id: device ID part of the full chip ID array (refers the same memory + * address as @id[1]) + * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as + * well as the eraseblock size) is determined from the extended NAND + * chip ID array) + * @chipsize: total chip size in MiB + * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) + * @options: stores various chip bit options + * + */ +typedef struct _nor_flash_dev { + UINT32 mfr_id; + UINT32 dev_id; + UINT32 capacity_id; + UINT32 bDualRead; + UINT32 uiQuadReadType; + UINT32 uiFlashSize; +} NOR_FLASH_DEV, *PNOR_FLASH_DEV; + +#define SPI_ID_NOR(mfrid, devid, capacityid, dual_read, quad_read_type, flash_size)\ + { .mfr_id =(mfrid), .dev_id = (devid), .capacity_id =(capacityid), .bDualRead=(dual_read), \ + .uiQuadReadType=(quad_read_type), .uiFlashSize=(flash_size) } + + +extern BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify); +#endif diff --git a/loader/Include/Driver/pad.h b/loader/Include/Driver/pad.h new file mode 100755 index 000000000..747602960 --- /dev/null +++ b/loader/Include/Driver/pad.h @@ -0,0 +1,874 @@ +/** + PAD controller header + + PAD controller header + + @file pad.h + @ingroup mIHALSysPAD + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _PAD_H +#define _PAD_H + +//#include "Type.h" +#include "constant.h" + + + +/** \addtogroup mIHALSysPAD */ +//@{ + +// Macro to generate dummy element for enum type to expand enum size to word (4 bytes) +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 + +#if 0 +/** + Pad type select + + Pad type select + + Pad type value for pad_setPullUpDown(). +*/ +typedef enum +{ + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_setDrivingSink(). +*/ +typedef enum { + PAD_DRIVINGSINK_2P5MA = 0x01, ///< for backward compatible + PAD_DRIVINGSINK_5MA = 0x02, ///< Pad driver/sink 5mA + PAD_DRIVINGSINK_7P5MA = 0x04, ///< for backward compatible + PAD_DRIVINGSINK_10MA = 0x08, ///< Pad driver/sink 10mA + + PAD_DRIVINGSINK_12P5MA = 0x10, ///< for backward compatible + PAD_DRIVINGSINK_15MA = 0x20, ///< Pad driver/sink 15mA + PAD_DRIVINGSINK_17P5MA = 0x40, ///< for backward compatible + PAD_DRIVINGSINK_20MA = 0x80, ///< Pad driver/sink 20mA + PAD_DRIVINGSINK_25MA = 0x100, ///< Pad driver/sink 25mA + PAD_DRIVINGSINK_30MA = 0x200, ///< Pad driver/sink 30mA + PAD_DRIVINGSINK_35MA = 0x400, ///< Pad driver/sink 35mA + PAD_DRIVINGSINK_40MA = 0x800, ///< Pad driver/sink 40mA + PAD_DRIVINGSINK_4MA = 0x1000, ///< PAD driver/sink 4mA + PAD_DRIVINGSINK_6MA = 0x2000, ///< PAD driver/sink 6mA + PAD_DRIVINGSINK_8MA = 0x4000, ///< PAD driver/sink 8mA + PAD_DRIVINGSINK_16MA = 0x8000, ///< PAD driver/sink 16mA + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_setPullUpDown(). +*/ +#define PAD_PIN_NOT_EXIST (15) // For backward compatible +//@{ +//CGPIOx group begin +#define PAD_PIN_CGPIO_BASE 0 +#define PAD_PIN_CGPIO0 (PAD_PIN_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_PIN_CGPIO1 (PAD_PIN_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_PIN_CGPIO2 (PAD_PIN_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_PIN_CGPIO3 (PAD_PIN_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_PIN_CGPIO4 (PAD_PIN_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_PIN_CGPIO5 (PAD_PIN_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_PIN_CGPIO6 (PAD_PIN_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_PIN_CGPIO7 (PAD_PIN_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_PIN_CGPIO8 (PAD_PIN_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_PIN_CGPIO9 (PAD_PIN_CGPIO_BASE + 9) ///< CGPIO9 +#define PAD_PIN_CGPIO10 (PAD_PIN_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_PIN_CGPIO11 (PAD_PIN_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_PIN_CGPIO12 (PAD_PIN_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_PIN_CGPIO13 (PAD_PIN_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_PIN_CGPIO14 (PAD_PIN_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_PIN_CGPIO15 (PAD_PIN_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_PIN_CGPIO16 (PAD_PIN_CGPIO_BASE + 16) ///< CGPIO16 +#define PAD_PIN_CGPIO17 (PAD_PIN_CGPIO_BASE + 17) ///< CGPIO17 +#define PAD_PIN_CGPIO18 (PAD_PIN_CGPIO_BASE + 18) ///< CGPIO18 +#define PAD_PIN_CGPIO19 (PAD_PIN_CGPIO_BASE + 19) ///< CGPIO19 +#define PAD_PIN_CGPIO20 (PAD_PIN_CGPIO_BASE + 20) ///< CGPIO20 +#define PAD_PIN_CGPIO21 (PAD_PIN_CGPIO_BASE + 21) ///< CGPIO21 +#define PAD_PIN_CGPIO22 (PAD_PIN_CGPIO_BASE + 22) ///< CGPIO22 +#define PAD_PIN_CGPIO23 (PAD_PIN_CGPIO_BASE + 23) ///< CGPIO23 +#define PAD_PIN_CGPIO24 (PAD_PIN_CGPIO_BASE + 24) ///< CGPIO24 +#define PAD_PIN_CGPIO25 (PAD_PIN_CGPIO_BASE + 25) ///< CGPIO25 +#define PAD_PIN_CGPIO26 (PAD_PIN_CGPIO_BASE + 26) ///< CGPIO26 +#define PAD_PIN_CGPIO27 (PAD_PIN_CGPIO_BASE + 27) ///< CGPIO27 +#define PAD_PIN_CGPIO28 (PAD_PIN_CGPIO_BASE + 28) ///< CGPIO28 +#define PAD_PIN_CGPIO29 (PAD_PIN_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_PIN_CGPIO30 (PAD_PIN_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_PIN_CGPIO31 (PAD_PIN_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_PIN_CGPIO32 (PAD_PIN_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_PIN_CGPIO33 (PAD_PIN_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIOx group end + +//SGPIOx group begin +#define PAD_PIN_SGPIO_BASE 100 +#define PAD_PIN_SGPIO0 (PAD_PIN_SGPIO_BASE + 0) ///< SGPIO0 +#define PAD_PIN_SGPIO1 (PAD_PIN_SGPIO_BASE + 1) ///< SGPIO1 +#define PAD_PIN_SGPIO2 (PAD_PIN_SGPIO_BASE + 2) ///< SGPIO2 +#define PAD_PIN_SGPIO3 (PAD_PIN_SGPIO_BASE + 3) ///< SGPIO3 +#define PAD_PIN_SGPIO4 (PAD_PIN_SGPIO_BASE + 4) ///< SGPIO4 +#define PAD_PIN_SGPIO5 (PAD_PIN_SGPIO_BASE + 5) ///< SGPIO5 +#define PAD_PIN_SGPIO6 (PAD_PIN_SGPIO_BASE + 6) ///< SGPIO6 +#define PAD_PIN_SGPIO7 (PAD_PIN_SGPIO_BASE + 7) ///< SGPIO7 +#define PAD_PIN_SGPIO8 (PAD_PIN_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_PIN_SGPIO9 (PAD_PIN_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_PIN_SGPIO10 (PAD_PIN_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_PIN_SGPIO11 (PAD_PIN_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIOx group end + +//PGPIOx group begin +#define PAD_PIN_PGPIO_BASE 150 +#define PAD_PIN_PGPIO0 (PAD_PIN_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_PIN_PGPIO1 (PAD_PIN_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_PIN_PGPIO2 (PAD_PIN_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_PIN_PGPIO3 (PAD_PIN_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_PIN_PGPIO4 (PAD_PIN_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_PIN_PGPIO5 (PAD_PIN_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_PIN_PGPIO6 (PAD_PIN_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_PIN_PGPIO7 (PAD_PIN_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_PIN_PGPIO8 (PAD_PIN_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_PIN_PGPIO9 (PAD_PIN_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_PIN_PGPIO10 (PAD_PIN_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_PIN_PGPIO11 (PAD_PIN_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_PIN_PGPIO12 (PAD_PIN_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_PIN_PGPIO13 (PAD_PIN_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_PIN_PGPIO14 (PAD_PIN_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_PIN_PGPIO15 (PAD_PIN_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_PIN_PGPIO16 (PAD_PIN_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_PIN_PGPIO17 (PAD_PIN_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_PIN_PGPIO18 (PAD_PIN_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_PIN_PGPIO19 (PAD_PIN_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_PIN_PGPIO20 (PAD_PIN_PGPIO_BASE + 20) ///< PGPIO20 +#define PAD_PIN_PGPIO21 (PAD_PIN_PGPIO_BASE + 21) ///< PGPIO21 +#define PAD_PIN_PGPIO22 (PAD_PIN_PGPIO_BASE + 22) ///< PGPIO22 +#define PAD_PIN_PGPIO23 (PAD_PIN_PGPIO_BASE + 23) ///< PGPIO23 +#define PAD_PIN_PGPIO24 (PAD_PIN_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_PIN_PGPIO25 (PAD_PIN_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_PIN_PGPIO26 (PAD_PIN_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_PIN_PGPIO27 (PAD_PIN_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_PIN_PGPIO28 (PAD_PIN_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_PIN_PGPIO29 (PAD_PIN_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_PIN_PGPIO30 (PAD_PIN_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_PIN_PGPIO31 (PAD_PIN_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_PIN_PGPIO32 (PAD_PIN_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_PIN_PGPIO33 (PAD_PIN_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_PIN_PGPIO34 (PAD_PIN_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_PIN_PGPIO35 (PAD_PIN_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_PIN_PGPIO36 (PAD_PIN_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_PIN_PGPIO37 (PAD_PIN_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_PIN_PGPIO38 (PAD_PIN_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_PIN_PGPIO39 (PAD_PIN_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_PIN_PGPIO40 (PAD_PIN_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_PIN_PGPIO41 (PAD_PIN_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_PIN_PGPIO42 (PAD_PIN_PGPIO_BASE + 42) ///< PGPIO42 +#define PAD_PIN_PGPIO43 (PAD_PIN_PGPIO_BASE + 43) ///< PGPIO43 +#define PAD_PIN_PGPIO44 (PAD_PIN_PGPIO_BASE + 44) ///< PGPIO44 +#define PAD_PIN_PGPIO45 (PAD_PIN_PGPIO_BASE + 45) ///< PGPIO45 +#define PAD_PIN_PGPIO46 (PAD_PIN_PGPIO_BASE + 46) ///< PGPIO46 +#define PAD_PIN_PGPIO47 (PAD_PIN_PGPIO_BASE + 47) ///< PGPIO47 +//PGPIOx group end + + +//LGPIOx group begin +#define PAD_PIN_LGPIO_BASE 250 +#define PAD_PIN_LGPIO0 (PAD_PIN_LGPIO_BASE + 0) ///< LGPIO0 +#define PAD_PIN_LGPIO1 (PAD_PIN_LGPIO_BASE + 1) ///< LGPIO1 +#define PAD_PIN_LGPIO2 (PAD_PIN_LGPIO_BASE + 2) ///< LGPIO2 +#define PAD_PIN_LGPIO3 (PAD_PIN_LGPIO_BASE + 3) ///< LGPIO3 +#define PAD_PIN_LGPIO4 (PAD_PIN_LGPIO_BASE + 4) ///< LGPIO4 +#define PAD_PIN_LGPIO5 (PAD_PIN_LGPIO_BASE + 5) ///< LGPIO5 +#define PAD_PIN_LGPIO6 (PAD_PIN_LGPIO_BASE + 6) ///< LGPIO6 +#define PAD_PIN_LGPIO7 (PAD_PIN_LGPIO_BASE + 7) ///< LGPIO7 +#define PAD_PIN_LGPIO8 (PAD_PIN_LGPIO_BASE + 8) ///< LGPIO8 +#define PAD_PIN_LGPIO9 (PAD_PIN_LGPIO_BASE + 9) ///< LGPIO9 +#define PAD_PIN_LGPIO10 (PAD_PIN_LGPIO_BASE + 10) ///< LGPIO10 +#define PAD_PIN_LGPIO11 (PAD_PIN_LGPIO_BASE + 11) ///< LGPIO11 +#define PAD_PIN_LGPIO12 (PAD_PIN_LGPIO_BASE + 12) ///< LGPIO12 +#define PAD_PIN_LGPIO13 (PAD_PIN_LGPIO_BASE + 13) ///< LGPIO13 +#define PAD_PIN_LGPIO14 (PAD_PIN_LGPIO_BASE + 14) ///< LGPIO14 +#define PAD_PIN_LGPIO15 (PAD_PIN_LGPIO_BASE + 15) ///< LGPIO15 + +#define PAD_PIN_LGPIO16 (PAD_PIN_LGPIO_BASE + 16) ///< LGPIO16 +#define PAD_PIN_LGPIO17 (PAD_PIN_LGPIO_BASE + 17) ///< LGPIO17 +#define PAD_PIN_LGPIO18 (PAD_PIN_LGPIO_BASE + 18) ///< LGPIO18 +#define PAD_PIN_LGPIO19 (PAD_PIN_LGPIO_BASE + 19) ///< LGPIO19 +#define PAD_PIN_LGPIO20 (PAD_PIN_LGPIO_BASE + 20) ///< LGPIO20 +#define PAD_PIN_LGPIO21 (PAD_PIN_LGPIO_BASE + 21) ///< LGPIO21 +#define PAD_PIN_LGPIO22 (PAD_PIN_LGPIO_BASE + 22) ///< LGPIO22 +#define PAD_PIN_LGPIO23 (PAD_PIN_LGPIO_BASE + 23) ///< LGPIO23 +#define PAD_PIN_LGPIO24 (PAD_PIN_LGPIO_BASE + 24) ///< LGPIO24 +#define PAD_PIN_LGPIO25 (PAD_PIN_LGPIO_BASE + 25) ///< LGPIO25 +#define PAD_PIN_LGPIO26 (PAD_PIN_LGPIO_BASE + 26) ///< LGPIO26 +#define PAD_PIN_LGPIO27 (PAD_PIN_LGPIO_BASE + 27) ///< LGPIO27 +#define PAD_PIN_LGPIO28 (PAD_PIN_LGPIO_BASE + 28) ///< LGPIO28 +#define PAD_PIN_LGPIO29 (PAD_PIN_LGPIO_BASE + 29) ///< LGPIO29 +#define PAD_PIN_LGPIO30 (PAD_PIN_LGPIO_BASE + 30) ///< LGPIO30 +#define PAD_PIN_LGPIO31 (PAD_PIN_LGPIO_BASE + 31) ///< LGPIO31 +#define PAD_PIN_LGPIO32 (PAD_PIN_LGPIO_BASE + 32) ///< LGPIO32 +//LGPIOx group end + +//DGPIO group begin +#define PAD_PIN_DGPIO_BASE 300 +#define PAD_PIN_DGPIO0 (PAD_PIN_DGPIO_BASE + 0) ///< DGPIO0 +#define PAD_PIN_DGPIO1 (PAD_PIN_DGPIO_BASE + 1) ///< DGPIO1 +#define PAD_PIN_DGPIO2 (PAD_PIN_DGPIO_BASE + 2) ///< DGPIO2 +#define PAD_PIN_DGPIO3 (PAD_PIN_DGPIO_BASE + 3) ///< DGPIO3 +#define PAD_PIN_DGPIO4 (PAD_PIN_DGPIO_BASE + 4) ///< DGPIO4 +#define PAD_PIN_DGPIO5 (PAD_PIN_DGPIO_BASE + 5) ///< DGPIO5 +#define PAD_PIN_DGPIO6 (PAD_PIN_DGPIO_BASE + 6) ///< DGPIO6 +#define PAD_PIN_DGPIO7 (PAD_PIN_DGPIO_BASE + 7) ///< DGPIO7 +#define PAD_PIN_DGPIO8 (PAD_PIN_DGPIO_BASE + 8) ///< DGPIO8 +#define PAD_PIN_DGPIO9 (PAD_PIN_DGPIO_BASE + 9) ///< DGPIO9 +#define PAD_PIN_DGPIO10 (PAD_PIN_DGPIO_BASE + 10) ///< DGPIO10 +#define PAD_PIN_DGPIO11 (PAD_PIN_DGPIO_BASE + 11) ///< DGPIO11 +#define PAD_PIN_DGPIO12 (PAD_PIN_DGPIO_BASE + 12) ///< DGPIO12 +//DGPIO group end + +//@} + + + +#define PAD_DS_GROUP4_10 0x0000 +#define PAD_DS_GROUP6_16 0x1000 +#define PAD_DS_GROUP8 0x2000 +#define PAD_DS_GROUP16 0x4000 +#define PAD_DS_GROUP5_40 0x8000 + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_setDrivingSink() +*/ +//@{ +//CGPIO group begin +#define PAD_DS_CGPIO_BASE 0 +#define PAD_DS_CGPIO0 (PAD_DS_CGPIO_BASE + 0) ///< CGPIO0 +#define PAD_DS_CGPIO1 (PAD_DS_CGPIO_BASE + 1) ///< CGPIO1 +#define PAD_DS_CGPIO2 (PAD_DS_CGPIO_BASE + 2) ///< CGPIO2 +#define PAD_DS_CGPIO3 (PAD_DS_CGPIO_BASE + 3) ///< CGPIO3 +#define PAD_DS_CGPIO4 (PAD_DS_CGPIO_BASE + 4) ///< CGPIO4 +#define PAD_DS_CGPIO5 (PAD_DS_CGPIO_BASE + 5) ///< CGPIO5 +#define PAD_DS_CGPIO6 (PAD_DS_CGPIO_BASE + 6) ///< CGPIO6 +#define PAD_DS_CGPIO7 (PAD_DS_CGPIO_BASE + 7) ///< CGPIO7 +#define PAD_DS_CGPIO8 (PAD_DS_CGPIO_BASE + 8) ///< CGPIO8 +#define PAD_DS_CGPIO9 ((PAD_DS_CGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< CGPIO9 +#define PAD_DS_CGPIO10 (PAD_DS_CGPIO_BASE + 10) ///< CGPIO10 +#define PAD_DS_CGPIO11 (PAD_DS_CGPIO_BASE + 11) ///< CGPIO11 +#define PAD_DS_CGPIO12 (PAD_DS_CGPIO_BASE + 12) ///< CGPIO12 +#define PAD_DS_CGPIO13 (PAD_DS_CGPIO_BASE + 13) ///< CGPIO13 +#define PAD_DS_CGPIO14 (PAD_DS_CGPIO_BASE + 14) ///< CGPIO14 +#define PAD_DS_CGPIO15 (PAD_DS_CGPIO_BASE + 15) ///< CGPIO15 + +#define PAD_DS_CGPIO16 ((PAD_DS_CGPIO_BASE + 16) | PAD_DS_GROUP5_40) ///< CGPIO16 +#define PAD_DS_CGPIO17 ((PAD_DS_CGPIO_BASE + 17) | PAD_DS_GROUP5_40) ///< CGPIO17 +#define PAD_DS_CGPIO18 ((PAD_DS_CGPIO_BASE + 18) | PAD_DS_GROUP5_40) ///< CGPIO18 +#define PAD_DS_CGPIO19 ((PAD_DS_CGPIO_BASE + 19) | PAD_DS_GROUP5_40) ///< CGPIO19 +#define PAD_DS_CGPIO20 ((PAD_DS_CGPIO_BASE + 20) | PAD_DS_GROUP5_40) ///< CGPIO20 +#define PAD_DS_CGPIO21 ((PAD_DS_CGPIO_BASE + 21) | PAD_DS_GROUP5_40) ///< CGPIO21 +#define PAD_DS_CGPIO22 ((PAD_DS_CGPIO_BASE + 22) | PAD_DS_GROUP5_40) ///< CGPIO22 +#define PAD_DS_CGPIO23 ((PAD_DS_CGPIO_BASE + 23) | PAD_DS_GROUP5_40) ///< CGPIO23 +#define PAD_DS_CGPIO24 ((PAD_DS_CGPIO_BASE + 24) | PAD_DS_GROUP5_40) ///< CGPIO24 +#define PAD_DS_CGPIO25 ((PAD_DS_CGPIO_BASE + 25) | PAD_DS_GROUP5_40) ///< CGPIO25 +#define PAD_DS_CGPIO26 ((PAD_DS_CGPIO_BASE + 26) | PAD_DS_GROUP5_40) ///< CGPIO26 +#define PAD_DS_CGPIO27 ((PAD_DS_CGPIO_BASE + 27) | PAD_DS_GROUP5_40) ///< CGPIO27 +#define PAD_DS_CGPIO28 ((PAD_DS_CGPIO_BASE + 28) | PAD_DS_GROUP6_16) ///< CGPIO28 +#define PAD_DS_CGPIO29 (PAD_DS_CGPIO_BASE + 29) ///< CGPIO29 +#define PAD_DS_CGPIO30 (PAD_DS_CGPIO_BASE + 30) ///< CGPIO30 +#define PAD_DS_CGPIO31 (PAD_DS_CGPIO_BASE + 31) ///< CGPIO31 + +#define PAD_DS_CGPIO32 (PAD_DS_CGPIO_BASE + 32) ///< CGPIO32 +#define PAD_DS_CGPIO33 (PAD_DS_CGPIO_BASE + 33) ///< CGPIO33 +//CGPIO group end + +//SGPIO group Driving/Sink begin +#define PAD_DS_SGPIO_BASE 48 +#define PAD_DS_SGPIO0 ((PAD_DS_SGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< SGPIO0 +#define PAD_DS_SGPIO1 ((PAD_DS_SGPIO_BASE + 1) | PAD_DS_GROUP8) ///< SGPIO1 +#define PAD_DS_SGPIO2 ((PAD_DS_SGPIO_BASE + 2) | PAD_DS_GROUP8) ///< SGPIO2 +#define PAD_DS_SGPIO3 ((PAD_DS_SGPIO_BASE + 3) | PAD_DS_GROUP8) ///< SGPIO3 +#define PAD_DS_SGPIO4 ((PAD_DS_SGPIO_BASE + 4) | PAD_DS_GROUP8) ///< SGPIO4 +#define PAD_DS_SGPIO5 ((PAD_DS_SGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< SGPIO5 +#define PAD_DS_SGPIO6 ((PAD_DS_SGPIO_BASE + 6) | PAD_DS_GROUP8) ///< SGPIO6 +#define PAD_DS_SGPIO7 ((PAD_DS_SGPIO_BASE + 7) | PAD_DS_GROUP8) ///< SGPIO7 +#define PAD_DS_SGPIO8 (PAD_DS_SGPIO_BASE + 8) ///< SGPIO8 +#define PAD_DS_SGPIO9 (PAD_DS_SGPIO_BASE + 9) ///< SGPIO9 +#define PAD_DS_SGPIO10 (PAD_DS_SGPIO_BASE + 10) ///< SGPIO10 +#define PAD_DS_SGPIO11 (PAD_DS_SGPIO_BASE + 11) ///< SGPIO11 +//SGPIO group Driving/Sink end + +//PGPIO group Driving/Sink begin +#define PAD_DS_PGPIO_BASE 64 +#define PAD_DS_PGPIO0 (PAD_DS_PGPIO_BASE + 0) ///< PGPIO0 +#define PAD_DS_PGPIO1 (PAD_DS_PGPIO_BASE + 1) ///< PGPIO1 +#define PAD_DS_PGPIO2 (PAD_DS_PGPIO_BASE + 2) ///< PGPIO2 +#define PAD_DS_PGPIO3 (PAD_DS_PGPIO_BASE + 3) ///< PGPIO3 +#define PAD_DS_PGPIO4 (PAD_DS_PGPIO_BASE + 4) ///< PGPIO4 +#define PAD_DS_PGPIO5 (PAD_DS_PGPIO_BASE + 5) ///< PGPIO5 +#define PAD_DS_PGPIO6 (PAD_DS_PGPIO_BASE + 6) ///< PGPIO6 +#define PAD_DS_PGPIO7 (PAD_DS_PGPIO_BASE + 7) ///< PGPIO7 +#define PAD_DS_PGPIO8 (PAD_DS_PGPIO_BASE + 8) ///< PGPIO8 +#define PAD_DS_PGPIO9 (PAD_DS_PGPIO_BASE + 9) ///< PGPIO9 +#define PAD_DS_PGPIO10 (PAD_DS_PGPIO_BASE + 10) ///< PGPIO10 +#define PAD_DS_PGPIO11 (PAD_DS_PGPIO_BASE + 11) ///< PGPIO11 +#define PAD_DS_PGPIO12 (PAD_DS_PGPIO_BASE + 12) ///< PGPIO12 +#define PAD_DS_PGPIO13 (PAD_DS_PGPIO_BASE + 13) ///< PGPIO13 +#define PAD_DS_PGPIO14 (PAD_DS_PGPIO_BASE + 14) ///< PGPIO14 +#define PAD_DS_PGPIO15 (PAD_DS_PGPIO_BASE + 15) ///< PGPIO15 + +#define PAD_DS_PGPIO16 (PAD_DS_PGPIO_BASE + 16) ///< PGPIO16 +#define PAD_DS_PGPIO17 (PAD_DS_PGPIO_BASE + 17) ///< PGPIO17 +#define PAD_DS_PGPIO18 (PAD_DS_PGPIO_BASE + 18) ///< PGPIO18 +#define PAD_DS_PGPIO19 (PAD_DS_PGPIO_BASE + 19) ///< PGPIO19 +#define PAD_DS_PGPIO20 ((PAD_DS_PGPIO_BASE + 20) | PAD_DS_GROUP6_16) ///< PGPIO20 +#define PAD_DS_PGPIO21 ((PAD_DS_PGPIO_BASE + 21) | PAD_DS_GROUP6_16) ///< PGPIO21 +#define PAD_DS_PGPIO22 ((PAD_DS_PGPIO_BASE + 22) | PAD_DS_GROUP6_16) ///< PGPIO22 +#define PAD_DS_PGPIO23 ((PAD_DS_PGPIO_BASE + 23) | PAD_DS_GROUP6_16) ///< PGPIO23 +#define PAD_DS_PGPIO24 (PAD_DS_PGPIO_BASE + 24) ///< PGPIO24 +#define PAD_DS_PGPIO25 (PAD_DS_PGPIO_BASE + 25) ///< PGPIO25 +#define PAD_DS_PGPIO26 (PAD_DS_PGPIO_BASE + 26) ///< PGPIO26 +#define PAD_DS_PGPIO27 (PAD_DS_PGPIO_BASE + 27) ///< PGPIO27 +#define PAD_DS_PGPIO28 (PAD_DS_PGPIO_BASE + 28) ///< PGPIO28 +#define PAD_DS_PGPIO29 (PAD_DS_PGPIO_BASE + 29) ///< PGPIO29 +#define PAD_DS_PGPIO30 (PAD_DS_PGPIO_BASE + 30) ///< PGPIO30 +#define PAD_DS_PGPIO31 (PAD_DS_PGPIO_BASE + 31) ///< PGPIO31 + +#define PAD_DS_PGPIO32 (PAD_DS_PGPIO_BASE + 32) ///< PGPIO32 +#define PAD_DS_PGPIO33 (PAD_DS_PGPIO_BASE + 33) ///< PGPIO33 +#define PAD_DS_PGPIO34 (PAD_DS_PGPIO_BASE + 34) ///< PGPIO34 +#define PAD_DS_PGPIO35 (PAD_DS_PGPIO_BASE + 35) ///< PGPIO35 +#define PAD_DS_PGPIO36 (PAD_DS_PGPIO_BASE + 36) ///< PGPIO36 +#define PAD_DS_PGPIO37 (PAD_DS_PGPIO_BASE + 37) ///< PGPIO37 +#define PAD_DS_PGPIO38 (PAD_DS_PGPIO_BASE + 38) ///< PGPIO38 +#define PAD_DS_PGPIO39 (PAD_DS_PGPIO_BASE + 39) ///< PGPIO39 +#define PAD_DS_PGPIO40 (PAD_DS_PGPIO_BASE + 40) ///< PGPIO40 +#define PAD_DS_PGPIO41 (PAD_DS_PGPIO_BASE + 41) ///< PGPIO41 +#define PAD_DS_PGPIO42 ((PAD_DS_PGPIO_BASE + 42) | PAD_DS_GROUP8) ///< PGPIO42 +#define PAD_DS_PGPIO43 ((PAD_DS_PGPIO_BASE + 43) | PAD_DS_GROUP8) ///< PGPIO43 +#define PAD_DS_PGPIO44 ((PAD_DS_PGPIO_BASE + 44) | PAD_DS_GROUP8) ///< PGPIO44 +#define PAD_DS_PGPIO45 ((PAD_DS_PGPIO_BASE + 45) | PAD_DS_GROUP8) ///< PGPIO45 +#define PAD_DS_PGPIO46 ((PAD_DS_PGPIO_BASE + 46) | PAD_DS_GROUP8) ///< PGPIO46 +#define PAD_DS_PGPIO47 ((PAD_DS_PGPIO_BASE + 47) | PAD_DS_GROUP8) ///< PGPIO47 +//PGPIO group Driving/Sink end + +//LCD group Driving/Sink begin +#define PAD_DS_LGPIO_BASE 112 +#define PAD_DS_LGPIO0 ((PAD_DS_LGPIO_BASE + 0) | PAD_DS_GROUP6_16) ///< LGPIO0 +#define PAD_DS_LGPIO1 ((PAD_DS_LGPIO_BASE + 1) | PAD_DS_GROUP6_16) ///< LGPIO1 +#define PAD_DS_LGPIO2 ((PAD_DS_LGPIO_BASE + 2) | PAD_DS_GROUP6_16) ///< LGPIO2 +#define PAD_DS_LGPIO3 ((PAD_DS_LGPIO_BASE + 3) | PAD_DS_GROUP6_16) ///< LGPIO3 +#define PAD_DS_LGPIO4 ((PAD_DS_LGPIO_BASE + 4) | PAD_DS_GROUP6_16) ///< LGPIO4 +#define PAD_DS_LGPIO5 ((PAD_DS_LGPIO_BASE + 5) | PAD_DS_GROUP6_16) ///< LGPIO5 +#define PAD_DS_LGPIO6 ((PAD_DS_LGPIO_BASE + 6) | PAD_DS_GROUP6_16) ///< LGPIO6 +#define PAD_DS_LGPIO7 ((PAD_DS_LGPIO_BASE + 7) | PAD_DS_GROUP6_16) ///< LGPIO7 +#define PAD_DS_LGPIO8 ((PAD_DS_LGPIO_BASE + 8) | PAD_DS_GROUP6_16) ///< LGPIO8 +#define PAD_DS_LGPIO9 ((PAD_DS_LGPIO_BASE + 9) | PAD_DS_GROUP6_16) ///< LGPIO9 +#define PAD_DS_LGPIO10 ((PAD_DS_LGPIO_BASE + 10)| PAD_DS_GROUP6_16) ///< LGPIO10 +#define PAD_DS_LGPIO11 ((PAD_DS_LGPIO_BASE + 11)| PAD_DS_GROUP6_16) ///< LGPIO11 +#define PAD_DS_LGPIO12 ((PAD_DS_LGPIO_BASE + 12)| PAD_DS_GROUP6_16) ///< LGPIO12 +#define PAD_DS_LGPIO13 ((PAD_DS_LGPIO_BASE + 13)| PAD_DS_GROUP6_16) ///< LGPIO13 +#define PAD_DS_LGPIO14 ((PAD_DS_LGPIO_BASE + 14)| PAD_DS_GROUP6_16) ///< LGPIO14 +#define PAD_DS_LGPIO15 ((PAD_DS_LGPIO_BASE + 15)| PAD_DS_GROUP6_16) ///< LGPIO15 + +#define PAD_DS_LGPIO16 ((PAD_DS_LGPIO_BASE + 16)| PAD_DS_GROUP6_16) ///< LGPIO16 +#define PAD_DS_LGPIO17 ((PAD_DS_LGPIO_BASE + 17)| PAD_DS_GROUP6_16) ///< LGPIO17 +#define PAD_DS_LGPIO18 ((PAD_DS_LGPIO_BASE + 18)| PAD_DS_GROUP6_16) ///< LGPIO18 +#define PAD_DS_LGPIO19 ((PAD_DS_LGPIO_BASE + 19)| PAD_DS_GROUP6_16) ///< LGPIO19 +#define PAD_DS_LGPIO20 ((PAD_DS_LGPIO_BASE + 20)| PAD_DS_GROUP6_16) ///< LGPIO20 +#define PAD_DS_LGPIO21 ((PAD_DS_LGPIO_BASE + 21)| PAD_DS_GROUP6_16) ///< LGPIO21 +#define PAD_DS_LGPIO22 ((PAD_DS_LGPIO_BASE + 22)| PAD_DS_GROUP6_16) ///< LGPIO22 +#define PAD_DS_LGPIO23 ((PAD_DS_LGPIO_BASE + 23)| PAD_DS_GROUP6_16) ///< LGPIO23 +#define PAD_DS_LGPIO24 ((PAD_DS_LGPIO_BASE + 24)| PAD_DS_GROUP6_16) ///< LGPIO24 +#define PAD_DS_LGPIO25 ((PAD_DS_LGPIO_BASE + 25)| PAD_DS_GROUP6_16) ///< LGPIO25 +#define PAD_DS_LGPIO26 ((PAD_DS_LGPIO_BASE + 26)| PAD_DS_GROUP6_16) ///< LGPIO26 +#define PAD_DS_LGPIO27 ((PAD_DS_LGPIO_BASE + 27)| PAD_DS_GROUP6_16) ///< LGPIO27 +#define PAD_DS_LGPIO28 ((PAD_DS_LGPIO_BASE + 28)| PAD_DS_GROUP6_16) ///< LGPIO28 +#define PAD_DS_LGPIO29 ((PAD_DS_LGPIO_BASE + 29)| PAD_DS_GROUP6_16) ///< LGPIO29 +#define PAD_DS_LGPIO30 ((PAD_DS_LGPIO_BASE + 30)| PAD_DS_GROUP4_10) ///< LGPIO30 +#define PAD_DS_LGPIO31 ((PAD_DS_LGPIO_BASE + 31)| PAD_DS_GROUP4_10) ///< LGPIO31 +#define PAD_DS_LGPIO32 ((PAD_DS_LGPIO_BASE + 32)| PAD_DS_GROUP4_10) ///< LGPIO32 +//LCD group Driving/Sink end + +//DGPIO group Driving/Sink begin +#define PAD_DS_DGPIO_BASE 160 +#define PAD_DS_DGPIO0 ((PAD_DS_DGPIO_BASE + 0) | PAD_DS_GROUP16) ///< DGPIO0 +#define PAD_DS_DGPIO1 ((PAD_DS_DGPIO_BASE + 1) | PAD_DS_GROUP16) ///< DGPIO1 +#define PAD_DS_DGPIO2 ((PAD_DS_DGPIO_BASE + 2) | PAD_DS_GROUP16) ///< DGPIO2 +#define PAD_DS_DGPIO3 ((PAD_DS_DGPIO_BASE + 3) | PAD_DS_GROUP16) ///< DGPIO3 +#define PAD_DS_DGPIO4 ((PAD_DS_DGPIO_BASE + 4) | PAD_DS_GROUP16) ///< DGPIO4 +#define PAD_DS_DGPIO5 ((PAD_DS_DGPIO_BASE + 5) | PAD_DS_GROUP16) ///< DGPIO5 +#define PAD_DS_DGPIO6 ((PAD_DS_DGPIO_BASE + 6) | PAD_DS_GROUP8) ///< DGPIO6 +#define PAD_DS_DGPIO7 ((PAD_DS_DGPIO_BASE + 7) | PAD_DS_GROUP8) ///< DGPIO7 +#define PAD_DS_DGPIO8 ((PAD_DS_DGPIO_BASE + 8) | PAD_DS_GROUP8) ///< DGPIO8 +#define PAD_DS_DGPIO9 ((PAD_DS_DGPIO_BASE + 9) | PAD_DS_GROUP8) ///< DGPIO9 +#define PAD_DS_DGPIO10 ((PAD_DS_DGPIO_BASE + 10)| PAD_DS_GROUP8) ///< DGPIO10 +#define PAD_DS_DGPIO11 ((PAD_DS_DGPIO_BASE + 11)| PAD_DS_GROUP4_10) ///< DGPIO11 +#define PAD_DS_DGPIO12 ((PAD_DS_DGPIO_BASE + 12)| PAD_DS_GROUP4_10) ///< DGPIO12 +//DGPIO group Driving/Sink end +//@} + +#endif + +/** + @addtogroup mIDrvSys_PAD +*/ +//@{ + + +#define PAD_C_GPIO_BASE 0 +#define PAD_S_GPIO_BASE 96 +#define PAD_P_GPIO_BASE 128 +#define PAD_L_GPIO_BASE 224 +#define PAD_D_GPIO_BASE 288 +#define PAD_H_GPIO_BASE 320 +#define PAD_A_GPIO_BASE 352 +#define PAD_DS_GROUP_10 0x00000000 +#define PAD_DS_GROUP_16 0x10000000 +#define PAD_DS_GROUP_40 0x80000000 + +/** + @name Pad type pin ID. + + Pad type pin ID. + + Pad ID of pad_set_pull_up_down (), pad_get_pull_up_down (). +*/ +#define PAD_PIN_NOT_EXIST (64) // For backward compatible +//@{ +typedef enum { + + //C_GPIO group + PAD_PIN_CGPIO0 = (PAD_C_GPIO_BASE + 0), ///< C_GPIO_0 + PAD_PIN_CGPIO1 = (PAD_C_GPIO_BASE + 2), ///< C_GPIO_1 + PAD_PIN_CGPIO2 = (PAD_C_GPIO_BASE + 4), ///< C_GPIO_2 + PAD_PIN_CGPIO3 = (PAD_C_GPIO_BASE + 6), ///< C_GPIO_3 + PAD_PIN_CGPIO4 = (PAD_C_GPIO_BASE + 8), ///< C_GPIO_4 + PAD_PIN_CGPIO5 = (PAD_C_GPIO_BASE + 10), ///< C_GPIO_5 + PAD_PIN_CGPIO6 = (PAD_C_GPIO_BASE + 12), ///< C_GPIO_6 + PAD_PIN_CGPIO7 = (PAD_C_GPIO_BASE + 14), ///< C_GPIO_7 + PAD_PIN_CGPIO8 = (PAD_C_GPIO_BASE + 16), ///< C_GPIO_8 + PAD_PIN_CGPIO9 = (PAD_C_GPIO_BASE + 18), ///< C_GPIO_9 + PAD_PIN_CGPIO10 = (PAD_C_GPIO_BASE + 20), ///< C_GPIO_10 + PAD_PIN_CGPIO11 = (PAD_C_GPIO_BASE + 22), ///< C_GPIO_11 + PAD_PIN_CGPIO12 = (PAD_C_GPIO_BASE + 24), ///< C_GPIO_12 + PAD_PIN_CGPIO13 = (PAD_C_GPIO_BASE + 26), ///< C_GPIO_13 + PAD_PIN_CGPIO14 = (PAD_C_GPIO_BASE + 28), ///< C_GPIO_14 + PAD_PIN_CGPIO15 = (PAD_C_GPIO_BASE + 30), ///< C_GPIO_15 + PAD_PIN_CGPIO16 = (PAD_C_GPIO_BASE + 32), ///< C_GPIO_16 + PAD_PIN_CGPIO17 = (PAD_C_GPIO_BASE + 34), ///< C_GPIO_17 + PAD_PIN_CGPIO18 = (PAD_C_GPIO_BASE + 36), ///< C_GPIO_18 + PAD_PIN_CGPIO19 = (PAD_C_GPIO_BASE + 38), ///< C_GPIO_19 + PAD_PIN_CGPIO20 = (PAD_C_GPIO_BASE + 40), ///< C_GPIO_20 + PAD_PIN_CGPIO21 = (PAD_C_GPIO_BASE + 42), ///< C_GPIO_21 + PAD_PIN_CGPIO22 = (PAD_C_GPIO_BASE + 44), ///< C_GPIO_22 + + //S_GPIO group + PAD_PIN_SGPIO0 = (PAD_S_GPIO_BASE + 0), ///< S_GPIO_0 + PAD_PIN_SGPIO1 = (PAD_S_GPIO_BASE + 2), ///< S_GPIO_1 + PAD_PIN_SGPIO2 = (PAD_S_GPIO_BASE + 4), ///< S_GPIO_2 + PAD_PIN_SGPIO3 = (PAD_S_GPIO_BASE + 6), ///< S_GPIO_3 + PAD_PIN_SGPIO4 = (PAD_S_GPIO_BASE + 8), ///< S_GPIO_4 + PAD_PIN_SGPIO5 = (PAD_S_GPIO_BASE + 10), ///< S_GPIO_5 + PAD_PIN_SGPIO6 = (PAD_S_GPIO_BASE + 12), ///< S_GPIO_6 + PAD_PIN_SGPIO7 = (PAD_S_GPIO_BASE + 14), ///< S_GPIO_7 + PAD_PIN_SGPIO8 = (PAD_S_GPIO_BASE + 16), ///< S_GPIO_8 + PAD_PIN_SGPIO9 = (PAD_S_GPIO_BASE + 18), ///< S_GPIO_9 + PAD_PIN_SGPIO10 = (PAD_S_GPIO_BASE + 20), ///< S_GPIO_10 + PAD_PIN_SGPIO11 = (PAD_S_GPIO_BASE + 22), ///< S_GPIO_11 + PAD_PIN_SGPIO12 = (PAD_S_GPIO_BASE + 24), ///< S_GPIO_12 + + //P_GPIO group + PAD_PIN_PGPIO0 = (PAD_P_GPIO_BASE + 0), ///< P_GPIO_0 + PAD_PIN_PGPIO1 = (PAD_P_GPIO_BASE + 2), ///< P_GPIO_1 + PAD_PIN_PGPIO2 = (PAD_P_GPIO_BASE + 4), ///< P_GPIO_2 + PAD_PIN_PGPIO3 = (PAD_P_GPIO_BASE + 6), ///< P_GPIO_3 + PAD_PIN_PGPIO4 = (PAD_P_GPIO_BASE + 8), ///< P_GPIO_4 + PAD_PIN_PGPIO5 = (PAD_P_GPIO_BASE + 10), ///< P_GPIO_5 + PAD_PIN_PGPIO6 = (PAD_P_GPIO_BASE + 12), ///< P_GPIO_6 + PAD_PIN_PGPIO7 = (PAD_P_GPIO_BASE + 14), ///< P_GPIO_7 + PAD_PIN_PGPIO8 = (PAD_P_GPIO_BASE + 16), ///< P_GPIO_8 + PAD_PIN_PGPIO9 = (PAD_P_GPIO_BASE + 18), ///< P_GPIO_9 + PAD_PIN_PGPIO10 = (PAD_P_GPIO_BASE + 20), ///< P_GPIO_10 + PAD_PIN_PGPIO11 = (PAD_P_GPIO_BASE + 22), ///< P_GPIO_11 + PAD_PIN_PGPIO12 = (PAD_P_GPIO_BASE + 24), ///< P_GPIO_12 + PAD_PIN_PGPIO13 = (PAD_P_GPIO_BASE + 26), ///< P_GPIO_13 + PAD_PIN_PGPIO14 = (PAD_P_GPIO_BASE + 28), ///< P_GPIO_14 + PAD_PIN_PGPIO15 = (PAD_P_GPIO_BASE + 30), ///< P_GPIO_15 + PAD_PIN_PGPIO16 = (PAD_P_GPIO_BASE + 32), ///< P_GPIO_16 + PAD_PIN_PGPIO17 = (PAD_P_GPIO_BASE + 34), ///< P_GPIO_17 + PAD_PIN_PGPIO18 = (PAD_P_GPIO_BASE + 36), ///< P_GPIO_18 + PAD_PIN_PGPIO19 = (PAD_P_GPIO_BASE + 38), ///< P_GPIO_19 + PAD_PIN_PGPIO20 = (PAD_P_GPIO_BASE + 40), ///< P_GPIO_20 + PAD_PIN_PGPIO21 = (PAD_P_GPIO_BASE + 42), ///< P_GPIO_21 + PAD_PIN_PGPIO22 = (PAD_P_GPIO_BASE + 44), ///< P_GPIO_22 + PAD_PIN_PGPIO23 = (PAD_P_GPIO_BASE + 46), ///< P_GPIO_23 + PAD_PIN_PGPIO24 = (PAD_P_GPIO_BASE + 48), ///< P_GPIO_24 + + //L_GPIO group + PAD_PIN_LGPIO0 = (PAD_L_GPIO_BASE + 0), ///< L_GPIO_0 + PAD_PIN_LGPIO1 = (PAD_L_GPIO_BASE + 2), ///< L_GPIO_1 + PAD_PIN_LGPIO2 = (PAD_L_GPIO_BASE + 4), ///< L_GPIO_2 + PAD_PIN_LGPIO3 = (PAD_L_GPIO_BASE + 6), ///< L_GPIO_3 + PAD_PIN_LGPIO4 = (PAD_L_GPIO_BASE + 8), ///< L_GPIO_4 + PAD_PIN_LGPIO5 = (PAD_L_GPIO_BASE + 10), ///< L_GPIO_5 + PAD_PIN_LGPIO6 = (PAD_L_GPIO_BASE + 12), ///< L_GPIO_6 + PAD_PIN_LGPIO7 = (PAD_L_GPIO_BASE + 14), ///< L_GPIO_7 + PAD_PIN_LGPIO8 = (PAD_L_GPIO_BASE + 16), ///< L_GPIO_8 + PAD_PIN_LGPIO9 = (PAD_L_GPIO_BASE + 18), ///< L_GPIO_9 + PAD_PIN_LGPIO10 = (PAD_L_GPIO_BASE + 20), ///< L_GPIO_10 + PAD_PIN_LGPIO11 = (PAD_L_GPIO_BASE + 22), ///< L_GPIO_11 + PAD_PIN_LGPIO12 = (PAD_L_GPIO_BASE + 24), ///< L_GPIO_12 + PAD_PIN_LGPIO13 = (PAD_L_GPIO_BASE + 26), ///< L_GPIO_13 + PAD_PIN_LGPIO14 = (PAD_L_GPIO_BASE + 28), ///< L_GPIO_14 + PAD_PIN_LGPIO15 = (PAD_L_GPIO_BASE + 30), ///< L_GPIO_15 + PAD_PIN_LGPIO16 = (PAD_L_GPIO_BASE + 32), ///< L_GPIO_16 + PAD_PIN_LGPIO17 = (PAD_L_GPIO_BASE + 34), ///< L_GPIO_17 + PAD_PIN_LGPIO18 = (PAD_L_GPIO_BASE + 36), ///< L_GPIO_18 + PAD_PIN_LGPIO19 = (PAD_L_GPIO_BASE + 38), ///< L_GPIO_19 + PAD_PIN_LGPIO20 = (PAD_L_GPIO_BASE + 40), ///< L_GPIO_20 + PAD_PIN_LGPIO21 = (PAD_L_GPIO_BASE + 42), ///< L_GPIO_21 + PAD_PIN_LGPIO22 = (PAD_L_GPIO_BASE + 44), ///< L_GPIO_22 + PAD_PIN_LGPIO23 = (PAD_L_GPIO_BASE + 46), ///< L_GPIO_23 + PAD_PIN_LGPIO24 = (PAD_L_GPIO_BASE + 48), ///< L_GPIO_23 + + //D_GPIO group + PAD_PIN_DGPIO0 = (PAD_D_GPIO_BASE + 0), ///< D_GPIO_0 + PAD_PIN_DGPIO1 = (PAD_D_GPIO_BASE + 2), ///< D_GPIO_1 + PAD_PIN_DGPIO2 = (PAD_D_GPIO_BASE + 4), ///< D_GPIO_2 + PAD_PIN_DGPIO3 = (PAD_D_GPIO_BASE + 6), ///< D_GPIO_3 + PAD_PIN_DGPIO4 = (PAD_D_GPIO_BASE + 8), ///< D_GPIO_4 + PAD_PIN_DGPIO5 = (PAD_D_GPIO_BASE + 10), ///< D_GPIO_5 + PAD_PIN_DGPIO6 = (PAD_D_GPIO_BASE + 12), ///< D_GPIO_6 + PAD_PIN_DGPIO7 = (PAD_D_GPIO_BASE + 14), ///< D_GPIO_7 + + //HSI_GPIO group + PAD_PIN_HSIGPIO0 = (PAD_H_GPIO_BASE + 0), ///< HSI_GPIO_0 + PAD_PIN_HSIGPIO1 = (PAD_H_GPIO_BASE + 2), ///< HSI_GPIO_1 + PAD_PIN_HSIGPIO2 = (PAD_H_GPIO_BASE + 4), ///< HSI_GPIO_2 + PAD_PIN_HSIGPIO3 = (PAD_H_GPIO_BASE + 6), ///< HSI_GPIO_3 + PAD_PIN_HSIGPIO4 = (PAD_H_GPIO_BASE + 8), ///< HSI_GPIO_4 + PAD_PIN_HSIGPIO5 = (PAD_H_GPIO_BASE + 10), ///< HSI_GPIO_5 + PAD_PIN_HSIGPIO6 = (PAD_H_GPIO_BASE + 12), ///< HSI_GPIO_6 + PAD_PIN_HSIGPIO7 = (PAD_H_GPIO_BASE + 14), ///< HSI_GPIO_7 + PAD_PIN_HSIGPIO8 = (PAD_H_GPIO_BASE + 16), ///< HSI_GPIO_8 + PAD_PIN_HSIGPIO9 = (PAD_H_GPIO_BASE + 18), ///< HSI_GPIO_9 + PAD_PIN_HSIGPIO10 = (PAD_H_GPIO_BASE + 20), ///< HSI_GPIO_10 + PAD_PIN_HSIGPIO11 = (PAD_H_GPIO_BASE + 22), ///< HSI_GPIO_11 + + //A_GPIO group + PAD_PIN_AGPIO0 = (PAD_A_GPIO_BASE + 0), ///< A_GPIO_0 + PAD_PIN_AGPIO1 = (PAD_A_GPIO_BASE + 2), ///< A_GPIO_1 + PAD_PIN_AGPIO2 = (PAD_A_GPIO_BASE + 4), ///< A_GPIO_2 + + PAD_PIN_MAX = PAD_PIN_AGPIO2, + ENUM_DUMMY4WORD(PAD_PIN) +} PAD_PIN; +//@} + +/** + Pad type select + + Pad type select + + Pad type value for pad_set_pull_up_down(), pad_get_pull_up_down(). +*/ +typedef enum { + PAD_NONE = 0x00, ///< none of pull up/down + PAD_PULLDOWN = 0x01, ///< pull down + PAD_PULLUP = 0x02, ///< pull up + PAD_KEEPER = 0x03, ///< keeper + + ENUM_DUMMY4WORD(PAD_PULL) +} PAD_PULL; + +/** + Pad driving select + + Pad driving select + + Pad driving value for pad_set_driving_sink(), pad_get_driving_sink(). +*/ +typedef enum { + PAD_DRIVINGSINK_4MA = 0x0001, ///< Pad driver/sink 4mA + PAD_DRIVINGSINK_10MA = 0x0202, ///< Pad driver/sink 10mA + + PAD_DRIVINGSINK_6MA = 0x0010, ///< Pad driver/sink 6mA + PAD_DRIVINGSINK_16MA = 0x0020, ///< Pad driver/sink 16mA + + PAD_DRIVINGSINK_5MA = 0x0100, ///< Pad driver/sink 5mA + PAD_DRIVINGSINK_15MA = 0x0400, ///< Pad driver/sink 15mA + PAD_DRIVINGSINK_20MA = 0x0800, ///< Pad driver/sink 20mA + PAD_DRIVINGSINK_25MA = 0x1000, ///< Pad driver/sink 25mA + PAD_DRIVINGSINK_30MA = 0x2000, ///< Pad driver/sink 30mA + PAD_DRIVINGSINK_35MA = 0x4000, ///< Pad driver/sink 35mA + PAD_DRIVINGSINK_40MA = 0x8000, ///< Pad driver/sink 40mA + + ENUM_DUMMY4WORD(PAD_DRIVINGSINK) +} PAD_DRIVINGSINK; + +/** + @name Pad driving pin ID. + + Pad driving pin ID. + + Pad ID of pad_set_driving_sink(), pad_get_driving_sink() +*/ +//@{ +typedef enum { + + //C_GPIO group + PAD_DS_CGPIO0 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< C_GPIO_0 + PAD_DS_CGPIO1 = ((PAD_C_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< C_GPIO_1 + PAD_DS_CGPIO2 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< C_GPIO_2 + PAD_DS_CGPIO3 = ((PAD_C_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< C_GPIO_3 + PAD_DS_CGPIO4 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< C_GPIO_4 + PAD_DS_CGPIO5 = ((PAD_C_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< C_GPIO_5 + PAD_DS_CGPIO6 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< C_GPIO_6 + PAD_DS_CGPIO7 = ((PAD_C_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< C_GPIO_7 + PAD_DS_CGPIO8 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< C_GPIO_8 + PAD_DS_CGPIO9 = ((PAD_C_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< C_GPIO_9 + PAD_DS_CGPIO10 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< C_GPIO_10 + PAD_DS_CGPIO11 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_40), ///< C_GPIO_11 + PAD_DS_CGPIO12 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_40), ///< C_GPIO_12 + PAD_DS_CGPIO13 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_40), ///< C_GPIO_13 + PAD_DS_CGPIO14 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_40), ///< C_GPIO_14 + PAD_DS_CGPIO15 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_40), ///< C_GPIO_15 + PAD_DS_CGPIO16 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_40), ///< C_GPIO_16 + PAD_DS_CGPIO17 = ((PAD_C_GPIO_BASE + 24) | PAD_DS_GROUP_40), ///< C_GPIO_17 + PAD_DS_CGPIO18 = ((PAD_C_GPIO_BASE + 36) | PAD_DS_GROUP_16), ///< C_GPIO_18 + PAD_DS_CGPIO19 = ((PAD_C_GPIO_BASE + 38) | PAD_DS_GROUP_16), ///< C_GPIO_19 + PAD_DS_CGPIO20 = ((PAD_C_GPIO_BASE + 40) | PAD_DS_GROUP_16), ///< C_GPIO_20 + PAD_DS_CGPIO21 = ((PAD_C_GPIO_BASE + 42) | PAD_DS_GROUP_16), ///< C_GPIO_21 + PAD_DS_CGPIO22 = ((PAD_C_GPIO_BASE + 44) | PAD_DS_GROUP_16), ///< C_GPIO_22 + + //S_GPIO group + PAD_DS_SGPIO0 = ((PAD_S_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< S_GPIO_0 + PAD_DS_SGPIO1 = ((PAD_S_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< S_GPIO_1 + PAD_DS_SGPIO2 = ((PAD_S_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< S_GPIO_2 + PAD_DS_SGPIO3 = ((PAD_S_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< S_GPIO_3 + PAD_DS_SGPIO4 = ((PAD_S_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< S_GPIO_4 + PAD_DS_SGPIO5 = ((PAD_S_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< S_GPIO_5 + PAD_DS_SGPIO6 = ((PAD_S_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< S_GPIO_6 + PAD_DS_SGPIO7 = ((PAD_S_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< S_GPIO_7 + PAD_DS_SGPIO8 = ((PAD_S_GPIO_BASE + 16) | PAD_DS_GROUP_10), ///< S_GPIO_8 + PAD_DS_SGPIO9 = ((PAD_S_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< S_GPIO_9 + PAD_DS_SGPIO10 = ((PAD_S_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< S_GPIO_10 + PAD_DS_SGPIO11 = ((PAD_S_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< S_GPIO_11 + PAD_DS_SGPIO12 = ((PAD_S_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< S_GPIO_12 + + //P_GPIO group + PAD_DS_PGPIO0 = ((PAD_P_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< P_GPIO_0 + PAD_DS_PGPIO1 = ((PAD_P_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< P_GPIO_1 + PAD_DS_PGPIO2 = ((PAD_P_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< P_GPIO_2 + PAD_DS_PGPIO3 = ((PAD_P_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< P_GPIO_3 + PAD_DS_PGPIO4 = ((PAD_P_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< P_GPIO_4 + PAD_DS_PGPIO5 = ((PAD_P_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< P_GPIO_5 + PAD_DS_PGPIO6 = ((PAD_P_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< P_GPIO_6 + PAD_DS_PGPIO7 = ((PAD_P_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< P_GPIO_7 + PAD_DS_PGPIO8 = ((PAD_P_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< P_GPIO_8 + PAD_DS_PGPIO9 = ((PAD_P_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< P_GPIO_9 + PAD_DS_PGPIO10 = ((PAD_P_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< P_GPIO_10 + PAD_DS_PGPIO11 = ((PAD_P_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< P_GPIO_11 + PAD_DS_PGPIO12 = ((PAD_P_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< P_GPIO_12 + PAD_DS_PGPIO13 = ((PAD_P_GPIO_BASE + 26) | PAD_DS_GROUP_10), ///< P_GPIO_13 + PAD_DS_PGPIO14 = ((PAD_P_GPIO_BASE + 28) | PAD_DS_GROUP_10), ///< P_GPIO_14 + PAD_DS_PGPIO15 = ((PAD_P_GPIO_BASE + 30) | PAD_DS_GROUP_10), ///< P_GPIO_15 + PAD_DS_PGPIO16 = ((PAD_P_GPIO_BASE + 32) | PAD_DS_GROUP_10), ///< P_GPIO_16 + PAD_DS_PGPIO17 = ((PAD_P_GPIO_BASE + 34) | PAD_DS_GROUP_10), ///< P_GPIO_17 + PAD_DS_PGPIO18 = ((PAD_P_GPIO_BASE + 36) | PAD_DS_GROUP_10), ///< P_GPIO_18 + PAD_DS_PGPIO19 = ((PAD_P_GPIO_BASE + 38) | PAD_DS_GROUP_10), ///< P_GPIO_19 + PAD_DS_PGPIO20 = ((PAD_P_GPIO_BASE + 40) | PAD_DS_GROUP_10), ///< P_GPIO_20 + PAD_DS_PGPIO21 = ((PAD_P_GPIO_BASE + 42) | PAD_DS_GROUP_10), ///< P_GPIO_21 + PAD_DS_PGPIO22 = ((PAD_P_GPIO_BASE + 44) | PAD_DS_GROUP_10), ///< P_GPIO_22 + PAD_DS_PGPIO23 = ((PAD_P_GPIO_BASE + 46) | PAD_DS_GROUP_10), ///< P_GPIO_23 + PAD_DS_PGPIO24 = ((PAD_P_GPIO_BASE + 48) | PAD_DS_GROUP_10), ///< P_GPIO_24 + + //L_GPIO group + PAD_DS_LGPIO0 = ((PAD_L_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< L_GPIO_0 + PAD_DS_LGPIO1 = ((PAD_L_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< L_GPIO_1 + PAD_DS_LGPIO2 = ((PAD_L_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< L_GPIO_2 + PAD_DS_LGPIO3 = ((PAD_L_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< L_GPIO_3 + PAD_DS_LGPIO4 = ((PAD_L_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< L_GPIO_4 + PAD_DS_LGPIO5 = ((PAD_L_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< L_GPIO_5 + PAD_DS_LGPIO6 = ((PAD_L_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< L_GPIO_6 + PAD_DS_LGPIO7 = ((PAD_L_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< L_GPIO_7 + PAD_DS_LGPIO8 = ((PAD_L_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< L_GPIO_8 + PAD_DS_LGPIO9 = ((PAD_L_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< L_GPIO_9 + PAD_DS_LGPIO10 = ((PAD_L_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< L_GPIO_10 + PAD_DS_LGPIO11 = ((PAD_L_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< L_GPIO_11 + PAD_DS_LGPIO12 = ((PAD_L_GPIO_BASE + 24) | PAD_DS_GROUP_10), ///< L_GPIO_12 + PAD_DS_LGPIO13 = ((PAD_L_GPIO_BASE + 26) | PAD_DS_GROUP_10), ///< L_GPIO_13 + PAD_DS_LGPIO14 = ((PAD_L_GPIO_BASE + 28) | PAD_DS_GROUP_10), ///< L_GPIO_14 + PAD_DS_LGPIO15 = ((PAD_L_GPIO_BASE + 30) | PAD_DS_GROUP_10), ///< L_GPIO_15 + PAD_DS_LGPIO16 = ((PAD_L_GPIO_BASE + 32) | PAD_DS_GROUP_10), ///< L_GPIO_16 + PAD_DS_LGPIO17 = ((PAD_L_GPIO_BASE + 34) | PAD_DS_GROUP_10), ///< L_GPIO_17 + PAD_DS_LGPIO18 = ((PAD_L_GPIO_BASE + 36) | PAD_DS_GROUP_10), ///< L_GPIO_18 + PAD_DS_LGPIO19 = ((PAD_L_GPIO_BASE + 38) | PAD_DS_GROUP_10), ///< L_GPIO_19 + PAD_DS_LGPIO20 = ((PAD_L_GPIO_BASE + 40) | PAD_DS_GROUP_10), ///< L_GPIO_20 + PAD_DS_LGPIO21 = ((PAD_L_GPIO_BASE + 42) | PAD_DS_GROUP_10), ///< L_GPIO_21 + PAD_DS_LGPIO22 = ((PAD_L_GPIO_BASE + 44) | PAD_DS_GROUP_10), ///< L_GPIO_22 + PAD_DS_LGPIO23 = ((PAD_L_GPIO_BASE + 46) | PAD_DS_GROUP_10), ///< L_GPIO_23 + PAD_DS_LGPIO24 = ((PAD_L_GPIO_BASE + 48) | PAD_DS_GROUP_10), ///< L_GPIO_23 + + //D_GPIO group + PAD_DS_DGPIO0 = ((PAD_D_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< D_GPIO_0 + PAD_DS_DGPIO1 = ((PAD_D_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< D_GPIO_1 + PAD_DS_DGPIO2 = ((PAD_D_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< D_GPIO_2 + PAD_DS_DGPIO3 = ((PAD_D_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< D_GPIO_3 + PAD_DS_DGPIO4 = ((PAD_D_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< D_GPIO_4 + PAD_DS_DGPIO5 = ((PAD_D_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< D_GPIO_5 + PAD_DS_DGPIO6 = ((PAD_D_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< D_GPIO_6 + PAD_DS_DGPIO7 = ((PAD_D_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< D_GPIO_7 + + //HSI_GPIO group + PAD_DS_HSIGPIO0 = ((PAD_H_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< HSI_GPIO_0 + PAD_DS_HSIGPIO1 = ((PAD_H_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< HSI_GPIO_1 + PAD_DS_HSIGPIO2 = ((PAD_H_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< HSI_GPIO_2 + PAD_DS_HSIGPIO3 = ((PAD_H_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< HSI_GPIO_3 + PAD_DS_HSIGPIO4 = ((PAD_H_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< HSI_GPIO_4 + PAD_DS_HSIGPIO5 = ((PAD_H_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< HSI_GPIO_5 + PAD_DS_HSIGPIO6 = ((PAD_H_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< HSI_GPIO_6 + PAD_DS_HSIGPIO7 = ((PAD_H_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< HSI_GPIO_7 + PAD_DS_HSIGPIO8 = ((PAD_H_GPIO_BASE + 16) | PAD_DS_GROUP_10), ///< HSI_GPIO_8 + PAD_DS_HSIGPIO9 = ((PAD_H_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< HSI_GPIO_9 + PAD_DS_HSIGPIO10 = ((PAD_H_GPIO_BASE + 20) | PAD_DS_GROUP_10), ///< HSI_GPIO_10 + PAD_DS_HSIGPIO11 = ((PAD_H_GPIO_BASE + 22) | PAD_DS_GROUP_10), ///< HSI_GPIO_11 + + //A_GPIO group + PAD_DS_AGPIO0 = ((PAD_A_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< A_GPIO_0 + PAD_DS_AGPIO1 = ((PAD_A_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< A_GPIO_1 + PAD_DS_AGPIO2 = ((PAD_A_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< A_GPIO_2 + + PAD_DS_MAX = PAD_DS_AGPIO2, + ENUM_DUMMY4WORD(PAD_DS) +} PAD_DS; +//@} + +/** + Pad power ID select + + Pad power ID for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_POWERID_MC0 = 0x00, ///< Pad power id for MC0 + PAD_POWERID_MC1 = 0x01, ///< Pad power id for MC1 + PAD_POWERID_ADC = 0x02, ///< Pad power id for Audio ADC + PAD_POWERID_CSI = 0x04, ///< Pad power id for CSI/LVDS + + ENUM_DUMMY4WORD(PAD_POWERID) +} PAD_POWERID; + +/** + Pad power select + + Pad power value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_3P3V = 0x00, ///< Pad power is 3.3V + PAD_AVDD = 0x00, ///< Pad power is AVDD ( for PAD_POWERID_ADC use) + PAD_1P8V = 0x01, ///< Pad power is 1.8V + PAD_PAD_VAD = 0x01, ///< Pad power is PAD_ADC_VAD ( for PAD_POWERID_ADC use) + + ENUM_DUMMY4WORD(PAD_POWER) +} PAD_POWER; + +/** + Pad power VAD for PAD_POWERID_ADC + + Pad power VAD value for PAD_POWER_STRUCT. +*/ +typedef enum { + PAD_VAD_2P9V = 0x00, ///< Pad power VAD = 2.9V + PAD_VAD_3P0V = 0x01, ///< Pad power VAD = 3.0V + PAD_VAD_3P1V = 0x03, ///< Pad power VAD = 3.1V + + PAD_VAD_2P4V = 0x100, ///< Pad power VAD = 2.4V + PAD_VAD_2P5V = 0x101, ///< Pad power VAD = 2.5V + PAD_VAD_2P6V = 0x103, ///< Pad power VAD = 2.6V + + ENUM_DUMMY4WORD(PAD_VAD) +} PAD_VAD; + + +/** + PAD power structure + + PAD power setting for pad_set_power() +*/ +typedef struct { + PAD_POWERID power_id; ///< Pad power id + PAD_POWER power; ///< Pad power + BOOL bias_current; ///< Regulator bias current selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL opa_gain; ///< Regulator OPA gain/phase selection + ///< - @b FALSE: disable + ///< - @b TRUE: enable + BOOL pull_down; ///< Regulator output pull down control + ///< - @b FALSE: none + ///< - @b TRUE: pull down enable + BOOL regulator_en; ///< Regulator enable + ///< - @b FALSE: disable + ///< - @b TRUE: enable + PAD_VAD vad; ///< Pad VAD of PAD_POWERID_ADC when PAD_PAD_VAD = 1 +} PAD_POWER_STRUCT; + + + + + + + + +// Backward compatible usages +#define PAD_PIN_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO23 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO24 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO25 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO26 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO27 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO28 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO29 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO30 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO31 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO32 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_CGPIO33 PAD_PIN_NOT_EXIST // For backward compatible +#define PAD_DS_PGPIO39 PAD_PIN_NOT_EXIST // For backward compatible + + +/* + Exporting APIs +*/ + +extern ER pad_setPullUpDown(UINT32 pin, PAD_PULL pulltype); +extern ER pad_setDrivingSink(UINT32 name, PAD_DRIVINGSINK driving); +//@} + + + +//@} + +#endif diff --git a/loader/Include/Driver/regdef.h b/loader/Include/Driver/regdef.h new file mode 100755 index 000000000..93a938095 --- /dev/null +++ b/loader/Include/Driver/regdef.h @@ -0,0 +1,199 @@ +/* + * MIPS register definitions, originally from: + * + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License, Version 2. See the file "COPYING" in the main directory of this + * archive for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +/* + * Symbolic register names for 32 bit ABI + */ +# define Mode_USR 0x10 /* M[4:0] = 01010 */ +# define Mode_FIQ 0x11 /* M[4:0] = 10001 */ +# define Mode_IRQ 0x12 /* M[4:0] = 10010 */ +# define Mode_SVC 0x13 /* M[4:0] = 10011 */ +# define Mode_ABT 0x17 /* M[4:0] = 10111 */ +# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */ +# define Mode_SYS 0x1F /* M[4:0] = 11111 */ +# define Mode_MSK 0x1F /* M[4:0] = 11111 */ +# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */ +# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */ + +/* + ************************************************************************ + * Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |W|W|R|W|NumSets |Associativity |L | + * |T|B|A|A| | |S | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSIDR_WT 31 +#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */ +#define S_CCSIDR_WB 30 +#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */ +#define S_CCSIDR_RA 29 +#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */ +#define S_CCSIDR_WA 28 +#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */ +#define S_CCSIDR_SETS 13 +#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */ +#define S_CCSIDR_A 3 +#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */ +#define S_CCSIDR_LS 0 +#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */ + +/* + ************************************************************************ + * Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |0|0|LoUU |LoC |LoUIS|CT7 |CT6 |CT5 |CT4 |CT3 |CT2 |CT1 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CLIDR_LoUU 27 +#define M_CLIDR_LoUU (0x7 << S_CLIDR_LoUU) +#define S_CLIDR_LoC 24 +#define M_CLIDR_LoC (0x7 << S_CLIDR_LoC) /* Cache cohernecy level */ +#define S_CLIDR_LoUIS 21 +#define M_CLIDR_LoUIS (0x7 << S_CLIDR_LoUIS) +#define S_CLIDR_Ctype7 18 +#define M_CLIDR_Ctype7 (0x7 << S_CLIDR_Ctype7) /* Cache type of level 7 cache */ +#define S_CLIDR_Ctype6 15 +#define M_CLIDR_Ctype6 (0x7 << S_CLIDR_Ctype6) /* Cache type of level 6 cache */ +#define S_CLIDR_Ctype5 12 +#define M_CLIDR_Ctype5 (0x7 << S_CLIDR_Ctype5) /* Cache type of level 5 cache */ +#define S_CLIDR_Ctype4 9 +#define M_CLIDR_Ctype4 (0x7 << S_CLIDR_Ctype4) /* Cache type of level 4 cache */ +#define S_CLIDR_Ctype3 6 +#define M_CLIDR_Ctype3 (0x7 << S_CLIDR_Ctype3) /* Cache type of level 3 cache */ +#define S_CLIDR_Ctype2 3 +#define M_CLIDR_Ctype2 (0x7 << S_CLIDR_Ctype2) /* Cache type of level 2 cache */ +#define S_CLIDR_Ctype1 0 +#define M_CLIDR_Ctype1 (0x7 << S_CLIDR_Ctype1) /* Cache type of level 1 cache */ + +#define K_CLIDR_Ctype_NO 0 /* No cache */ +#define K_CLIDR_Ctype_IC 1 /* Instruction cache only */ +#define K_CLIDR_Ctype_DC 2 /* Data cache only */ +#define K_CLIDR_Ctype_ID 3 /* Seperate instruction and data caches, Harvard cache */ +#define K_CLIDR_Ctype_U 4 /* Unified cache, von Neumann cacge */ + +/* + ************************************************************************ + * Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved |Level|I| + * | | |n| + * | | |D| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_CCSELR_Level 1 +#define M_CCSELR_Level (0x7 << S_CCSELR_Level) /* Cache level */ +#define S_CCSELR_InD 0 +#define M_CCSELR_InD (0x1 << S_CCSELR_InD) /* I$ or D$ */ + +/* + ************************************************************************ + * System Control Register, SCTLR (cp15, 0, c1, c0, 0) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M| + * | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | | + * | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | | + * | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_SCTLR_TE 30 +#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */ +#define S_SCTLR_AFE 29 +#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */ +#define S_SCTLR_TRE 28 +#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */ +#define S_SCTLR_NMFI 27 +#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */ +#define S_SCTLR_EE 25 +#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */ +#define S_SCTLR_VE 24 +#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */ +#define S_SCTLR_FI 21 +#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */ +#define S_SCTLR_UWXN 20 +#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */ +#define S_SCTLR_WXN 19 +#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN) +#define S_SCTLR_HA 17 +#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */ +#define S_SCTLR_RR 14 +#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */ +#define S_SCTLR_V 13 +#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */ +#define S_SCTLR_I 12 +#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */ +#define S_SCTLR_Z 11 +#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */ +#define S_SCTLR_SW 10 +#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */ +#define S_SCTLR_CP15BEN 5 +#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */ +#define S_SCTLR_C 2 +#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */ +#define S_SCTLR_A 1 +#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */ +#define S_SCTLR_M 0 +#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */ + +/************************************************************************ + * Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F| + * | |a|l|X|M| | |1|2|W| + * | |r|l|C|P| |f| | | | + * | | |o|L| | |l|p|p| | + * | |o|c| | | | |r|r| | + * | |n| | | | |z|e|e| | + * | | |o| | | |e|f|f| | + * | | |n| | | |r| | | | + * | | |e| | | |o|e|e| | + * | | | | | | |s|n|n| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define S_ACTLR_PAR_ON 9 +#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */ +#define S_ACTLR_ALLOC_ONE 8 +#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */ +#define S_ACTLR_EXCL 7 +#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */ +#define S_ACTLR_SMP 6 +#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */ +#define S_ACTLR_W_FL_ZEROS 3 +#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */ +#define S_ACTLR_L1_PERF_EN 2 +#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */ +#define S_ACTLR_L2_PERF_EN 1 +#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */ +#define S_ACTLR_FW 0 +#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */ + + diff --git a/loader/Include/IOReg.h b/loader/Include/IOReg.h new file mode 100755 index 000000000..7f4e2f318 --- /dev/null +++ b/loader/Include/IOReg.h @@ -0,0 +1,190 @@ +/** + I/O Access header file + + I/O Access header file + + @file IOReg.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef __IO_REG_H +#define __IO_REG_H + +#include "constant.h" +#include "CMacro.h" +#include "Memory.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ + +/** + @name Input 8bit IO register + + Input 8bit IO register + + @param[in] x I/O address + + @return register value +*/ +//@{ +#define INREG8(x) (*((volatile UINT8*)(x))) ///< Read 8bits IO register +//@} + +/** + @name Output 8bit IO register + + Output to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG8(x, y) (*((volatile UINT8*)(x)) = (y)) ///< Write 8bits IO register +//@} + +/** + @name Set bits to 8bit IO register + + Set bits to 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG8(x, y) OUTREG8((x), INREG8(x) | (y)) ///< Set 8bits IO register +//@} + +/** + @name Clear bits from 8bit IO register + + Clear bits from 8bit IO register + + @param[in] x I/O address + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG8(x, y) OUTREG8((x), INREG8(x) & ~(y)) ///< Clear 8bits IO register +//@} + +/** + @name Input 16bit IO register + + Input 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + + @return register value +*/ +//@{ +#define INREG16(x) (*((volatile UINT16*)(x))) ///< Read 16bits IO register +//@} + +/** + @name Output 16bit IO register + + Output to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG16(x, y) (*((volatile UINT16*)(x)) = (y)) ///< Write 16bits IO register +//@} + +/** + @name Set bits to 16bit IO register + + Set bits to 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG16(x, y) OUTREG16((x), INREG16(x) | (y)) ///< Set 16bits IO register +//@} + +/** + @name Clear bits from 16bit IO register + + Clear bits from 16bit IO register + + @param[in] x I/O address (should be 2 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG16(x, y) OUTREG16((x), INREG16(x) & ~(y)) ///< Clear 16bits IO register +//@} + +/** + @name Input 32bit IO register + + Input 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + + @return register value +*/ +//@{ +#define INREG32(x) (*((volatile UINT32*)(x))) ///< Read 32bits IO register +//@} + +/** + @name Output 32bit IO register + + Output to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be output + + @return void +*/ +//@{ +#define OUTREG32(x, y) (*((volatile UINT32*)(x)) = (y)) ///< Write 32bits IO register +//@} + +/** + @name Set bits to 32bit IO register + + Set bits to 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be set. y will be ORed to this address + + @return register value +*/ +//@{ +#define SETREG32(x, y) OUTREG32((x), INREG32(x) | (y)) ///< Set 32bits IO register +//@} + +/** + @name Clear bits from 32bit IO register + + Clear bits from 32bit IO register + + @param[in] x I/O address (should be 4 bytes alignment) + @param[in] y Value to be clear. ~(y) will be ANDed to this address + + @return register value +*/ +//@{ +#define CLRREG32(x, y) OUTREG32((x), INREG32(x) & ~(y)) ///< Clear 32bits IO register +//@} + +//@} + +#endif // __IO_REG_H diff --git a/loader/Include/SMacro.h b/loader/Include/SMacro.h new file mode 100755 index 000000000..372ea3898 --- /dev/null +++ b/loader/Include/SMacro.h @@ -0,0 +1,129 @@ +; Global vars for arg parsing + + GBLS _arg0 + GBLS _arg1 + +; _spaces_remove +; remove start and end spaces from global variable wstring + + MACRO + _spaces_remove $wstring + WHILE ( ("*" :CC: $wstring) :RIGHT: 1 = " ") +$wstring SETS ($wstring :LEFT: (:LEN: $wstring - 1)) + WEND + WHILE ( ($wstring :CC: "*") :LEFT: 1 = " ") +$wstring SETS ($wstring :RIGHT: (:LEN: $wstring - 1)) + WEND + MEND + +; _lbracket_remove +; Attempt to remove a single left bracket - error if not there + + MACRO + _lbracket_remove $s + ASSERT $s:LEFT:1 = "(" +$s SETS $s:RIGHT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _rbracket_remove +; Attempt to remove a single right bracket - error if not there +; then removes excess spaces + + MACRO + _rbracket_remove $s + ASSERT $s:RIGHT:1 = ")" +$s SETS $s:LEFT:(:LEN:$s-1) + _spaces_remove $s + MEND + +; _comment_remove +; Remove any comment from line end and then strip any spaces + + MACRO + _comment_remove $s + _spaces_remove $s + IF (("**":CC:$s):RIGHT:2) = "*/" + WHILE ($s:RIGHT:2) <> "/*" +$s SETS $s:LEFT:(:LEN:$s-1) + WEND +$s SETS $s:LEFT:(:LEN:$s-2) + _spaces_remove $s + ENDIF + MEND + +; _arg_remove +; Pull an argument from the front of a spaces stripped string + + MACRO + _arg_remove $s,$arg + LCLA _arglen + LCLL _ok +_arglen SETA 0 +_ok SETL {TRUE} + WHILE _ok + IF _arglen>=:LEN:$s +_ok SETL {FALSE} ; break if used up input string + ELSE +$arg SETS ($s:LEFT:(_arglen+1)):RIGHT:1 ; next character + IF $arg=" " +_ok SETL {FALSE} + ELSE +_arglen SETA _arglen+1 + ENDIF + ENDIF + WEND +$arg SETS $s:LEFT:_arglen +$s SETS $s:RIGHT:(:LEN:$s-_arglen) + _spaces_remove $s + MEND + +; ifndef +; Purpose: Allow #ifndef for common C headers (Just for guarded C header file) +; Syntax : #ifndef + + MACRO + ifndef $a + MEND + +; define +; Purpose: Allow #defines for common C/Assembler headers +; Syntax : #define + + MACRO +$la define $a +_arg0 SETS "$a" + ASSERT "$la"="#" ; syntax: # define fred 1 + _comment_remove _arg0 + _arg_remove _arg0,_arg1 + IF "$_arg0"<>"" +$_arg1 EQU $_arg0 + ENDIF + MEND + + +; COMMENT +; Purpose: Allow comments in common C/Assembler headers +; Syntax : COMMENT + + MACRO + COMMENT $a,$b,$c,$d,$e,$f,$g,$h + MEND + +; local labels use label$l to get a local label and LOCAL to start a new +; area + + GBLA LocalCount + GBLS l +LocalCount SETA 1 +l SETS "x$LocalCount" + +; increment local variable number + + MACRO + LOCAL +LocalCount SETA LocalCount+1 +l SETS "x$LocalCount" + MEND + + END diff --git a/loader/Include/StorageDef.h b/loader/Include/StorageDef.h new file mode 100755 index 000000000..07958d500 --- /dev/null +++ b/loader/Include/StorageDef.h @@ -0,0 +1,448 @@ +/** + Storage module driver. + + This file is the driver of storage module. + + @file StorageDef.h + @ingroup mIDrvStorage + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _STORAGE_DEF_ +#define _STORAGE_DEF_ + +#include "constant.h" + +#define _STORAGE_OBJ_ 1 +/** + @addtogroup mIDrvStorage +*/ +//@{ + +/** + @name External storage type + +*/ +//@{ +#define EXT_STORAGE_TYPE_NONE (0) +#define EXT_STORAGE_TYPE_SDIO1 (1) +#define EXT_STORAGE_TYPE_SDIO2 (2) +#define EXT_STORAGE_TYPE_USB (3) +#define EXT_STORAGE_TYPE_ETH (4) +//*} + +/** + @name SPI Quad read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_QUAD_NONE 0 ///< Not support +#define SPI_QUAD_TYPE1 1 ///< Support quad read, QE(Quad Enable) bit is in Status Reigster[bit 6] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE2 2 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. +#define SPI_QUAD_TYPE3 3 ///< Support quad read, QE(Quad Enable) NOT exist and 0x6B command requires 8 dummy clocks +#define SPI_QUAD_TYPE4 4 ///< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0x6B command requires 8 dummy clocks. + ///< But QE should be modified by 0x31 command +//@} + + +/** + @name SPI RDCR read type + + @note for SPI_IDENTIFY +*/ +//@{ +#define SPI_RDCR_NONE 0 ///< Not support +#define SPI_RDCR_TYPE1 1 ///< Support RDCR(0x15) bit[7..6] need config as 0x3 + +//@} + +/** + SPI flash identify descriptor + + @note For STRG_IDENTIFY_CB +*/ +typedef struct +{ + BOOL bSupportEWSR; ///< EWSR(0x50) command capability + ///< - @b TRUE: support EWSR command + ///< - @b FALSE: NOT support EWSR command + BOOL bSupportAAI; ///< AAI program(0xAD) command capability + ///< - @b TRUE: ONLY support AAI program command + ///< - @b FALSE: NOT support AAI program command, but support page program command + BOOL bDualRead; ///< Dual read (0x3B) command capability + ///< - @b TRUE: support dual read comand. (Command value should be 0x3B.) + ///< - @b FALSE: NOT support dual read command + UINT32 uiQuadReadType; ///< Quad read type capability. (ONLY support quad command 0x6B) + ///< - @b SPI_QUAD_NONE: NOT support quad read command + ///< - @b SPI_QUAD_TYPE1: Support quad read command, QE in Status Register bit 6 + ///< - @b SPI_QUAD_TYPE2: Support quad read command, QE in Status Register bit 9 + ///< - @b SPI_QUAD_TYPE3: Support quad read command, QE NOT exist + ///< - @b SPI_QUAD_TYPE4: Support quad read command, QE in Status Register bit 9 (but need 0x31 command) + UINT32 uiFlashSize; ///< Flash total byte size. (unit: byte) +} SPI_IDENTIFY, *PSPI_IDENTIFY; + +/** + @name Storage Access CallBack + + Storage Access CallBack Prototype + + @return void +*/ +//@{ +typedef void (*STRG_ACCESS_CB)(void); ///< Storage access call back prototype +//@} + +/** + @name Storage Identify CallBack + + Storage Identify CallBack Prototype + + @param[in] UINT32 uiMfgID (JEDEC) manufacturer ID read from spi flash + @param[in] UINT32 uiTypeID (JEDEC) type ID read from spi flash + @param[in] UINT32 uiCapacityID (JEDEC) capacity ID read from spi flash + @param[out] PSPI_IDENTIFY flash identification returned to spi flash driver + + @return + - @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information + - @b FALSE: input ID is NOT supported/identified by call back +*/ +//@{ +typedef BOOL (*STRG_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPI_IDENTIFY); ///< Storage identify call back prototype +//@} + +/** + @name Storage return value + + @note for flash_open(), flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define E_OK 0 ///< Success +#define E_NAND_IDENTIFY_ERR -1 ///< Read NAND ID (information) error +#define E_NAND_INSUFFICINET_BLK -2 ///< Bad block is too much to write data +#define E_NAND_BLK_NOT_FOUND -3 ///< Logic block number not found in physical block +#define E_NAND_WRITE_PAGEDATA_ERR -4 ///< Logic block number not found in physical block +#define E_NAND_ERASEE_BLK_ERR -5 ///< NAND erase block error +#define E_NAND_READ_PAGE_ERR -6 ///< NAND read page data error +#define E_NAND_READ_BLK_ERR -7 ///< NAND read block data error +#define E_NAND_ID_NOT_SUPPORT -8 ///< Not support NAND ID +#define E_IDENTIFY_ERR -9 ///< SPI IDENTIFY error +#define E_SYS -10 ///< System Error +#define E_NAND_ALIGN_ERR -11 ///< Not block alignment +#define E_NAND_BOUNDARY_ERR -12 ///< boundary < write buffer +#define E_OK_TABLE_FOUND 1 ///< Success & NAND table find +#define E_OK_TABLE_NOT_FOUND 2 ///< Success & NAND table not find +//@} + +/** + @name Internal Storage Update Region + + @note for flash_readSectors(), and flash_writeSectors() +*/ +//@{ +#define NAND_RW_LOADER 0 ///< Update Region is Loader (Update size is assumed 16 KB) +#define NAND_RW_RESERVED 1 ///< Update Region is reserved area (Update size is assumed 16 KB) +#define NAND_RW_FIRMWARE 2 ///< Update Region is FW (Update size is variable) +#define NAND_RW_FIRMWARE_2 3 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_3 4 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_4 5 ///< Update Region is FW from 2-5(Update size is variable) +#define NAND_RW_FIRMWARE_5 6 ///< Update Region is FW from 2-5(Update size is variable) +//@} + +/** + @name Internal Storage Configuration ID + + @note for flash_setConfig() +*/ +//@{ +#define FLASH_CFG_ID_NONE 0 +#define FLASH_CFG_ID_SPI_SUPPORT_4BITS 1 ///< Enable your project to support 4 bit SPI flash. ONLY enable when you ENSURE SPI_D0~SPI_D3 are connected to SPI flash in your PCB!!! +#define FLASH_CFG_ID_EMMC_SUPPORT_8BITS 2 ///< Enable your project to support 8 bit EMMC. ONLY enable when you ENSURE EMMC_D0~SPI_D7 are connected to EMMC flash in your PCB!!! +#define FLASH_CFG_ID_CS_SELECT 3 ///< Select this flash (nand/nor) is connected with CS0 or CS1 +#define FLASH_CFG_ID_SPI_IDENTIFY_CB 4 ///< Install flash identify call back +//@} + +#if (_STORAGE_OBJ_== 1) + + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 + +/** + @name New storage object interface + + For new version storage device driver +*/ +//@{ +typedef struct { + INT32(*flash_open)(void); ///< Flash Open + void(*flash_close)(void); ///< Flash Close + INT32(*flash_readSectors)(UINT32, UINT32, UINT8 *,UINT32); ///< Flash Read Sector + INT32(*flash_writeSectors)(UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector + INT32(*flash_writePartition)(UINT32, UINT32, UINT32, UINT8 *, UINT32); ///< Flash Write Sector, and remain space need erase + UINT32(*flash_getBlockSize)(void); ///< Flash Get Block Size + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); + INT32(*flash_get_spare_data)(UINT32, UINT32 *); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +extern PSTORAGE_OBJ emmc_get_storage_object(void); +extern PSTORAGE_OBJ nand_get_storage_object(void); +extern PSTORAGE_OBJ nor_get_storage_object(void); + +//@} +#else +#define FLASH_OPEN(m) flash_open() +#define FLASH_CLOSE(m) flash_close() +#define FLASH_READSECTOR(m, n, o, x, y) flash_readSectors(n,o,x,y) ///< Flash Read Sector +#define FLASH_WRITESECTOR(m, n, o, x, y) flash_writeSectors(n,o,x,y) ///< Flash Write Sector +#define FLASH_GETBLKSIZE(m) flash_getBlockSize() + + void(*flash_setReservedBadBlockNumber)(UINT32); ///< Flash Set Reserved Bad Block Number + void(*flash_setReservedAreaMaxBlockNumber)(UINT32); ///< Flash Set Reserved Area Block Number + UINT64(*flash_getTotalSize)(void); + void(*flash_installAccessCB)(STRG_ACCESS_CB); + void(*flash_installIdentifyCB)(STRG_IDENTIFY_CB); + void(*flash_setFrequency)(UINT32); + INT32(*flash_setConfig)(UINT32, UINT32); +} STORAGE_OBJ, *PSTORAGE_OBJ; + +/** + Flash Open + + This function will initialize internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return + - @b E_OK: open success + - @b E_IDENTIFY_ERR: identify fail (SPI path) + - @b E_NAND_IDENTIFY_ERR: identify fail (NAND path) + - @b E_NAND_ID_NOT_SUPPORT: not supported NAND flash +*/ +extern INT32 flash_open(void); +/** + Flash Close + + This function will close internal flash driver + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return void +*/ +extern void flash_close(void); + +/** + Flash Read Sector + + This function will read data from internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this read operation (unit: flash block) + @param[in] length Length of read operation (unit: byte) + @param[out] buffer Pointer to DRAM buffer to receive read data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_READ_BLK_ERR: NAND access block error + - @b E_NAND_READ_PAGE_ERR: NAND access page error +*/ +extern INT32 flash_readSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Write Sector + + This function will write data to internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] startblk Start block of this write operation (unit: flash block) + @param[in] length Length of write operation (unit: byte) + @param[in] buffer Pointer to DRAM buffer of written data (word alignment) + @param[in] updateType Operation Access Region + - @b NAND_RW_LOADER: loader region + - @b NAND_RW_RESERVED: reserved area + - @b NAND_RW_FIRMWARE: f/w region + + @return + - @b E_OK: read success + - @b E_NAND_BLK_NOT_FOUND: can not find available physical block + - @b E_NAND_ERASEE_BLK_ERR: erase block error + - @b E_NAND_WRITE_PAGEDATA_ERR: page program error + - @b E_NAND_INSUFFICINET_BLK: insufficient good block +*/ +extern INT32 flash_writeSectors(UINT32 startblk, UINT32 length, UINT8 * buffer, UINT32 updateType); + +/** + Flash Get Block Size + + This function will return block size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return block size (unit: byte) +*/ +extern UINT32 flash_getBlockSize(void); + +/** + Flash Set Reserved Bad Block Number + + This function will set block count reserved to do bad block replacement + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] badBlkNum reserved bad block count (unit: block) + + @return void +*/ +extern void flash_setReservedBadBlockNumber(UINT32 badBlkNum); + +//#NT#2010/04/20#Steven Wang -begin +//#NT#Autumn reserved area from 2 ~ 23 +/** + Flash Set Reserved Area Block Number + + This function will set reserved area max block count + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] RsvMaxBlkNum max reserved area block count (unit: block) + + @return void +*/ +extern void flash_setReservedAreaMaxBlockNumber(UINT32 RsvMaxBlkNum); +//#NT#2010/04/20#Steven Wang -end + +/** + Flash Get Total Size + + This function will return total size of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @return total size (unit: byte) +*/ +extern UINT64 flash_getTotalSize(void); + +/** + Install Flash Access CallBack + + This function will install access callback. + The installed callback will be invoked when one block/page is programmed + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @param[in] accessCB installed callback + + @return void +*/ +extern void flash_installAccessCB(STRG_ACCESS_CB accessCB); + +/** + Install Flash Identify CallBack + + This function will install identification callback. + The installed callback will be invoked when spi flash driver is opened. + + @note NAND driver will NOT invoke the installed call back + + @param[in] identifyCB installed callback + + @return void +*/ +extern void flash_installIdentifyCB(STRG_IDENTIFY_CB identifyCB); + +/** + Flash Set Bus Frequency + + This function will set operating frequency of attached internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiFreq Operating frequency (unit: MHz) + + @return void +*/ +extern void flash_setFrequency(UINT32 uiFreq); + +/** + Flash Set Configuration + + This function will set specific configuration for internal flash + + @note Internal flash is selected by STORAGEINT in MakeConfig.txt + + @param[in] uiConfigId Configuration ID, can be: + - @b FLASH_CFG_ID_SPI_SUPPORT_4BITS: configure to support 4 bit SPI flash + @param[in] uiContext Configuration context for uiConfigId + When uiConfigId == FLASH_CFG_ID_SPI_SUPPORT_4BITS: + - @b TRUE: use 4 bit read when attached SPI flash support 4 bit read + - @b FALSE: won't use 4 bit read + + @return + - @b E_OK: success + - @b Else: fail +*/ +extern INT32 flash_setConfig(UINT32 uiConfigId, UINT32 uiContext); +#endif +// External storage public API ( SDIO/MS/xD ) +/** + Open card driver + + This function will initialize card driver and register it to file system + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return + - @b TRUE: open success + - @b FALSE: open fail +*/ +extern INT32 card_open(void); + +/** + Close card driver + + This function will close card driver + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ +extern void card_close(void); + +/** + Get card type + + This function is used to get card storage type + + @note card is selected by STORAGEEXT in MakeConfig.txt + + @return void +*/ + +extern UINT32 card_get_type(void); + +//@} + +extern void USBOTGReset(void); +//extern INT32 USB3Download(void); +extern INT32 USBDownload(void); +extern void USBSetResult(UINT32 uiResult); +extern INT32 USBStateMachine(void); +#endif diff --git a/loader/Include/Type.h b/loader/Include/Type.h new file mode 100755 index 000000000..74a00059e --- /dev/null +++ b/loader/Include/Type.h @@ -0,0 +1,9 @@ +#ifndef __TYPE_H +#define __TYPE_H + +#include +//#include + +#define _ALIGNED(x) __attribute__((aligned(x))) + +#endif // __TYPE_H diff --git a/loader/Include/constant.h b/loader/Include/constant.h new file mode 100755 index 000000000..2bc267c5e --- /dev/null +++ b/loader/Include/constant.h @@ -0,0 +1,115 @@ +#ifndef _CONSTANT_H +#define _CONSTANT_H + +//Size MNEMONIC + +#define SZ_1 (1 << 0) /* 0x00000001 */ +#define SZ_2 (1 << 1) /* 0x00000002 */ +#define SZ_4 (1 << 2) /* 0x00000004 */ +#define SZ_8 (1 << 3) /* 0x00000008 */ +#define SZ_16 (1 << 4) /* 0x00000010 */ +#define SZ_32 (1 << 5) /* 0x00000020 */ +#define SZ_64 (1 << 6) /* 0x00000040 */ +#define SZ_128 (1 << 7) /* 0x00000080 */ +#define SZ_256 (1 << 8) /* 0x00000100 */ +#define SZ_512 (1 << 9) /* 0x00000200 */ + +#define SZ_1K (1 << 10) /* 0x00000400 */ +#define SZ_2K (1 << 11) /* 0x00000800 */ +#define SZ_4K (1 << 12) /* 0x00001000 */ +#define SZ_8K (1 << 13) /* 0x00002000 */ +#define SZ_16K (1 << 14) /* 0x00004000 */ +#define SZ_32K (1 << 15) /* 0x00008000 */ +#define SZ_64K (1 << 16) /* 0x00010000 */ +#define SZ_128K (1 << 17) /* 0x00020000 */ +#define SZ_256K (1 << 18) /* 0x00040000 */ +#define SZ_512K (1 << 19) /* 0x00080000 */ + +#define SZ_1M (1 << 20) /* 0x00100000 */ +#define SZ_2M (1 << 21) /* 0x00200000 */ +#define SZ_4M (1 << 22) /* 0x00400000 */ +#define SZ_8M (1 << 23) /* 0x00800000 */ +#define SZ_16M (1 << 24) /* 0x01000000 */ +#define SZ_32M (1 << 25) /* 0x02000000 */ +#define SZ_64M (1 << 26) /* 0x04000000 */ +#define SZ_128M (1 << 27) /* 0x08000000 */ +#define SZ_256M (1 << 28) /* 0x10000000 */ +#define SZ_512M (1 << 29) /* 0x20000000 */ + +#define SZ_1G (1 << 30) /* 0x40000000 */ +#define SZ_2G (1 << 31) /* 0x80000000 */ + +#define SZ_30M (SZ_32M - SZ_2M) + +// ASCII code + +#define CR 0x0D +#define LF 0x0A +#define BS 0x08 +#define ESC 27 + +// Boolean constant definition + +#if 0 +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ON +#define ON 1 +#endif + +#ifndef OFF +#define OFF 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef DISK_FULL +#define DISK_FULL (-1) +#endif + +// type declaration + +typedef int BOOLEAN; +typedef unsigned long long UINT64; +typedef long long INT64; +typedef unsigned long UINT32; +typedef unsigned long INT32U; +typedef unsigned INT32S; +typedef unsigned char INT8U; +typedef long INT32; +typedef unsigned short UINT16; +typedef short INT16; +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int uint; +typedef unsigned short ushort; +typedef unsigned char uchar; +typedef unsigned int UINT; +typedef int INT; + +typedef enum {FALSE, TRUE} BOOL; + +// error codes +typedef long ER; + +#endif diff --git a/loader/Include/ctype.h b/loader/Include/ctype.h new file mode 100755 index 000000000..dbbc7cf7d --- /dev/null +++ b/loader/Include/ctype.h @@ -0,0 +1,36 @@ + + +#ifndef NVT_CTYPES_H__ +#define NVT_CTYPES_H__ + + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + + +#endif diff --git a/loader/Include/debug.h b/loader/Include/debug.h new file mode 100755 index 000000000..7a76973d4 --- /dev/null +++ b/loader/Include/debug.h @@ -0,0 +1,31 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_DEBUG_H__ +#define __NVT_DEBUG_H__ + +#include "fuart.h" +/** \addtogroup mISYSClib */ +//@{ + +extern void debug_set_console(CONSOLE_OBJ *p_obj); +extern void debug_err(char *str); +extern void debug_err_var(char *str, int var); +extern void debug_msg(char *str) __attribute__ ((section (".part1"))); +extern void debug_msg_var(char *str, int var) __attribute__ ((section (".part1"))); +extern void debug_dump_addr(UINT32 addr, UINT32 size); + + +//@} + +#endif + diff --git a/loader/Include/fat.h b/loader/Include/fat.h new file mode 100755 index 000000000..f1082903e --- /dev/null +++ b/loader/Include/fat.h @@ -0,0 +1,48 @@ +/** + File system library + + This file is the library of file system + + @file fat.h + @ingroup mISYSFile + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _FAT_H +#define _FAT_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @addtogroup mISYSFile +*/ +//@{ + +#define FAT_READ_TOTAL_FILE_LENGTH 0 + +typedef void (*TOGGLE_LED)(UINT8 WithCount); + +extern BOOL fat_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern UINT32 fat_getPartitionCount(void); +extern BOOL fat_mountPartition(UINT32 partition_id); +extern void fat_closeFAT(void); +extern BOOL fat_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern UINT32 fat_getRootfileSize(void); +extern void fat_close_rootfile(void); +extern void fat_regToggleLED(TOGGLE_LED pToggleLED); +extern void fat_installAccessCB(STRG_ACCESS_CB accessCB); + +// For SD registration +extern BOOL fat_internal_initFAT(UINT32 uiBuf, UINT32 uiSize); +extern BOOL fat_internal_open_rootfile(UINT8 *pfilename); +extern UINT32 fat_internal_read_rootfile(UINT8 *pbuf, UINT32 uiRdLen); +extern void fat_internal_close_rootfile(void); + +//@} + +#endif + diff --git a/loader/Include/fdt/compiler.h b/loader/Include/fdt/compiler.h new file mode 100755 index 000000000..7fa9b3831 --- /dev/null +++ b/loader/Include/fdt/compiler.h @@ -0,0 +1,56 @@ +/* + * Keep all the ugly #ifdef for system stuff here + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef NULL +#define NULL 0 +#endif + +#if 0 +#define uswap_16(x) (x) +#define uswap_32(x) (x) +#define _uswap_64(x, sfx) (x) +#else +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) +#define uswap_32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) +#define _uswap_64(x, sfx) \ + ((((x) & 0xff00000000000000##sfx) >> 56) | \ + (((x) & 0x00ff000000000000##sfx) >> 40) | \ + (((x) & 0x0000ff0000000000##sfx) >> 24) | \ + (((x) & 0x000000ff00000000##sfx) >> 8) | \ + (((x) & 0x00000000ff000000##sfx) << 8) | \ + (((x) & 0x0000000000ff0000##sfx) << 24) | \ + (((x) & 0x000000000000ff00##sfx) << 40) | \ + (((x) & 0x00000000000000ff##sfx) << 56)) +#endif +#if defined(__GNUC__) +#define uswap_64(x) _uswap_64(x, ull) +#else +#define uswap_64(x) _uswap_64(x, ) +#endif +#define cpu_to_le16(x) (x) +#define cpu_to_le32(x) (x) +#define cpu_to_le64(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) +#define cpu_to_be16(x) uswap_16(x) +#define cpu_to_be32(x) uswap_32(x) +#define cpu_to_be64(x) uswap_64(x) +#define be16_to_cpu(x) uswap_16(x) +#define be32_to_cpu(x) uswap_32(x) +#define be64_to_cpu(x) uswap_64(x) + +/* Type for `void *' pointers. */ +typedef unsigned long int uintptr_t; + +#endif diff --git a/loader/Include/fdt/fdt.h b/loader/Include/fdt/fdt.h new file mode 100755 index 000000000..0187749f1 --- /dev/null +++ b/loader/Include/fdt/fdt.h @@ -0,0 +1,111 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/loader/Include/fdt/libfdt.h b/loader/Include/fdt/libfdt.h new file mode 100755 index 000000000..42c5e9d0e --- /dev/null +++ b/loader/Include/fdt/libfdt.h @@ -0,0 +1,1580 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "libfdt_env.h" +#include "fdt.h" + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +#define FDT_ERR_MAX 13 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header*)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic); +__fdt_set_hdr(totalsize); +__fdt_set_hdr(off_dt_struct); +__fdt_set_hdr(off_dt_strings); +__fdt_set_hdr(off_mem_rsvmap); +__fdt_set_hdr(version); +__fdt_set_hdr(last_comp_version); +__fdt_set_hdr(boot_cpuid_phys); +__fdt_set_hdr(size_dt_strings); +__fdt_set_hdr(size_dt_struct); +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +int fdt_check_full(const void *fdt, size_t bufsize); + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property_namelen(), but only examine the first + * namelen characters of name for matching the property name. + */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias to look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * ... other code here ... + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +struct fdt_region { + int offset; + int size; +}; + +/** + * fdt_find_regions() - find regions in device tree + * + * Given a list of nodes to include and properties to exclude, find + * the regions of the device tree which describe those included parts. + * + * The intent is to get a list of regions which will be invariant provided + * those parts are invariant. For example, if you request a list of regions + * for all nodes but exclude the property "data", then you will get the + * same region contents regardless of any change to "data" properties. + * + * This function can be used to produce a byte-stream to send to a hashing + * function to verify that critical parts of the FDT have not changed. + * + * Nodes which are given in 'inc' are included in the region list, as + * are the names of the immediate subnodes nodes (but not the properties + * or subnodes of those subnodes). + * + * For eaxample "/" means to include the root node, all root properties + * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter + * ensures that we capture the names of the subnodes. In a hashing situation + * it prevents the root node from changing at all Any change to non-excluded + * properties, names of subnodes or number of subnodes would be detected. + * + * When used with FITs this provides the ability to hash and sign parts of + * the FIT based on different configurations in the FIT. Then it is + * impossible to change anything about that configuration (include images + * attached to the configuration), but it may be possible to add new + * configurations, new images or new signatures within the existing + * framework. + * + * Adding new properties to a device tree may result in the string table + * being extended (if the new property names are different from those + * already added). This function can optionally include a region for + * the string table so that this can be part of the hash too. + * + * The device tree header is not included in the list. + * + * @fdt: Device tree to check + * @inc: List of node paths to included + * @inc_count: Number of node paths in list + * @exc_prop: List of properties names to exclude + * @exc_prop_count: Number of properties in exclude list + * @region: Returns list of regions + * @max_region: Maximum length of region list + * @path: Pointer to a temporary string for the function to use for + * building path names + * @path_len: Length of path, must be large enough to hold the longest + * path in the tree + * @add_string_tab: 1 to add a region for the string table + * @return number of regions in list. If this is >max_regions then the + * region array was exhausted. You should increase max_regions and try + * the call again. + */ +int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, + char * const exc_prop[], int exc_prop_count, + struct fdt_region region[], int max_regions, + char *path, int path_len, int add_string_tab); + +#endif /* _LIBFDT_H */ diff --git a/loader/Include/fdt/libfdt_env.h b/loader/Include/fdt/libfdt_env.h new file mode 100755 index 000000000..82b1621d5 --- /dev/null +++ b/loader/Include/fdt/libfdt_env.h @@ -0,0 +1,64 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H + +#include "compiler.h" + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; +typedef __s32 int32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#define __bitwise + +typedef __u16 __bitwise __le16; +typedef __u16 __bitwise __be16; +typedef __u32 __bitwise __le32; +typedef __u32 __bitwise __be32; +#if defined(__GNUC__) +typedef __u64 __bitwise __le64; +typedef __u64 __bitwise __be64; +#endif + +extern struct fdt_header *working_fdt; /* Pointer to the working fdt */ + +typedef __be16 fdt16_t; +typedef __be32 fdt32_t; +typedef __be64 fdt64_t; + +#define fdt32_to_cpu(x) be32_to_cpu(x) +#define cpu_to_fdt32(x) cpu_to_be32(x) +#define fdt64_to_cpu(x) be64_to_cpu(x) +#define cpu_to_fdt64(x) cpu_to_be64(x) + +/* adding a ramdisk needs 0x44 bytes in version 2008.10 */ +#define FDT_RAMDISK_OVERHEAD 0x80 + +#endif /* _LIBFDT_ENV_H */ diff --git a/loader/Include/fuart.h b/loader/Include/fuart.h new file mode 100755 index 000000000..d65a64b5a --- /dev/null +++ b/loader/Include/fuart.h @@ -0,0 +1,85 @@ +/** + Header file for UART + + This file is the header file for UART driver + + @file fuart.h + @ingroup mIIOUART + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + + +#ifndef _FUART_H +#define _FUART_H + +#include "constant.h" + +/** + @addtogroup mIIOUART +*/ +//@{ +#ifndef ENUM_DUMMY4WORD +#define ENUM_DUMMY4WORD(name) E_##name = 0x10000000 +#endif + +typedef enum { + CONSOLE_UART0, + CONSOLE_UART1, + + ENUM_DUMMY4WORD(UART_CONSOLE_CH) +} UART_CONSOLE_CH; + + +typedef struct _CONSOLE { + void (*hook)(void); ///< start this object + void (*putc)(char c); ///< console input funciton pointer + unsigned char (*getc)(void); ///< console output function point +} CONSOLE_OBJ, *PCONSOLE_OBJ; + + + +/** + @name Put system UART string + + Print string to UART + + @param[in] m printed string +*/ +//@{ +#define uart_putSystemUARTStr(m) fLib_PutSerialStr(m) ///< Print string MACRO +//@} + +/** + @name Put system UART character + + Print character to UART + + @param[in] m printed character +*/ +//@{ +#define uart_putSystemUARTChar(m) fLib_PutSerialChar(m) ///< Print character MACRO +//@} + +extern void fLib_PutSerialChar(char Ch) __attribute__ ((section (".part1"))); +extern void fLib_PutSerialStr(char *Str) __attribute__ ((section (".part1"))); +extern void uart_openSystemUART(void); +extern void uart_openSystemUART2(void); + +extern void uart_getChar_polling(char * c); +extern void uart_chkChar(char * c); +extern void uart_getStr_polling(char * c); +extern void uart_getBinary(char *pcString, UINT32 BufferLen); + +void serial_init(void); +unsigned char serial_getc(void); +void serial_putc(char c); +void serial2_init(void); +unsigned char serial2_getc(void); +void serial2_putc(char c); +PCONSOLE_OBJ get_uart_object(UART_CONSOLE_CH uart_ch); + +//@} + +#endif diff --git a/loader/Include/gic.h b/loader/Include/gic.h new file mode 100755 index 000000000..e916c2c65 --- /dev/null +++ b/loader/Include/gic.h @@ -0,0 +1,195 @@ + +#ifndef _ASM_ARMV8_GIC_H_ +#define _ASM_ARMV8_GIC_H_ +//#include "FLibARM.h" +#define UART_INTID 43 + + + +#define GIC_UART_INTID (UART_INTID + 32) +#if 0 +/* + * Distributor layout + */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +/* + * CPU Interface layout + */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 +#endif + +#define MAX_SPIS 480 + +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 + +#define _GICD_ 0x1000 +#define _GICC_ 0x2000 +#define _GICH_ 0x4000 +#define _GICV_ 0x6000 + +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +/* Distributor interface definitions */ +#define GICD_CTLR _GICD_ + 0x0 +#define GICD_TYPER _GICD_ + 0x4 +#define GICD_IGROUPR _GICD_ + 0x80 +#define GICD_ISENABLER _GICD_ + 0x100 +#define GICD_ICENABLER _GICD_ + 0x180 +#define GICD_ISPENDR _GICD_ + 0x200 +#define GICD_ICPENDR _GICD_ + 0x280 +#define GICD_ISACTIVER _GICD_ + 0x300 +#define GICD_ICACTIVER _GICD_ + 0x380 +#define GICD_IPRIORITYR _GICD_ + 0x400 +#define GICD_ITARGETSR _GICD_ + 0x800 +#define GICD_ICFGR _GICD_ + 0xC00 +#define GICD_SGIR _GICD_ + 0xF00 +#define GICD_CPENDSGIR _GICD_ + 0xF10 +#define GICD_SPENDSGIR _GICD_ + 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* GICD_ICFGR bit definitions */ +#define LEVEL_SENSITIVE 0x0 +#define TRIGGER_SENSITIVE 0x1 + +/* Physical CPU Interface registers */ +#define GICC_CTLR _GICC_ + 0x0 +#define GICC_PMR _GICC_ + 0x4 +#define GICC_BPR _GICC_ + 0x8 +#define GICC_IAR _GICC_ + 0xC +#define GICC_EOIR _GICC_ + 0x10 +#define GICC_RPR _GICC_ + 0x14 +#define GICC_HPPIR _GICC_ + 0x18 +#define GICC_AHPPIR _GICC_ + 0x28 +#define GICC_IIDR _GICC_ + 0xFC +#define GICC_DIR _GICC_ + 0x1000 +#define GICC_PRIODROP _GICC_ + GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) +#define ENABLE_GRP1 (1 << 1) +#define ENABLE_GRP0 (1 << 0) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +extern void nvt_enable_irq(int number); +extern void nvt_disable_irq(int number); +extern void arm_gic_cpuif_setup(void); +extern void arm_gic_distif_setup(void); +extern void gicd_write_igroupr(UINT32 id, UINT32 val); +extern void gicd_write_ipriorityr(UINT32 id, UINT32 val); + +extern UINT32 gicc_get_IAR(void); +extern void gicc_set_EOIR(UINT32 val); + + + + +#endif /* _ASM_ARMV8_GIC_H_ */ diff --git a/loader/Include/global.h b/loader/Include/global.h new file mode 100755 index 000000000..4153ad5b3 --- /dev/null +++ b/loader/Include/global.h @@ -0,0 +1,66 @@ +/** + Global utility header file + + Global utility header file + + @file global.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _GLOBAL_H +#define _GLOBAL_H + +#include "constant.h" + +#define BOOT_SOURCE_SPI 0x00 +#define BOOT_SOURCE_CARD 0x01 +#define BOOT_SOURCE_SPI_NAND_2K 0x02 +#define BOOT_SOURCE_SPI_NAND_RS_2K 0x03 +#define BOOT_SOURCE_ETHERNET 0x04 +#define BOOT_SOURCE_USB 0x05 +#define BOOT_SOURCE_SPI_NAND_4K 0x06 +#define BOOT_SOURCE_RESERVED 0x07 +#define BOOT_SOURCE_EMMC_4BIT 0x08 +#define BOOT_SOURCE_EMMC_8BIT 0x09 +#define BOOT_SOURCE_SPI_NAND_RS_4K 0x0A +#define BOOT_SOURCE_USB_FULL 0x0B +#define BOOT_SOURCE_UART 0x0C + +#define CHIPVER_A 0x0 + +/** + @addtogroup mISYSUtil +*/ +//@{ + +extern UINT32 bitCount(UINT32 data); +extern void UTL_setDrvTmpBufferAddress(UINT32 addr); +extern UINT32 UTL_getDrvTmpBufferAddress(void); +extern char* Dec2HexStr(UINT32 data); +//extern void PrintDec2Hex(UINT32 data) __attribute__ ((section (".part1"))); +extern void rom_Dec2HexStr(UINT32 data) __attribute__ ((section (".part1"))); +#define PrintDec2Hex(m) rom_Dec2HexStr(m) +extern char* Dec2HexStr2Bytes(UINT32 data); +extern void PrintDec2HexStr2Bytes(UINT32 data) __attribute__ ((section (".part1"))); +extern UINT32 DecStr2Int(char* str); +extern BOOL UTL_canUpdateSecKey(void); +extern BOOL utl_is_sram_fw(UINT32 fw_addr); +extern void utl_test_checksum(UINT32 addr, UINT32 size); +extern void utl_dram_protect_enable(UINT32 addr, UINT32 size); +extern void utl_dram_protect_disable(void); +extern UINT32 utl_dram_protect_check(void); +extern UINT32 utl_get_bootsrc(void); +extern UINT32 utl_get_chipversion(void); + +#if (_ROM_PUBLIC_API_ == 1) +extern void rom_debug_msg(char* str); +extern void rom_debug_msg_var(char *str, int var); +extern void rom_Dec2HexStr(UINT32 data); +#endif +extern void load_dram_scan(UINT32 addr, UINT32 size) __attribute__ ((section (".dram_text"))); +extern void timer_delay(UINT32 US) __attribute__ ((section (".part1"))); + +//@} + +#endif diff --git a/loader/Include/limits.h b/loader/Include/limits.h new file mode 100755 index 000000000..20a514867 --- /dev/null +++ b/loader/Include/limits.h @@ -0,0 +1,31 @@ + + +#ifndef __NVT_LIBC_LIMITS_H +#define __NVT_LIBC_LIMITS_H + +#define CHAR_BIT 8 /* number of bits in a char */ +#define SCHAR_MIN (-128) /* minimum signed char value */ +#define SCHAR_MAX 127 /* maximum signed char value */ +#define UCHAR_MAX 0xff /* maximum unsigned char value */ + +#ifndef _CHAR_UNSIGNED +#define CHAR_MIN SCHAR_MIN /* mimimum char value */ +#define CHAR_MAX SCHAR_MAX /* maximum char value */ +#else +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#endif /* _CHAR_UNSIGNED */ + +#define MB_LEN_MAX 2 /* max. # bytes in multibyte char */ +#define SHRT_MIN (-32768) /* minimum (signed) short value */ +#define SHRT_MAX 32767 /* maximum (signed) short value */ +#define USHRT_MAX 0xffff /* maximum unsigned short value */ +#define INT_MIN (-2147483647 - 1) /* minimum (signed) int value */ +#define INT_MAX 2147483647 /* maximum (signed) int value */ +#define UINT_MAX 0xffffffff /* maximum unsigned int value */ +#define LONG_MIN (-2147483647L - 1) /* minimum (signed) long value */ +#define LONG_MAX 2147483647L /* maximum (signed) long value */ +#define ULONG_MAX 0xffffffffUL /* maximum unsigned long value */ + +#endif + diff --git a/loader/Include/loader.h b/loader/Include/loader.h new file mode 100755 index 000000000..b0f11ebbb --- /dev/null +++ b/loader/Include/loader.h @@ -0,0 +1,99 @@ +/** + Global loader header file + + Global loader header file + + @file loader.h + @ingroup mISYSUtil + @note Nothing +*/ + +#ifndef _LOADER_H +#define _LOADER_H + +#include "constant.h" +#include "StorageDef.h" + +/** + @name Special key detect CallBack + + Special key detect Prototype + + Project layer can detect special key in this callback. + If callback returns TRUE, loader will try to find files on SD card. + + @return + - @b TRUE: special key is pressed + - @b FALSE: special key is NOT pressed +*/ +//@{ +typedef BOOL (*LDR_SPECIAL_KEY_CB)(void); +//@} + +/** + @name Card detect CallBack + + Card detect Prototype + + Project layer can detect SD card existence in this callback. + If callback returns TRUE, loader will consider SD is plugged + + @return + - @b TRUE: SD exist + - @b FALSE: SD NOT exist +*/ +//@{ +typedef BOOL (*LDR_CARD_DETECT_CB)(void); +//@} +/** + @name Recovery Trigger CallBack + + Recovery trigger Prototype + + Project layer can detect if the recovery flow should started. + If callback returns TRUE, recovery flow will start. + + @return + - @b TRUE: Recovery flow is triggered. + - @b FALSE: Recovery flow is NOT triggered. +*/ +//@{ +typedef BOOL (*LDR_RECOVERY_TRIGGER_CB)(void); +//@} + +/** + @name Fastboot key detect CallBack + + Fastboot key detect Prototype + + Project layer can detect fastboot key in this callback. + If callback returns TRUE, loader will run the fastboot flow. + + @return + - @b TRUE: fastboot key is pressed + - @b FALSE: fastboot key is NOT pressed +*/ +//@{ +typedef BOOL (*LDR_FASTBOOT_KEY_CB)(void); + +typedef enum _STORAGEINT { + STORAGEINT_UNOKNOWN, + STORAGEINT_SPI_NAND, + STORAGEINT_SPI_NOR, + STORAGEINT_EMMC, +} STORAGEINT; + +extern void loader_setUpdateFwName(char* fileName); +extern void loader_setUpdateLdrName(char* fileName); +extern void loader_setRunFwName(char* fileName); +extern void loader_setRecoveryFwName(char *fileName); +extern void loader_setRecoveryPartitionID(UINT32 partition_id); +extern void loader_setVersion(UINT32 version); +extern void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj); +extern void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback); +extern void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback); +extern void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback); +extern void loader_installFastbootKeyCB(LDR_FASTBOOT_KEY_CB callback); + +#endif + diff --git a/loader/Include/lz.h b/loader/Include/lz.h new file mode 100755 index 000000000..4fcd15bbc --- /dev/null +++ b/loader/Include/lz.h @@ -0,0 +1,31 @@ +/** + Decompress library header file + + Decompress library header file + + @file lz.h + @ingroup mISYSUtil + @note Nothing +*/ +#ifndef __NVT_LZ_DEF__ +#define __NVT_LZ_DEF__ + +#include "constant.h" + +/** + @addtogroup mISYSUtil +*/ +//@{ +#if (_ROM_PUBLIC_API_ == 1) +#define LZ_Un_compress(a,b,c) rom_LZ_Uncompress(a,b,c) +extern unsigned int rom_LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize)__attribute__ ((section (".part1"))); +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize); +#else +extern unsigned int LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize)__attribute__ ((section (".part1"))); +#define LZ_Un_compress(a,b,c) LZ_Uncompress(a,b,c) +#endif +//extern void LZ_Uncompress(UINT8 *in, UINT8 *out, UINT32 insize) __attribute__ ((section (".part1"), far)); + +//@} + +#endif diff --git a/loader/Include/modelext/bin_info.h b/loader/Include/modelext/bin_info.h new file mode 100755 index 000000000..78bbdbba4 --- /dev/null +++ b/loader/Include/modelext/bin_info.h @@ -0,0 +1,191 @@ +/** + Bin File Information + + Bin file layout + + ----------------------------------------------------- + HEADINFO 0x00 ~ 0x80 = 128 bytes = 32 WORDS + ----------------------------------------------------- + + EXCEPTION_TABLE: 0x180 ~ 0x200 = 128 bytes = 32 WORDS (see exception_MIPS.s) + + ----------------------------------------------------- + + VECTOR_TABLE: 0x200 ~ 0x2f0 = 240 bytes = 60 WORDS (see isr_MIPS.s) + + ----------------------------------------------------- + + Code Info: 0x2f0 ~ 0x400 = 272 bytes = 68 WORDS (see CodeInfo_MIPS.s) + + ----------------------------------------------------- + + Code Entry: 0x400 (see Loader_MIPS.s) + + : + + PART-1 + PART-2 + PART-3 + : + PART-N + + ----------------------------------------------------- + + @file bin_info.h + @ingroup mMODELEXT + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2011. All rights reserved. +*/ +#ifndef _BINI_NFO_H +#define _BIN_INFO_H + +#define BIN_INFO_VER 0x19062115 ///< YYYY/MM/DD HH +#if UITRON_FW +#define BIN_INFO_OFFSET_RTOS 0x00000100 ///< uITRON HEADINFO.o attached to this offset +#else +#define BIN_INFO_OFFSET_RTOS 0x00000200 ///< uITRON HEADINFO.o attached to this offset +#endif +#define BIN_INFO_OFFSET_UBOOT 0x00000300 ///< uboot HEADINFO.o attached to this +#define BIN_INFO_OFFSET_NUTTX 0x00000100 ///< nuttx +#define BIN_INFO_OFFSET_TEEOS 0x00000100 ///< teeos + +//Ep: Encryption Program (CheckSum version) +//Epcrc: Encryption Program (CRC version) +//Bfc: Bin File Compress +//Ld: Loader +//Fw: Firmware + +//Head control flag for HEADINFO.BinCtrl +#define HDCF_LZCOMPRESS_EN 0x0000001 ///< BIT 0.compressed enable (0=no,1=yes) + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define BOOT_FLAG_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +//HEADINFO::Resv field definition +typedef enum _HEADINFO_RESV_IDX_{ + HEADINFO_RESV_IDX_FDT_ADDR = 0, + HEADINFO_RESV_IDX_SHM_ADDR = 1, + HEADINFO_RESV_IDX_BOOT_FLAG = 2, + HEADINFO_RESV_IDX_COUNTS = 19, +} HEADINFO_RESV_IDX; + +//HEADINFO::Resv field definition for teeos +typedef enum HEADINFO_TEEOS_RESV_IDX{ + HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR = 0, + HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR = 1, //< write by loader + HEADINFO_TEEOS_RESV_IDX_COUNTS = 19, +} HEADINFO_TEEOS_RESV_IDX; + +/** + Header information + + 0x00 ~ 0x80 = 128 bytes = 32 WORDS +*/ +typedef struct HEADINFO { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[HEADINFO_RESV_IDX_COUNTS]; + ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + ///< Resv1[HEADINFO_RESV_IDX_FDT_ADDR]: store fdt addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_SHM_ADDR]: store shm addr for rtos + ///< Resv1[HEADINFO_RESV_IDX_BOOT_FLAG]: boot flag for rtos + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK releasedate (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int ModelextAddr;///< [0x74~0x78] where modelext data is. w by Ld / u-boot + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + ///< BIT 1.Linux SMP enable (1: SMP/VOS, 0: Dual OS) + unsigned int CRCBinaryTag;///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} +HEADINFO; + +STATIC_ASSERT(sizeof(HEADINFO) == 128); + + +/** + Loader information + + 0x80 ~ 0xc0 = 64 bytes = 16 WORDS +*/ +typedef struct _LDINFO { + char LdInfo_1[16]; ///< [0x80~0x90] LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< [0x90] Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< [0x94] Ld flag (4) ----------- w by Ld + ///< BIT 0.UPDATE_FW (0=no,1=yes) + ///< BIT 1.UPDATE_LOADER (0=no,1=yes) + ///< BIT 2.BOOT_CARD (0=no,1=yes) + ///< BIT 3.BOOT_FLASH (0=no,1=yes) + ///< BIT 4.UPDATE_CAL (0=no,1=yes) + ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) + //< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) + UINT32 LdLoadSize; ///< [0x98] Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< [0x9c] Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< [0xa0] Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< [0xa4] FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< [0xa8] IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< [0xaa] Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 Resv[5]; ///< [0xac~0xc0] (4*5) ------------ reserved for project Ld +} +LDINFO; + +STATIC_ASSERT(sizeof(LDINFO) == 64); +/** + Binary file information + + 0x00 ~ 0x180 = 384 bytes = 96 WORDS +*/ +typedef struct _BININFO { + HEADINFO head; ///< 0x00 ~ 0x80 = 128 bytes = 32 WORDS, header information + LDINFO ld; ///< 0x80 ~ 0xc0 = 64 bytes = 16 WORDS, loader information + unsigned int Resv[48]; ///< 0x80 ~ 0x180 = 384 bytes = 64 WORDS, reserved information +} +BININFO; + +STATIC_ASSERT(sizeof(BININFO) == 384); + +/////////////////////////////////////////////////////////////////////////////// +//Code Info: 0x2f0 ~ 0x400 +#if UITRON_FW +#define ZI_SECTION_OFFSET (0x2f0+0x10) ///< ZI area information of starting offset //cliff +#define CODE_SECTION_OFFSET (0x2f0+0x18) ///< code section information of starting offset //cliff + +/////////////////////////////////////////////////////////////////////////////// +//Code Entry: 0x0 ~ +#define CODE_ENTRY_OFFSET (0x0) ///< code entry starting offset (660/510 is 0x400, 680 is 0x0) //cliff +#else +#define ZI_SECTION_OFFSET (0x3f0+0x10) ///< ZI area information of starting offset +#define CODE_SECTION_OFFSET (0x3f0+0x18) ///< code section information of starting offset + +#endif +/* +bfc syntex + +bfc.exe p1 p2 p3 p4 p5 p6 p7 p8 p9 + +p1: compress/decompress +p2: compress method +p3: input file name +p4: output file name +p5: partial load flag ('1' means partial load) +p6: partial load file start [locate offset of bin file] +p7: output binary file length [locate offset of bin file] +p8: partial compress flag [locate offset of bin file] +p9: NAND block size (option) + +NOTE: p6~p9 must be hex format (0x****) + +@$(BFC) c lz $(BIN_R) tmp 1 0x310 0x68 0x78 $(EMBMEM_BLK_SIZE) +*/ + +#endif + diff --git a/loader/Include/modelext/dram_partition_info.h b/loader/Include/modelext/dram_partition_info.h new file mode 100755 index 000000000..0441da45b --- /dev/null +++ b/loader/Include/modelext/dram_partition_info.h @@ -0,0 +1,55 @@ +#ifndef _DRAM_PARTITION_INFO_H +#define _DRAM_PARTITION_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +/** + DRAM Partition + + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define DRAM_PARTITION_INFO_VER 0x17032309 ///< YYYY/MM/DD HH + +typedef struct _DRAM_PARTITION { + unsigned int fourcc; ///< FourCC DRAM + unsigned int info_size; ///< sizeof(CORE_INFO) + unsigned int dram_addr; ///< whole dram starting address + unsigned int dram_size; ///< whole dram size + unsigned int rev_addr; ///< reversed starting address + unsigned int rev_size; ///< reversed size + unsigned int fdt_addr; ///< ipc starting address + unsigned int fdt_size; ///< ipc size + unsigned int linux_addr;///< linux-kernel starting address + unsigned int linux_size;///< linux-kernel size + unsigned int uboot_addr;///< u-boot starting address + unsigned int uboot_size;///< u-boot size + unsigned int rtos_addr; ///< rtos starting address + unsigned int rtos_size; ///< rtos size + unsigned int dsp1_addr; ///< DSP1 starting address + unsigned int dsp1_size; ///< DSP1 size + unsigned int dsp2_addr; ///< ecos(na51023) / DSP2(na51000) starting address + unsigned int dsp2_size; ///< ecos(na51023) / DSP2(na51000) size + unsigned int loader_addr; ///< loader starting address + unsigned int loader_size; ///< loader size + unsigned int nuttx_addr; ///< nuttx starting address + unsigned int nuttx_size; ///< nuttx size + unsigned int teeos_addr; ///< teeos starting address + unsigned int teeos_size; ///< teeos size + unsigned int hdal1_addr; ///< hdal[0] starting address + unsigned int hdal1_size; ///< hdal[0] size + unsigned int hdal2_addr; ///< hdal[1] starting address for dram2 + unsigned int hdal2_size; ///< hdal[1] size for dram2 + unsigned int core2_entry1_addr; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry1_size; ///< for smp boot, cpu2 start at 0 then jump to core2_entry2 for addr 0 can be reuse. + unsigned int core2_entry2_addr; ///< asm code to start smp + unsigned int core2_entry2_size; ///< asm code to start smp + +}DRAM_PARTITION; + +#endif \ No newline at end of file diff --git a/loader/Include/modelext/emb_partition_info.h b/loader/Include/modelext/emb_partition_info.h new file mode 100755 index 000000000..cd968cab7 --- /dev/null +++ b/loader/Include/modelext/emb_partition_info.h @@ -0,0 +1,56 @@ +#ifndef _EMB_PARTITION_INFO_H +#define _EMB_PARTITION_INFO_H + +#define EMB_PARTITION_INFO_VER 0x16072117 ///< YYYY/MM/DD HH + +/** + Partition Infomation + This is common header used between firmware of uITRON, eCos, Linux, DSP + so !!!!!! DO NOT modify it !!!!!! +*/ + +#define EMB_PARTITION_INFO_COUNT 16 + +#define EMBTYPE_UNKNOWN 0x00 +#define EMBTYPE_LOADER 0x01 /* loader must always put in partition[0] */ +#define EMBTYPE_MODELEXT 0x02 /* modelext must always put in partition[1] */ +#define EMBTYPE_UITRON 0x03 +#define EMBTYPE_ECOS 0x04 +#define EMBTYPE_UBOOT 0x05 +#define EMBTYPE_LINUX 0x06 +#define EMBTYPE_DSP 0x07 +#define EMBTYPE_PSTORE 0x08 +#define EMBTYPE_FAT 0x09 +#define EMBTYPE_EXFAT 0x0A +#define EMBTYPE_ROOTFS 0x0B +#define EMBTYPE_RAMFS 0x0C +#define EMBTYPE_UENV 0x0D /* u-boot environment data */ +#define EMBTYPE_MBR 0x0E /* for emmc partition, mbr always put in partition[0] instead of loader */ +#define EMBTYPE_NUTTX 0x0F +#define EMBTYPE_RTOS 0x10 +#define EMBTYPE_TEEOS 0x11 + +/** + customer defined data partition format +*/ +#define EMBTYPE_USER0 0x80 +#define EMBTYPE_USER1 0x81 +#define EMBTYPE_USER2 0x82 +#define EMBTYPE_USER3 0x83 +#define EMBTYPE_USER4 0x84 +#define EMBTYPE_USER5 0x85 +#define EMBTYPE_USER6 0x86 +#define EMBTYPE_USER7 0x87 + + +/* for reason of compatiable linux, we use original type to decalre */ + +typedef struct _EMB_PARTITION { + unsigned short EmbType; /* EMBTYPE_ */ + unsigned short OrderIdx; /* Order index of the same EmbType based on '0' */ + unsigned long long PartitionOffset; /* Phyical offset of partition */ + unsigned long long PartitionSize; /* Size of this partition */ + unsigned long long ReversedSize; /* Reserved size for bad block */ +} EMB_PARTITION, *PEMB_PARTITION; + +#endif diff --git a/loader/Include/modelext/gpio_info.h b/loader/Include/modelext/gpio_info.h new file mode 100755 index 000000000..7a49e37cd --- /dev/null +++ b/loader/Include/modelext/gpio_info.h @@ -0,0 +1,42 @@ +/** + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. + + @file gpio_info.h + @ingroup mMODELEXT + + @brief Header file of IO config + This file is the header file of IO config + + @note Nothing. + @date 2016/06/24 +*/ + +/** \addtogroup mIPRJAPCommonIO */ +//@{ + +#ifndef _GPIO_INFO_H +#define _GPIO_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif + +#define GPIO_INFO_VER 0x16062414 ///< YYYY/MM/DD HH + + +//-------------------------------------------------------------------- +// GPIO common +//-------------------------------------------------------------------- +typedef struct _GPIO_INIT_OBJ{ + UINT32 GpioPin; + UINT32 GpioDir; + UINT32 PadDir; + UINT32 PadPin; +} GPIO_INIT_OBJ,*PGPIO_INIT_OBJ; + +#endif + +//@} + diff --git a/loader/Include/modelext/interrupt.h b/loader/Include/modelext/interrupt.h new file mode 100755 index 000000000..c5c2e20db --- /dev/null +++ b/loader/Include/modelext/interrupt.h @@ -0,0 +1,764 @@ +/** + Header file for Interrupt module + + This file is the header file that define the API for Interrupt module. + + @file Interrupt.h + @ingroup mIDrvSys_Interrupt + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2010. All rights reserved. +*/ + +#ifndef _INTERRUPT_H +#define _INTERRUPT_H + +#if defined(__UITRON) +#include "Type.h" +#include "cc.h" +#else +#include "nvt_type.h" +#include "modelext/cc.h" +#define _ARM_GIC_USAGE_ ENABLE +#endif + +// Interrupt number <= 32 +//typedef UINT32 INT_PTN; +// Interrupt number > 32 +typedef UINT64 INT_PTN; + +/** + @addtogroup mIDrvSys_Interrupt +*/ +//@{ +#define INT_GIC_ID_DST_VER 0x16080216 + + +/** + Interrupt configuration identifier + + @note For int_setConfig() +*/ +typedef enum +{ + INT_CONFIG_ID_GIC_DESTINATION = 0, ///< Configured Interrupt exception destination to CPU/CPU2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_GIC_DST : Point of destination table + + INT_CONFIG_ID_INTC_DESTINATION, ///< Configured Interrupt exception destination to DSP/DSP2 + ///< @note + ///< Context is : + ///< - @b PINT_ID_INTC_DST : Point of destination table + + + + ENUM_DUMMY4WORD(INT_CONFIG_ID) +} INT_CONFIG_ID; + +/** + Interrupt module ID + + Interrupt module ID for int_getIRQId() and int_getDummyId(). +*/ +#if(_ARM_GIC_USAGE_ == DISABLE) +#define INT_GIC_SPI_START_ID 0 +#else +#define INT_GIC_SPI_START_ID 32 +#endif + +typedef enum +{ + INT_ID_TIMER = INT_GIC_SPI_START_ID, + INT_ID_SIE, + INT_ID_SIE2, + INT_ID_SIE3, + + INT_ID_SIE4, + INT_ID_IPE, + INT_ID_IME, + INT_ID_DCE, + + INT_ID_IFE, + INT_ID_IFE2, + INT_ID_DIS, + INT_ID_FDE, + +// INT_ID_RDE, //Removed @ NT96680 + INT_ID_ETH_LPI, //Ethernet_LPI + INT_ID_RHE, + INT_ID_DRE, + INT_ID_DAI, //15 + + INT_ID_H26X, + INT_ID_JPEG, + INT_ID_GRAPHIC, + INT_ID_GRAPHIC2, + + INT_ID_AFFINE, + INT_ID_ISE, + INT_ID_TGE, + INT_ID_TSMUX, + + INT_ID_GPIO, + INT_ID_REMOTE, + INT_ID_PWM, + INT_ID_USB, + + INT_ID_USB3, + INT_ID_NAND, + INT_ID_SDIO, + INT_ID_SDIO2, //31 + + INT_ID_SDIO3, + INT_ID_DMA, + INT_ID_ETHERNET, + INT_ID_SPI, + + INT_ID_SPI2, + INT_ID_SPI3, + INT_ID_SPI4, +// INT_ID_SPI5, //Removed @ NT96680 + INT_ID_ETH_REV_MII, //Ethernet_RevMII + + INT_ID_SIF, + INT_ID_I2C, + INT_ID_I2C2, + INT_ID_UART, //43 + + INT_ID_UART2, + INT_ID_UART3, + INT_ID_UART4, + INT_ID_ADC, + + INT_ID_IDE, + INT_ID_IDE2, + INT_ID_DSI, + INT_ID_MI, //51 + + INT_ID_HDMI, +// INT_ID_VX1, //Removed @ NT96680 + INT_ID_DMA2, //New @ NT96680 + INT_ID_LVDS, + INT_ID_LVDS2, //55 + + INT_ID_RTC, + INT_ID_WDT, + INT_ID_CG, + INT_ID_CC, //59 + + INT_ID_I2C3, //60 +// New add @ NT96680 + INT_ID_SLVS_EC, + INT_ID_LVDS3, //share with HiSPi3/CSI3 + INT_ID_LVDS4, //share with HiSPi4/CSI4 + + INT_ID_LVDS5, //share with HiSPi5/CSI5 + INT_ID_LVDS6, //share with HiSPi6/CSI6 + INT_ID_LVDS7, //share with HiSPi7/CSI7 + INT_ID_LVDS8, //share with HiSPi8/CSI8 + + INT_ID_SIE5, + INT_ID_SIE6, + INT_ID_SIE7, + INT_ID_SIE8, + + INT_ID_IVE, + INT_ID_SVM, + INT_ID_SDE, + INT_ID_CNN, //75 + + INT_ID_DSP, + INT_ID_DSP2, + INT_ID_CANBUS, + INT_ID_CRYPTO, //79 + + INT_ID_COPY, + INT_ID_ROTATE, + INT_ID_I2C4, + INT_ID_I2C5, //83 + +// INT_ID_I2C6, +// INT_ID_I2C7, + INT_ID_DRTC, + INT_ID_ISE2, + INT_ID_TIMER2, + INT_ID_GPIO2, //87 + + INT_ID_PWM2, + INT_ID_CC2, //89 + INT_ID_SIF2, + + INT_ID_DSP_2, + INT_ID_DSP_2_2, + INT_ID_TSDEMUX, //93 + + INT_ID_CNT, + INT_ID_MAX = INT_ID_CNT - INT_GIC_SPI_START_ID, //94 + + + INT_ID_WFI = 229, + INT_ID_GIC_TOTAL = 256, + ENUM_DUMMY4WORD(INT_ID) +} INT_ID; + +typedef enum +{ + INT_TARGET_CORE0 = 1, + INT_TARGET_CORE1, + ENUM_DUMMY4WORD(INT_CORE_ID) +} INT_CORE_ID; + +/* + Interrupt module ID of GIC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_DST, *PINT_GIC_ID_DST; + +/* + Interrupt module ID of INTC + + Indicate which core will configured as destination + + @note For DMA_WRITEPROT_ATTR +*/ + + +typedef union +{ + INT_PTN Reg[2]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + + //INT12 + UINT32 bReserved12:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + //INT20 + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + //INT36 + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bReserved39:1; +// UINT32 bInt_ID_SPI5:1; + + //INT40 + UINT32 bReserved40:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bReserved86:1; + UINT32 bReserved87:1; + + //INT88 + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved89:3; + + //INT92 + UINT32 bReserved92:4; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_INTC_ID_DST, *PINT_INTC_ID_DST; + +typedef union +{ + INT_PTN Reg[4]; + struct + { + //INT0 + UINT32 bInt_ID_TIMER:1; + UINT32 bInt_ID_SIE:1; + UINT32 bInt_ID_SIE2:1; + UINT32 bInt_ID_SIE3:1; + + UINT32 bInt_ID_SIE4:1; + UINT32 bInt_ID_IPE:1; + UINT32 bInt_ID_IME:1; + UINT32 bInt_ID_DCE:1; + + UINT32 bInt_ID_IFE:1; + UINT32 bInt_ID_IFE2:1; + UINT32 bInt_ID_DIS:1; + UINT32 bInt_ID_FDE:1; + +// UINT32 bInt_ID_RDE:1; + UINT32 bInt_ID_Ethernet_LPI:1; + UINT32 bInt_ID_RHE:1; + UINT32 bInt_ID_DRE:1; + UINT32 bInt_ID_DAI:1; + + + //INT16 + UINT32 bInt_ID_H264:1; + UINT32 bInt_ID_JPEG:1; + UINT32 bInt_ID_GRAPHIC:1; + UINT32 bInt_ID_GRAPHIC2:1; + + UINT32 bInt_ID_AFFINE:1; + UINT32 bInt_ID_ISE:1; + UINT32 bInt_ID_TGE:1; + UINT32 bInt_ID_TSMUX:1; + + UINT32 bInt_ID_GPIO:1; + UINT32 bInt_ID_REMOTE:1; + UINT32 bInt_ID_PWM:1; + UINT32 bInt_ID_USB:1; + + UINT32 bInt_ID_USB3:1; + UINT32 bInt_ID_NAND:1; + UINT32 bInt_ID_SDIO:1; + UINT32 bInt_ID_SDIO2:1; + + //INT32 + UINT32 bInt_ID_SDIO3:1; + UINT32 bInt_ID_DMA:1; + UINT32 bInt_ID_ETHERNET:1; + UINT32 bInt_ID_SPI:1; + + UINT32 bInt_ID_SPI2:1; + UINT32 bInt_ID_SPI3:1; + UINT32 bInt_ID_SPI4:1; + UINT32 bInt_ID_Ehternet_RevMII:1; +// UINT32 bInt_ID_SPI5:1; + + + UINT32 bInt_ID_SIF:1; + UINT32 bInt_ID_I2C:1; + UINT32 bInt_ID_I2C2:1; + UINT32 bInt_ID_UART:1; + + UINT32 bInt_ID_UART2:1; + UINT32 bInt_ID_UART3:1; + UINT32 bInt_ID_UART4:1; + UINT32 bInt_ID_ADC:1; + + //INT48 + UINT32 bInt_ID_IDE:1; + UINT32 bInt_ID_IDE2:1; + UINT32 bInt_ID_DSI:1; + UINT32 bInt_ID_MI:1; + + //INT52 + UINT32 bInt_ID_HDMI:1; +// UINT32 bInt_ID_VX1:1; + UINT32 bInt_ID_DMA2:1; + UINT32 bInt_ID_LVDS:1; // LVDS& HiSPI& CSI + UINT32 bInt_ID_LVDS2:1; //LVDS2&HiSPI2&CSI2 + + //INT56 + UINT32 bInt_ID_RTC:1; + UINT32 bInt_ID_WDT:1; + UINT32 bInt_ID_CG:1; + UINT32 bInt_ID_CC:1; + + //INT60 + UINT32 bInt_ID_I2C3:1; + UINT32 bInt_ID_SLVS_EC:1; + UINT32 bInt_ID_LVDS3:1; //LVDS3&HiSPI3&CSI3 + UINT32 bInt_ID_LVDS4:1; //LVDS4&HiSPI4&CSI4 + + //INT64 + UINT32 bInt_ID_LVDS5:1; //LVDS5&HiSPI5&CSI5 + UINT32 bInt_ID_LVDS6:1; //LVDS6&HiSPI6&CSI6 + UINT32 bInt_ID_LVDS7:1; //LVDS7&HiSPI7&CSI7 + UINT32 bInt_ID_LVDS8:1; //LVDS8&HiSPI8&CSI8 + + //INT68 + UINT32 bInt_ID_SIE5:1; + UINT32 bInt_ID_SIE6:1; + UINT32 bInt_ID_SIE7:1; + UINT32 bInt_ID_SIE8:1; + + //INT72 + UINT32 bInt_ID_IVE:1; + UINT32 bInt_ID_SVM:1; + UINT32 bInt_ID_SDE:1; + UINT32 bInt_ID_CNN:1; + + //INT76 + UINT32 bInt_ID_DSP:1; + UINT32 bInt_ID_DSP2:1; + UINT32 bInt_ID_CANBUS:1; + UINT32 bInt_ID_CRYPTO:1; + + //INT80 + UINT32 bInt_ID_HWCOPY:1; + UINT32 bInt_ID_ROTATE:1; + UINT32 bInt_ID_I2C4:1; + UINT32 bInt_ID_I2C5:1; + + //INT84 + UINT32 bInt_ID_I2C6:1; + UINT32 bInt_ID_I2C7:1; + UINT32 bInt_ID_TIMER2:1; //Timer to CA53 core2 + UINT32 bInt_ID_GPIO2:1; //GPIO to CA53 core2 + + //INT88 + UINT32 bInt_ID_PWM2:1; + UINT32 bInt_ID_CC2:1; + UINT32 bInt_ID_SIF2:1; //Timer to CA53 core2 + UINT32 bInt_ID_DSP_2:1; //?? + + //INT92 + UINT32 bInt_ID_DSP2_2:1; //?? + UINT32 bInt_ID_TMDEMUX:1; + UINT32 bReserved92:2; + //INT96 => 4 + UINT32 bReserved96:4; + //INT100=> 4 + UINT32 bReserved100:4; + //INT104=> 4 + UINT32 bReserved104:4; + //INT108=> 4 + UINT32 bReserved108:4; + //INT112=> 4 + UINT32 bReserved112:4; + //INT116=> 4 + UINT32 bReserved116:4; + //INT120=> 4 + UINT32 bReserved120:4; + //INT124=> 4 + UINT32 bReserved124:4; + }Bit; +} INT_GIC_ID_ENABLE, *PINT_GIC_ID_ENABLE; + +typedef struct +{ + INT_GIC_ID_DST int_id_dst[CC_CORE_CA53_CORE_NUM]; +} INT_GIC_DST, *PINT_GIC_DST; + +typedef struct +{ + INT_INTC_ID_DST int_id_dst[CC_CORE_DSP_NUM]; +} INT_INTC_DST, *PINT_INTC_DST; + +typedef struct +{ + INT_GIC_ID_ENABLE int_id_enable; +} INT_INTC_ENABLE, *PINT_INTC_ENABLE; + + +// MIPI CSI share the interrupt ID with LVDS / HiSPi +#define INT_ID_CSI INT_ID_LVDS +#define INT_ID_CSI2 INT_ID_LVDS2 + +#define INT_ID_CSI3 INT_ID_LVDS3 +#define INT_ID_CSI4 INT_ID_LVDS4 + +#define INT_ID_CSI5 INT_ID_LVDS5 +#define INT_ID_CSI6 INT_ID_LVDS6 +#define INT_ID_CSI7 INT_ID_LVDS7 +#define INT_ID_CSI8 INT_ID_LVDS8 + +#define INT_ID_VX1 INT_ID_LVDS5 +#define INT_ID_VX1_2 INT_ID_LVDS6 + +// Macro to generate bit value from ID +#define INT_ID_TO_BIT(Id) ((INT_PTN)(1) << (Id)) + +// check type and ID +STATIC_ASSERT((INT_ID_MAX - INT_GIC_SPI_START_ID) <= (sizeof(INT_PTN) << 3)); + +#define INT_ALL_MODULES ((sizeof(INT_PTN) == 4) ? 0xFFFFFFFFul : 0xFFFFFFFFFFFFFFFFull) + +extern INT_PTN int_getEnable(void); +extern INT_PTN int_getFlag(void); +extern INT_ID int_getIRQId(void); +extern INT_ID int_getDummyId(void); +extern UINT32 int_getLatency(void); +extern void int_setConfig(INT_CONFIG_ID ConfigID, UINT32 uiConfig); +extern void int_get_gic_enable(PINT_INTC_ENABLE gic_int_en); + + +//@} + +#endif diff --git a/loader/Include/modelext/model_cfg.h b/loader/Include/modelext/model_cfg.h new file mode 100755 index 000000000..eb7be844c --- /dev/null +++ b/loader/Include/modelext/model_cfg.h @@ -0,0 +1,8 @@ +#ifndef _MODEL_CFG_H +#define _MODEL_CFG_H + +#define MODEL_CFG_VER 0x16072510 ///< YYYY/MM/DD HH + +//No data structure, just a string. + +#endif diff --git a/loader/Include/modelext/modelext_info.h b/loader/Include/modelext/modelext_info.h new file mode 100755 index 000000000..b96b50b96 --- /dev/null +++ b/loader/Include/modelext/modelext_info.h @@ -0,0 +1,35 @@ +#ifndef _MODELEXT_INFO_H +#define _MODELEXT_INFO_H + +#define MODELEXT_INFO_VER 0x16072219 ///< YYYY/MM/DD HH + +typedef enum _MODELEXT_TYPE { + MODELEXT_TYPE_DUMMY = 0, + MODELEXT_TYPE_INFO , + MODELEXT_TYPE_BIN_INFO , + MODELEXT_TYPE_PINMUX_CFG , + MODELEXT_TYPE_INTDIR_CFG , + MODELEXT_TYPE_EMB_PARTITION, + MODELEXT_TYPE_GPIO_INFO , + MODELEXT_TYPE_DRAM_PARTITION, + MODELEXT_TYPE_MODEL_CFG, + MODELEXT_TYPE_MAX +} MODELEXT_TYPE; + +typedef struct _MODELEXT_HEADER { + unsigned int size; ///< header size + container size + unsigned int type; ///< MODELEXT_TYPE + unsigned int number; ///< number of carried data elements + unsigned int version; ///< data header version +} MODELEXT_HEADER; + +typedef struct _MODELEXT_INFO { + char name[8]; ///< always be 'M','O','D','E','L','E','X','T' + char chip_name[8]; ///< CHIP_NAME (8) ---- check by encrypt_bin + char version[8]; ///< Reversed + char date[8]; ///< date + unsigned int ext_bin_length; ///< Bin File Length (4) --- write by encrypt_bin + unsigned int check_sum; ///< Check Sum Value (4) ----- write by encrypt_bin +} MODELEXT_INFO; + +#endif diff --git a/loader/Include/modelext/modelext_parser.h b/loader/Include/modelext/modelext_parser.h new file mode 100755 index 000000000..e00170ea1 --- /dev/null +++ b/loader/Include/modelext/modelext_parser.h @@ -0,0 +1,78 @@ +#ifndef _MODELEXT_PARSER_H +#define _MODELEXT_PARSER_H + +#include "modelext_info.h" + +/** + modelext inline parse. + + modelext info tables are set to an certain memory address, + which use to get data pointer you want. + + @param[in] modelext info address. + @param[in] refer to MODELEXT_TYPE_ + @param[in] a memory space will be stored with description of modelext type. + @return + - @b address: the data pointer of result. +*/ +static inline unsigned char *modelext_get_cfg(unsigned char *buf, unsigned int type, MODELEXT_HEADER **header) +{ +#define MAGIC "MODELEXT" + + MODELEXT_HEADER *h = (MODELEXT_HEADER*)buf; + MODELEXT_INFO *d = (MODELEXT_INFO*)(buf + sizeof(MODELEXT_HEADER)); + + if(type >= MODELEXT_TYPE_MAX) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(memcmp(d->name, MAGIC, strlen(MAGIC))) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + MODELEXT_HEADER* h_tail = (MODELEXT_HEADER*)(buf + d->ext_bin_length); + + while(h->size) + { + if(h->type == type) + { + break; + } + else + { + h = (MODELEXT_HEADER*)(((char*)h) + h->size); + if(h >= h_tail) + { + return NULL; + } + } + } + + if(!h->size) + { + if(header) + { + *header = NULL; + } + return NULL; + } + + if(header) + { + *header = h; + } + + return (unsigned char*)(((unsigned char*)h) + sizeof(MODELEXT_HEADER)); +} + +#endif diff --git a/loader/Include/modelext/shm_info.h b/loader/Include/modelext/shm_info.h new file mode 100755 index 000000000..4ffaeaa3e --- /dev/null +++ b/loader/Include/modelext/shm_info.h @@ -0,0 +1,131 @@ +/** + @file shm_info.h + @ingroup + @note THESE STRUCTS ARE VERY VERY IMPORTANT FORMAT DEFINITION OF SYSTEM, + DO NOT MODIFY ANY ITEM OR INSERT/REMOVE ANY ITEM OF THESE STRUCTS!!! + + Copyright Novatek Microelectronics Corp. 2018. All rights reserved. +*/ +#ifndef __ARCH_COMMON_SHM_INFO_H +#define __ARCH_COMMON_SHM_INFO_H + +#if defined(__UITRON) +#include "Type.h" +#elif defined(_NVT_LINUX_) +#include +#else +#include +#endif + +#define SHM_INFO_VER 0x18060815 ///< YYYY/MM/DD HH + +/** + @name Ld control flag for LDINFO.LdCtrl +*/ +//@{ +#define LDCF_PARTLOAD_EN 0x0000001 ///< BIT 0.PARTLOAD_EN (0=no,1=yes) +//@} + +/** + @name Ld control flag for LDINFO.LdCtrl2 +*/ +//@{ +#define LDCF_UPDATE_FW 0x0000001 ///< BIT 0.UPDATE_FW (0=no,1=yes) +#define LDCF_UPDATE_LD 0x0000002 ///< BIT 1.UPDATE_LD (0=no,1=yes) +#define LDCF_BOOT_CARD 0x0000004 ///< BIT 2.BOOT_CARD (0=no,1=yes) +#define LDCF_BOOT_FLASH 0x0000008 ///< BIT 3.BOOT_FLASH (0=no,1=yes) +#define LDCF_UPDATE_CAL 0x0000010 ///< BIT 4.UPDATE_CAL (0=no,1=yes) +#define LDCF_UPDATE_FW_DONE 0x0000100 ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) +#define LDCF_S3_BOOT 0x0000200 ///< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) +//@} + +/** + Loader information + + MUST 28 WORDS +*/ +typedef struct _BOOTINFO { + char LdInfo_1[16]; ///< LD-NAME(16) ------ w by Ld + UINT32 LdCtrl; ///< Fw flag (4) ----------- r by Ld + ///< BIT 0.enable part-load (0=full load,1=part load) + UINT32 LdCtrl2; ///< Ld flag (4) ----------- w by Ld + ///< BIT 0.UPDATE_FW (0=no,1=yes) + ///< BIT 1.UPDATE_LOADER (0=no,1=yes) + ///< BIT 2.BOOT_CARD (0=no,1=yes) + ///< BIT 3.BOOT_FLASH (0=no,1=yes) + ///< BIT 4.UPDATE_CAL (0=no,1=yes) + ///< BIT 8.UPDATE_FW_DONE (0=no,1=yes) + //< BIT 9.BOOT FROM S3 STATE (0=no,1=yes) + UINT32 LdLoadSize; ///< Ld load size (4) ------ w by Ld (NOTE: this value must be block size align) + UINT32 LdLoadTime; ///< Ld exec time(us) (4) -- w by Ld + UINT32 LdResvSize; ///< Ld size (by bytes, reserved size in partition) (4) ------ w by Ld + UINT32 FWResvSize; ///< FW reserved size (4) ------ w by Ld + UINT16 LdPackage; ///< IC package expected by Ld (0xFF: ES, 0: 660, 3: 663, 5: 665, etc...) + UINT16 LdStorage; ///< Internal storage expected by Ld (0: unkown, 1: nand, 2: spi nand, 3: spi nor) + UINT32 fdt_addr; + UINT32 Resv[16]; ///< (4*5) ------------ reserved for project Ld +} BOOTINFO; + +STATIC_ASSERT(sizeof(BOOTINFO) == 112); + +/** + communication information + + MUST 54 WORDS +*/ +//BOOT_REASON +#define BOOT_REASON_NORMAL 0 // normal or from sd +#define BOOT_REASON_FWUPDFW 1 // Firmware update Firmware +#define BOOT_REASON_FROM_USB 2 // Update from USB +#define BOOT_REASON_FROM_ETH 3 // Update from ethernet +#define BOOT_REASON_FORMAT_ROOTFS 4 // Format rootfs because rootfs broken is detected +#define BOOT_REASON_RECOVERY_SYS 5 // System recovery from eMMC +#define BOOT_REASON_FROM_UART 6 // Update from uart + +//COMMINFO::Resv field definition +typedef enum _COMM_RESV_IDX_{ + COMM_RESV_IDX_BOOT_REASON = 0, + COMM_RESV_IDX_CORE1_START = 1, + COMM_RESV_IDX_CORE2_START = 2, + COMM_RESV_IDX_UITRON_COMP_ADDR = 3, + COMM_RESV_IDX_UITRON_COMP_LEN = 4, + COMM_RESV_IDX_FW_UPD_ADDR = 5, + COMM_RESV_IDX_FW_UPD_LEN = 6, + COMM_RESV_IDX_OTA_NAME_ADDR = 7, + COMM_RESV_IDX_S3_APB_ADDR = 8, + COMM_RESV_IDX_S3_APB_LEN = 9, +} COMM_RESV_IDX; + +typedef struct _COMMINFO { + char CommInfo_1[16];///< COMMINFO (16) + UINT32 Resv[45];///< reversed data for communication between loader, uboot, uitron, linux + // Resv[0]: COMM_RESV_IDX_BOOT_REASON, + // BYTE[0]: BOOT_REASON: use #define COMM_BOOT_REASON_ + // BYTE[1]: BOOT_DONE: 0:Not yet, 1:Done 2:NG + // BYTE[2]: DSP_DONE: 0:Not yet, 1:Done 2:NG + // Resv[1]: COMM_CORE1_START (used on uboot trigger loader to start uitron) + // Resv[2]: COMM_CORE2_START (used on uitron trigger linux resume) + // Resv[3]: COMM_UITRON_COMP_ADDR + // Resv[4]: COMM_UITRON_COMP_LEN + // Resv[5]: COMM_FW_UPD_ADDR + // Resv[6]: COMM_FW_UPD_LEN + // Resv[7]: COMM_OTA_NAME_ADDR : OTA name + // Resv[8]: COMM_S3_APB_ADDR : S3-resume's apb register info addr + // Resv[9]: COMM_S3_APB_LEN : S3-resume's apb register info len + UINT32 UserDef[5]; ///< can be used for customer +} COMMINFO; + +STATIC_ASSERT(sizeof(COMMINFO) == 216); + +/** + Binary file information + + MUST 82 WORDS +*/ +typedef struct _SHMINFO { + BOOTINFO boot; + COMMINFO comm; +} SHMINFO; + +STATIC_ASSERT(sizeof(SHMINFO) == 328); +#endif /* __ARCH_COMMON_SHM_INFO_H */ diff --git a/loader/Include/modelext/top.h b/loader/Include/modelext/top.h new file mode 100755 index 000000000..2011294fc --- /dev/null +++ b/loader/Include/modelext/top.h @@ -0,0 +1,1382 @@ +/** + TOP controller header + + Sets the pinmux of each module. + + @file top.h + @ingroup mIDrvSys_TOP + @note Refer NT96650 data sheet for PIN/PAD naming + + Copyright Novatek Microelectronics Corp. 2013. All rights reserved. +*/ + +#ifndef _TOP_H +#define _TOP_H + +#if defined(__UITRON) +#include "Type.h" +#else +#include "nvt_type.h" +#endif +//#define TOP_NEW_API (0) + +/** + @addtogroup mIDrvSys_TOP +*/ +//@{ +#define PIN_GROUP_CONFIG_VER 0x16062910 + +/** + Debug port select ID + + Debug port select value for pinmux_select_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_CKG = 0x0000, ///< CKGen + PINMUX_DEBUGPORT_ARB = 0x0001, ///< Arbiter + PINMUX_DEBUGPORT_DDR = 0x0002, ///< DDR + PINMUX_DEBUGPORT_APBTG = 0x0003, ///< APBTG + PINMUX_DEBUGPORT_OCPBRG = 0x0004, ///< OCP BRG + PINMUX_DEBUGPORT_INTC = 0x0005, ///< INTC + PINMUX_DEBUGPORT_IDE = 0x0006, ///< IDE + PINMUX_DEBUGPORT_IDE2 = 0x0007, ///< IDE2 + PINMUX_DEBUGPORT_MI = 0x0008, ///< MI + PINMUX_DEBUGMIPI_DSI = 0x0009, ///< MIPI DSI + PINMUX_DEBUGMIPI_CC = 0x000A, ///< CC + PINMUX_DEBUGMIPI_EFUSE = 0x000B, ///< EFUSE + PINMUX_DEBUGMIPI_ETH = 0x000C, ///< ETH + PINMUX_DEBUGMIPI_AHBC_ETH = 0x000D, ///< AHBC ETH + PINMUX_DEBUGMIPI_TSMUX = 0x000E, ///< TSMUX + + PINMUX_DEBUGPORT_TIMER = 0x0010, ///< Timer + PINMUX_DEBUGPORT_WDT = 0x0011, ///< WDT + PINMUX_DEBUGPORT_GPIO = 0x0012, ///< GPIO + PINMUX_DEBUGPORT_SSP = 0x0013, ///< SSP (DAI) + PINMUX_DEBUGPORT_AUDIO = 0x0014, ///< AUDIO + PINMUX_DEBUGPORT_SDIO1 = 0x0015, ///< SDIO1 + PINMUX_DEBUGPORT_SDIO2 = 0x0016, ///< SDIO2 + PINMUX_DEBUGPORT_SDIO3 = 0x0017, ///< SDIO3 + PINMUX_DEBUGPORT_SMMC = 0x0018, ///< XD/NAND/SMC + PINMUX_DEBUGPORT_USB = 0x0019, ///< USB + PINMUX_DEBUGPORT_USB2 = 0x001A, ///< USB2 + PINMUX_DEBUGPORT_AHBC_USB = 0x001B, ///< AHBC_USB + PINMUX_DEBUGPORT_AHBC_USB2 = 0x001C, ///< AHBC_USB2 + PINMUX_DEBUGPORT_I2C = 0x001D, ///< I2C + PINMUX_DEBUGPORT_I2C2 = 0x001E, ///< I2C2 + PINMUX_DEBUGPORT_SIF = 0x001F, ///< SIF + PINMUX_DEBUGPORT_SPI = 0x0020, ///< SPI + PINMUX_DEBUGPORT_SPI2 = 0x0021, ///< SPI2 + PINMUX_DEBUGPORT_SPI3 = 0x0022, ///< SPI3 + PINMUX_DEBUGPORT_SPI4 = 0x0023, ///< SPI4 + PINMUX_DEBUGPORT_SPI5 = 0x0024, ///< SPI5 + PINMUX_DEBUGPORT_PWM = 0x0025, ///< PWM + PINMUX_DEBUGPORT_ADM = 0x0026, ///< ADC + PINMUX_DEBUGPORT_REMOTE = 0x0027, ///< Remote + PINMUX_DEBUGPORT_CRYPTO = 0x0028, ///< Crypto + + PINMUX_DEBUGPORT_OCP2BRG = 0x0030, ///< OCP2 BRG + PINMUX_DEBUGPORT_DSP = 0x0031, ///< DSP + PINMUX_DEBUGPORT_H264 = 0x0038, ///< H.264 + + PINMUX_DEBUGMIPI_CSI = 0x0040, ///< MIPI CSI + PINMUX_DEBUGMIPI_CSI2 = 0x0041, ///< MIPI CSI2 + PINMUX_DEBUGMIPI_VX1 = 0x0042, ///< VX1 + PINMUX_DEBUGPORT_SIE = 0x0043, ///< SIE + PINMUX_DEBUGMIPI_SIE2 = 0x0044, ///< SIE2 + PINMUX_DEBUGPORT_SIE3 = 0x0045, ///< SIE3 + PINMUX_DEBUGMIPI_SIE4 = 0x0046, ///< SIE4 + PINMUX_DEBUGPORT_TGE = 0x0047, ///< TGE + PINMUX_DEBUGPORT_DIS = 0x0048, ///< DIS + PINMUX_DEBUGPORT_FDE = 0x0049, ///< FDE + PINMUX_DEBUGPORT_JPEG = 0x004A, ///< JPEG + PINMUX_DEBUGPORT_GRAPHIC = 0x004B, ///< GRAPHIC + PINMUX_DEBUGPORT_GRAPHIC2 = 0x004C, ///< GRAPHIC2 + PINMUX_DEBUGPORT_IFE = 0x004D, ///< IFE + PINMUX_DEBUGPORT_AFFINE = 0x004E, ///< Affine + PINMUX_DEBUGPORT_ISE = 0x004F, ///< ISE + PINMUX_DEBUGPORT_RDE = 0x0050, ///< RDE + PINMUX_DEBUGPORT_RHE = 0x0051, ///< RHE + PINMUX_DEBUGPORT_I2C3 = 0x0052, ///< I2C3 + + PINMUX_DEBUGPORT_IPE = 0x0060, ///< IPE + PINMUX_DEBUGPORT_IME = 0x0061, ///< IME + PINMUX_DEBUGPORT_IFE2 = 0x0062, ///< IFE2 + PINMUX_DEBUGPORT_HDMI = 0x0063, ///< HDMI + PINMUX_DEBUGPORT_DCE = 0x0064, ///< DCE + PINMUX_DEBUGPORT_DRE = 0x0065, ///< DRE + +/* //remove for NT96660 + PINMUX_DEBUGPORT_AMBARD = 0x0000, ///< AMBA RD + PINMUX_DEBUGPORT_AMBAWR = 0x0001, ///< AMBA WR + PINMUX_DEBUGPORT_AHB = 0x0002, ///< AHB + PINMUX_DEBUGPORT_AHBC0 = 0x0003, ///< AHB C0 + PINMUX_DEBUGPORT_AHBC1 = 0x0004, ///< AHB C1 + PINMUX_DEBUGPORT_APBBRG = 0x0005, ///< APB BRG + PINMUX_DEBUGPORT_DDRIO = 0x0006, ///< DDRIO + PINMUX_DEBUGPORT_LVDS = 0x001F, ///< LVDS + PINMUX_DEBUGPORT_SDIO1_FIFO = 0x0022, ///< SDIO1 FIFO + PINMUX_DEBUGPORT_SDIO2_FIFO = 0x0023, ///< SDIO2 FIFO + PINMUX_DEBUGPORT_BMC = 0x0024, ///< BMC + PINMUX_DEBUGPORT_IRDA1 = 0x0025, ///< IRDA1 + PINMUX_DEBUGPORT_IRDA2 = 0x0026, ///< IRDA2 + PINMUX_DEBUGMIPI_OCP = 0x0029, ///< OCP + PINMUX_DEBUGPORT_PRE = 0x0030, ///< PRE +*/ + PINMUX_DEBUGPORT_GROUP_NONE = 0x0000, ///< No debug port is output + PINMUX_DEBUGPORT_GROUP1 = 0x0100, ///< Output debug port to MC[18..0] + PINMUX_DEBUGPORT_GROUP2 = 0x0200, ///< Output debug port to LCD[18..0] + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT) +} PINMUX_DEBUGPORT; + +// for backward compatible +#define PINMUX_DEBUGMIPI_OCP PINMUX_DEBUGPORT_OCPBRG + +/* + PIN state for SDIO + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SDIO_STATE_NONE, + PIN_SDIO_STATE_ACTIVE = 0x0100, //< SD active + ENUM_DUMMY4WORD(PIN_SDIO_STATE) +} PIN_SDIO_STATE; + +/* + PIN state for SPI + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_SPI_STATE_NONE, + PIN_SPI_STATE_ACTIVE = 0x10000, //< SPI active + ENUM_DUMMY4WORD(PIN_SPI_STATE) +} PIN_SPI_STATE; + +/* + PIN state for NAND + + (Reserved for driver internal usage) + + @note For pinmux_getPinmux() +*/ +typedef enum +{ + PIN_NAND_STATE_NONE, + PIN_NAND_STATE_ACTIVE = 0x0400, //< NAND active + ENUM_DUMMY4WORD(PIN_NAND_STATE) +} PIN_NAND_STATE; + +/* + PINMUX selection for I2C + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2C_SEL_INACTIVE, //< I2C inactive + PINMUX_I2C_SEL_ACTIVE, //< I2C active + ENUM_DUMMY4WORD(PINMUX_I2C_SEL) +} PINMUX_I2C_SEL; + +/* + PINMUX selection for PWM + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_PWM_SEL_INACTIVE, //< PWM inactive + PINMUX_PWM_SEL_ACTIVE, //< PWM active + ENUM_DUMMY4WORD(PINMUX_PWM_SEL) +} PINMUX_PWM_SEL; + +/* + PINMUX selection for SIF + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_SIF_SEL_INACTIVE, //< SIF inactive + PINMUX_SIF_SEL_ACTIVE, //< SIF active + ENUM_DUMMY4WORD(PINMUX_SIF_SEL) +} PINMUX_SIF_SEL; + +/* + PINMUX selection for I2S + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_I2S_SEL_INACTIVE, //< I2S inactive + PINMUX_I2S_SEL_ACTIVE, //< I2S active + ENUM_DUMMY4WORD(PINMUX_I2S_SEL) +} PINMUX_I2S_SEL; + +/* + PINMUX selection for UART + + (Reserved for driver internal usage) + + @note For pinmux_setPinmux() +*/ +typedef enum +{ + PINMUX_UART_SEL_INACTIVE, //< UART inactive + PINMUX_UART_SEL_ACTIVE, //< UART active + ENUM_DUMMY4WORD(PINMUX_UART_SEL) +} PINMUX_UART_SEL; + + +/** + OCP Debug port select ID + + Debug port select value for pinmux_select_ocp_debugport(). +*/ +typedef enum +{ + PINMUX_DEBUGPORT_OCPCMD_DMA_APB = 0x0, ///< OCP CMD vs. DMA/APB + PINMUX_DEBUGPORT_OCPCMD_HANDSHAKE = 0x1, ///< OCP CMD handshaking + PINMUX_DEBUGPORT_OCP_DMA = 0x2, ///< OCP vs. DMA + PINMUX_DEBUGPORT_OCP_DEBUG_3 = 0x3, ///< OCP debug 3 + PINMUX_DEBUGPORT_OCP_DEBUG_4 = 0x4, ///< OCP debug 4 + + ENUM_DUMMY4WORD(PINMUX_DEBUGPORT_OCP) +} PINMUX_DEBUGPORT_OCP; + +/** + Function group + + @note For pinmux_init() +*/ +typedef enum +{ + PIN_FUNC_SDIO, ///< SDIO. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO2, ///< SDIO2. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_SDIO3, ///< SDIO3. Configuration refers to PIN_SDIO_CFG. + PIN_FUNC_NAND, ///< NAND. Configuration refers to PIN_NAND_CFG. + PIN_FUNC_SENSOR, ///< sensor interface. Configuration refers to PIN_SENSOR_CFG. + PIN_FUNC_SENSOR2, ///< sensor2 interface. Configuration refers to PIN_SENSOR2_CFG. + PIN_FUNC_SENSOR3, ///< sensor3 interface. Configuration refers to PIN_SENSOR3_CFG. + PIN_FUNC_SENSOR4, ///< sensor4 interface. Configuration refers to PIN_SENSOR4_CFG. + PIN_FUNC_SENSOR5, ///< sensor5 interface. Configuration refers to PIN_SENSOR5_CFG. + PIN_FUNC_SENSOR6, ///< sensor6 interface. Configuration refers to PIN_SENSOR6_CFG. + PIN_FUNC_SENSOR7, ///< sensor7 interface. Configuration refers to PIN_SENSOR7_CFG. + PIN_FUNC_SENSOR8, ///< sensor8 interface. Configuration refers to PIN_SENSOR8_CFG. + PIN_FUNC_MIPI_LVDS, ///< MIPI/LVDS interface configuration. Configuration refers to PIN_MIPI_LVDS_CFG. + PIN_FUNC_I2C, ///< I2C. Configuration refers to PIN_I2C_CFG. + PIN_FUNC_SIF, ///< SIF. Configuration refers to PIN_SIF_CFG. + PIN_FUNC_UART, ///< UART. Configuration refers to PIN_UART_CFG. + PIN_FUNC_SPI, ///< SPI. Configuration refers to PIN_SPI_CFG. + PIN_FUNC_REMOTE, ///< REMOTE. Configuration refers to PIN_REMOTE_CFG. + PIN_FUNC_PWM, ///< PWM. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_AUDIO, ///< AUDIO. Configuration refers to PIN_PWM_CFG. + PIN_FUNC_LCD, ///< LCD interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_LCD2, ///< LCD2 interface. Configuration refers to PINMUX_LCDINIT, PINMUX_PMI_CFG, PINMUX_DISPMUX_SEL. + PIN_FUNC_TV, ///< TV interface. Configuration refers to PINMUX_TV_HDMI_CFG. + PIN_FUNC_HDMI, ///< HDMI. Configuration refers to PINMUX_LCDINIT, PINMUX_TV_HDMI_CFG, PINMUX_HDMI_CFG. + PIN_FUNC_ETH, ///< ETH. Configuration refers to + + ENUM_DUMMY4WORD(PIN_FUNC) +} PIN_FUNC; + +/** + PIN config for SDIO + + @note For pinmux_init() with PIN_FUNC_SDIO or PIN_FUNC_SDIO2 or PIN_FUNC_SDIO3.\n + For example, you can use {PIN_FUNC_SDIO, PIN_SDIO_CFG_1ST_PINMUX|PIN_SDIO_CFG_4BITS}\n + to declare SDIO is 4 bits and located in 1st pinmux location. +*/ +typedef enum +{ + PIN_SDIO_CFG_NONE, + PIN_SDIO_CFG_4BITS = 0x01, ///< 4 bits wide + PIN_SDIO_CFG_8BITS = 0x02, ///< 8 bits wide + + PIN_SDIO_CFG_1ST_PINMUX = 0x00, ///< 1st pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[28..33] (C_GPIO[28..33]) + PIN_SDIO_CFG_2ND_PINMUX = 0x10, ///< 2nd pinmux location + ///< For SDIO: enable SD_CLK/SD_CMD/SD_D[0..3] on MC[16..21] (C_GPIO[16..21]) (SDIO only has one pinmux pad group) + ///< For SDIO2: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[22..27] (C_GPIO[22..27]) (SDIO2 only has one pinmux pad group) + ///< For SDIO3: enable SDIO_CLK/SDIO_CMD/SDIO_D[0..3] on MC[0..3]/MC9/MC11 (C_GPIO[0..3], 9, 11) + ///< When 8 bits, enable MC[0..7]/MC9/MC11 (C_GPIO[0..7], 9, 11) + + ENUM_DUMMY4WORD(PIN_SDIO_CFG) +} PIN_SDIO_CFG; + +/** + PIN config for NAND + + @note For pinmux_init() with PIN_FUNC_NAND.\n + For example, you can use {PIN_FUNC_NAND, PIN_NAND_CFG_1CS} to declare NAND with 1 CS. +*/ +typedef enum +{ + PIN_NAND_CFG_NONE, + PIN_NAND_CFG_1CS = 0x01, ///< 1 chip select. Enable NAND_D[0..7]/NAND_CS0/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..8], C_GPIO[10..15]) + PIN_NAND_CFG_2CS = 0x02, ///< 2 chip select. Enable NAND_D[0..7]/NAND_CS[0..1]/NAND_WE/NAND_RE/NAND_CLE/NAND_ALE/NAND_WP/NAND_RDY on MC[0..8]/MC[10..15] (C_GPIO[0..15]) + PIN_NAND_CFG_SPI_NAND = 0x4, ///< Virtual enum for project layer configuration + PIN_NAND_CFG_SPI_NOR = 0x8, ///< Virtual enum for project layer configuration + ENUM_DUMMY4WORD(PIN_NAND_CFG) +} PIN_NAND_CFG; + +/** + PIN config for Sensor + + @note For pinmux_init() with PIN_FUNC_SENSOR.\n + For example, you can use {PIN_FUNC_SENSOR, PIN_SENSOR_CFG_10BITS|PIN_SENSOR_CFG_SHUTTER|PIN_SENSOR_CFG_MCLK}\n + to declare sensor interface is 10 bits sensor, has SHUTTER and MCLK. +*/ +typedef enum +{ + PIN_SENSOR_CFG_NONE, + PIN_SENSOR_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SN_D[4..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[1..4]N/HSI_D[1..4]P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_10BITS = 0x02, ///< 10 bits sensor. Enable SN_D[2..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P0/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_12BITS = 0x04, ///< 12 bits sensor. Enable SN_D[0..11]/SN_PXCLK/SN_VD/SN_HD on HSI_D[0..4]N/HSI_D[0..4]P/HSI_CK0N/HSI_CK0P/SN_PXCLK/SN_VD/SN_HD (S_GPI[1..3]/S_GPI[1..3]) + PIN_SENSOR_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS = 0x40, ///< LVDS sensor PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + + PIN_SENSOR_CFG_SHUTTER = 0x100, ///< Enable SN_SHUTTER on SN_GPIO[10] (SN_GPIO[10]) + PIN_SENSOR_CFG_MCLK = 0x200, ///< Enable SN_MCLK on SN_MCLK (S_GPIO[0]) + PIN_SENSOR_CFG_MCLK2 = 0x400, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR_CFG_MES0 = 0x800, ///< Enable ME_SHUT0 on PWM0 (P_GPIO[0]) + PIN_SENSOR_CFG_MES0_2ND = 0x1000, ///< Enable (2nd) ME_SHUT0 on PWM16 (P_GPIO[16]) + PIN_SENSOR_CFG_MES1 = 0x2000, ///< Enable ME_SHUT1 on PWM1 (P_GPIO[1]) + PIN_SENSOR_CFG_MES1_2ND = 0x4000, ///< Enable (2nd) ME_SHUT1 on PWM17 (P_GPIO[17]) + PIN_SENSOR_CFG_FLCTR = 0x8000, ///< Enable SN_FLCTR on SN_FLCTR (P_GPIO[40]) + PIN_SENSOR_CFG_STROBE = 0x10000, ///< Enable SN_FLASH on SN_GPIO[9] (SN_GPIO[9]) + PIN_SENSOR_CFG_SPCLK = 0x20000, ///< Enable SP_CLK on SN_SPCLK (P_GPIO[20]) + PIN_SENSOR_CFG_SPCLK_2ND = 0x40000, ///< Enable SP_CLK on LCD27 (L_GPIO[27]) + PIN_SENSOR_CFG_SP2CLK = 0x80000, ///< Enable SP2_CLK on REMOTE_RX(P_GPIO[39]) + PIN_SENSOR_CFG_SP2CLK_2ND = 0x100000,///< Enable SP2_CLK on SBCS3 (P_GPIO[24]) + PIN_SENSOR_CFG_MES2 = 0x200000, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR_CFG_MES2_2ND = 0x400000, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR_CFG_MES3 = 0x800000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR_CFG_MES3_2ND = 0x1000000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + PIN_SENSOR_CFG_LOCKN = 0x2000000, ///< Enable LOCKN on PGPIO30 + PIN_SENSOR_CFG_LOCKN2= 0x4000000, ///< Enable LOCKN2 on PGPIO31 + + + ENUM_DUMMY4WORD(PIN_SENSOR_CFG) +} PIN_SENSOR_CFG; + +/** + PIN config for Sensor2 + + @note For pinmux_init() with PIN_FUNC_SENSOR2.\n + For example, you can use {PIN_FUNC_SENSOR2, PIN_SENSOR2_CFG_CCIR8BITS}\n + to declare sensor2 interface connect a CCIR 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR2_CFG_NONE, + PIN_SENSOR2_CFG_CCIR8BITS = 0x08, ///< Backward compatible + PIN_SENSOR2_CFG_CCIR16BITS = 0x10, ///< Backward compatible + PIN_SENSOR2_CFG_MIPI = 0x20, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS = 0x40, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR2_CFG_LVDS_VDHD = 0x80, ///< Backward compatible + PIN_SENSOR2_CFG_10BITS = 0x100, ///< Backward compatible + + PIN_SENSOR2_CFG_MCLK2 = 0x200, ///< Enable SN_MCLK2 on SBCS0 (S_GPIO[4]) + PIN_SENSOR2_CFG_MES2 = 0x400, ///< Enable ME_SHUT2 on PWM2 (P_GPIO[2]) + PIN_SENSOR2_CFG_MES2_2ND = 0x800, ///< Enable (2nd) ME_SHUT2 on PWM18 (P_GPIO[18]) + PIN_SENSOR2_CFG_MES3 = 0x1000, ///< Enable ME_SHUT3 on PWM3 (P_GPIO[3]) + PIN_SENSOR2_CFG_MES3_2ND = 0x2000, ///< Enable (2nd) ME_SHUT3 on PWM19 (P_GPIO[19]) + + ENUM_DUMMY4WORD(PIN_SENSOR2_CFG) +} PIN_SENSOR2_CFG; + +/** + PIN config for Sensor3 + + @note For pinmux_init() with PIN_FUNC_SENSOR3.\n + For example, you can use {PIN_FUNC_SENSOR3, PIN_SENSOR3_CFG_8BITS}\n + to declare sensor3 interface connect a 8 bits sensor. +*/ +typedef enum +{ + PIN_SENSOR3_CFG_NONE, + PIN_SENSOR3_CFG_8BITS = 0x01, ///< 8 bits sensor. Enable SIE3[0..7]/SIE3_PXCEL/SIE3_VD/SIE3_HD on P_GPIO[0..10] + PIN_SENSOR3_CFG_10BITS = 0x02, ///< 10 bits sensor. + PIN_SENSOR3_CFG_12BITS = 0x04, ///< 12 bits sensor. + PIN_SENSOR3_CFG_16BITS = 0x08, ///< 16 bits sensor. + PIN_SENSOR3_CFG_MIPI = 0x10, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR3_CFG_LVDS = 0x20, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR3_CFG_MCLK2 = 0x100, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR3_CFG) +} PIN_SENSOR3_CFG; + +/** + PIN config for Sensor4 + + @note For pinmux_init() with PIN_FUNC_SENSOR4.\n + For example, you can use {PIN_FUNC_SENSOR4, xxxx} +*/ +typedef enum +{ + PIN_SENSOR4_CFG_NONE, + PIN_SENSOR4_CFG_8BITS = 0x01, ///< Backward compatible + PIN_SENSOR4_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR4_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR4_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR4_CFG) +} PIN_SENSOR4_CFG; + +/** + PIN config for Sensor5 + + @note For pinmux_init() with PIN_FUNC_SENSOR5.\n + For example, you can use {PIN_FUNC_SENSOR5, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR5_CFG_NONE, + PIN_SENSOR5_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR5_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR5_CFG_MCLK2 = 0x10, ///< MCLK2 + + ENUM_DUMMY4WORD(PIN_SENSOR5_CFG) +} PIN_SENSOR5_CFG; + +/** + PIN config for Sensor6 + + @note For pinmux_init() with PIN_FUNC_SENSOR6.\n + For example, you can use {PIN_FUNC_SENSOR6, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR6_CFG_NONE, + PIN_SENSOR6_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR6_CFG_16BITS= 0x02, ///< 16 bit sensor + PIN_SENSOR6_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR6_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR6_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR6_CFG) +} PIN_SENSOR6_CFG; + +/** + PIN config for Sensor7 + + @note For pinmux_init() with PIN_FUNC_SENSOR7.\n + For example, you can use {PIN_FUNC_SENSOR7, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR7_CFG_NONE, + PIN_SENSOR7_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR7_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR7_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR7_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR7_CFG) +} PIN_SENSOR7_CFG; + +/** + PIN config for Sensor8 + + @note For pinmux_init() with PIN_FUNC_SENSOR8.\n + For example, you can use {PIN_FUNC_SENSOR8, xxxx}\n +*/ +typedef enum +{ + PIN_SENSOR8_CFG_NONE, + PIN_SENSOR8_CFG_8BITS = 0x01, ///< 8 bit sensor + PIN_SENSOR8_CFG_MIPI = 0x04, ///< MIPI sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + PIN_SENSOR8_CFG_LVDS = 0x08, ///< LVDS sensor. PIN/PAD is configured by PIN_FUNC_MIPI_LVDS group. + + PIN_SENSOR8_CFG_MCLK2 = 0x10, ///< + + ENUM_DUMMY4WORD(PIN_SENSOR8_CFG) +} PIN_SENSOR8_CFG; + + +/** + PIN config for MIPI/LVDS + + @note For pinmux_init() with PIN_FUNC_MIPI_LVDS.\n + For example, you can use {PIN_FUNC_MIPI_LVDS, PIN_MIPI_LVDS_CFG_CLK0|PIN_MIPI_LVDS_CFG_DAT0|PIN_MIPI_LVDS_CFG_DAT4|PIN_MIPI_LVDS_CFG_DAT7|PIN_MIPI_LVDS_CFG_DAT9}\n + to declare LVDS/MIPI connect sensor with CLK0/D0/D4/D7/D9 lanes. +*/ +typedef enum +{ + PIN_MIPI_LVDS_CFG_NONE, + + PIN_MIPI_LVDS_CFG_CLK0 = 0x1, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK1 = 0x2, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK2 = 0x4, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK3 = 0x8, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK4 = 0x10, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK5 = 0x20, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK6 = 0x40, ///< CLK lane 0. Enable HSI_CK0N/HSI_CK0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_CLK7 = 0x80, ///< CLK lane 1. Enable HSI_CK1N/HSI_CK1P for LVDS/CSI/CSI2. + + PIN_MIPI_LVDS_CFG_DAT0 = 0x100, ///< DATA lane 0. Enable HSI_D0N/HSI_D0P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT1 = 0x200, ///< DATA lane 1. Enable HSI_D1N/HSI_D1P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT2 = 0x400, ///< DATA lane 2. Enable HSI_D2N/HSI_D2P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT3 = 0x800, ///< DATA lane 3. Enable HSI_D3N/HSI_D3P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT4 = 0x1000, ///< DATA lane 4. Enable HSI_D4N/HSI_D4P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT5 = 0x2000, ///< DATA lane 5. Enable HSI_D5N/HSI_D5P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT6 = 0x4000, ///< DATA lane 6. Enable HSI_D6N/HSI_D6P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT7 = 0x8000, ///< DATA lane 7. Enable HSI_D7N/HSI_D7P for LVDS/CSI/CSI2. + PIN_MIPI_LVDS_CFG_DAT8 = 0x10000, ///< Backward compatible + PIN_MIPI_LVDS_CFG_DAT9 = 0x20000, ///< Backward compatible + + ENUM_DUMMY4WORD(PIN_MIPI_LVDS_CFG) +} PIN_MIPI_LVDS_CFG; + +/** + PIN config for I2C + + @note For pinmux_init() with PIN_FUNC_I2C.\n + For example, you can use {PIN_FUNC_I2C, PIN_I2C_CFG_CH1|PIN_I2C_CFG_CH1_2ND_PINMUX}\n + to declare I2C channel1 both output to 1st and 2nd pinmux location. +*/ +typedef enum +{ + PIN_I2C_CFG_NONE, + PIN_I2C_CFG_CH1 = 0x1, ///< Enable channel 1. + PIN_I2C_CFG_CH1_2ND_PINMUX = 0x2, ///< Enable 2nd pinmux of channel 1. + PIN_I2C_CFG_CH2 = 0x10, ///< Enable channel 2. + PIN_I2C_CFG_CH2_2ND_PINMUX = 0x20, ///< Enable 2nd pinmux of channel 2. + PIN_I2C_CFG_CH3 = 0x100, ///< Enable channel 3. + PIN_I2C_CFG_CH3_2ND_PINMUX = 0x200, ///< Enable 2nd pinmux of channel 3. + PIN_I2C_CFG_CH3_3RD_PINMUX = 0x400, ///< Enable 3nd pinmux of channel 3. + PIN_I2C_CFG_CH4 = 0x1000, ///< Enable channel 4. + PIN_I2C_CFG_CH4_2ND_PINMUX = 0x2000, ///< Enable 2nd pinmux of channel 4. + PIN_I2C_CFG_CH4_3RD_PINMUX = 0x4000, ///< Enable 3nd pinmux of channel 4. + PIN_I2C_CFG_CH4_4TH_PINMUX = 0x8000, ///< Enable 4th pinmux of channel 4. + PIN_I2C_CFG_CH5 = 0x10000, ///< Enable channel 5. + PIN_I2C_CFG_CH5_2ND_PINMUX = 0x20000, ///< Enable 2nd pinmux of channel 5. + + ENUM_DUMMY4WORD(PIN_I2C_CFG) +} PIN_I2C_CFG; + +/** + PIN config for SIF + + *note For pinmux_init() with PIN_FUNC_SIF.\n + For example, you can use {PIN_FUNC_SIF, PIN_SIF_CFG_CH0|PIN_SIF_CFG_CH2}\n + to declare SIF channel0 and channel2 pinmux are enabled. +*/ +typedef enum +{ + PIN_SIF_CFG_NONE, + + PIN_SIF_CFG_CH0 = 0x01, ///< Enable SIF channel 0. Enable SN_CS0/SN_SCK0/SN_DAT0 (L_GPIO 27/28/29) + PIN_SIF_CFG_CH0_2ND_PINMUX = 0x02, ///< Enable SIF channel 0 2'nd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 16/18/19) + PIN_SIF_CFG_CH0_3RD_PINMUX = 0x04, ///< Enable SIF channel 0 3'rd pinmux. Enable SN_CS0/SN_SCK0/SN_SAT0 (P_GPIO 17/18/19) + + PIN_SIF_CFG_CH1 = 0x08, ///< Enable SIF channel 1. Enable SN_CS1/SN_SCK1/SN_DAT1 (L_GPIO 30/31/32) + PIN_SIF_CFG_CH1_2ND_PINMUX = 0x10, ///< Backward compatible + + PIN_SIF_CFG_CH2 = 0x20, ///< Enable SIF channel 2. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 30/32/33) + PIN_SIF_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable SIF channel 2 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 8/10/11) + + PIN_SIF_CFG_CH3 = 0x80, ///< Enable SIF channel 3. Enable SB_CS3/SB_CK23/SB_DAT23 (P_GPIO 31/32/33) + PIN_SIF_CFG_CH3_2ND_PINMUX = 0x100, ///< Enable SIF channel 3 2'nd pinmux. Enable SB_CS2/SB_CK23/SB_DAT23 (P_GPIO 9/10/11) + + PIN_SIF_CFG_CH4 = 0x200, ///< Enable SIF channel 4. Enable SB_CS4/SB_CK45/SB_DAT45 (P_GPIO 24/26/27) + + PIN_SIF_CFG_CH5 = 0x400, ///< Enable SIF channel 5. Enable SB_CS5/SB_CK45/SB_DAT45 (P_GPIO 25/26/27) + + PIN_SIF_CFG_CH6 = 0x800, ///< Enable SIF channel 6. Enable SB_CS6/SB_CK67/SB_DAT67 (S_GPIO 8/9/10) + + PIN_SIF_CFG_CH7 = 0x1000, ///< Enable SIF channel 7. Enable SB_CS7/SB_CK67/SB_DAT67 (S_GPIO 11/8/9) + + ENUM_DUMMY4WORD(PIN_SIF_CFG) +} PIN_SIF_CFG; + +/** + PIN config for UART + + @note For pinmux_init() with PIN_FUNC_UART.\n + For example, you can use {PIN_FUNC_UART, PIN_UART_CFG_CH1}\n + to declare UART1 pinmux is enabled. +*/ +typedef enum +{ + PIN_UART_CFG_NONE, + + PIN_UART_CFG_CH1 = 0x01, ///< Enable channel 1. Enable UART TX and RX + PIN_UART_CFG_CH1_TX = 0x02, ///< Enalbe channel 1. Enable only UART_TX + + PIN_UART_CFG_CH2 = 0x04, ///< Enable channel 2. Enable UART2 TX and RX + PIN_UART_CFG_CH2_CTSRTS = 0x08, ///< Enable channel 2 HW handshake. Enable UART2 CTS and RTS + PIN_UART_CFG_CH2_2ND = 0x10, ///< Enable channel 2 to 2ND pinmux (UART2_2) + + PIN_UART_CFG_CH3 = 0x20, ///< Enable channel 3. Enable UART3 TX and RX + PIN_UART_CFG_CH3_CTSRTS = 0x40, ///< Enable channel 3 HW handshake. Enable UART3 CTS and RTS + PIN_UART_CFG_CH3_2ND = 0x80, ///< Enable channel 3 to 2ND pinmux (UART3_2) + + PIN_UART_CFG_CH4 = 0x100, ///< Enable channel 4. Enable UART4 TX and RX + PIN_UART_CFG_CH4_CTSRTS = 0x200, ///< Enable channel 4 HW handshake. Enable UART4 CTS and RTS + PIN_UART_CFG_CH4_2ND = 0x400, ///< Enable channel 4 to 2ND pinmux (UART4_2) + + ENUM_DUMMY4WORD(PIN_UART_CFG) +} PIN_UART_CFG; + +/** + PIN config for SPI + + @note For pinmux_init() with PIN_FUNC_SPI.\n + For example, you can use {PIN_FUNC_SPI, PIN_SPI_CFG_CH1|PIN_SPI_CFG_CH3}\n + to declare SPI channel1 and channel3 are enabled. +*/ +typedef enum +{ + PIN_SPI_CFG_NONE, + + PIN_SPI_CFG_CH1 = 0x1, ///< Enable channel 1. Enable SPI_DO/SPI_CLK/SPI_CS on MC[0]/MC[2]/MC8 (C_GPIO[0]/C_GPIO[2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_2BITS = 0x2, ///< Enable channel 1 with 2 bits mode. Enable SPI_DO/SPI_DI/SPI_CLK/SPI_CS on MC[0..2]/MC8 (C_GPIO[0..2]/C_GPIO[8]) + PIN_SPI_CFG_CH1_4BITS = 0x4, ///< Backward compatible + PIN_SPI_CFG_CH1_2ND_PINMUX = 0x8, ///< Enable 2nd pinmux of channel 1. + + PIN_SPI_CFG_CH2 = 0x10, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO on SPI_CS/SPI_CLK/SPI_DO(P_GPIO[35..37]) + PIN_SPI_CFG_CH2_2BITS = 0x20, ///< Enable channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on SPI_CS/SPI_CLK/SPI_DO/SPI_DI(P_GPIO[35..38]) + PIN_SPI_CFG_CH2_2ND_PINMUX = 0x40, ///< Enable 2nd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + PIN_SPI_CFG_CH2_3RD_PINMUX = 0x80, ///< Enable 3rd pinmux of channel 2. Enable SPI2_CS/SPI2_CLK/SPI2_DO/SPI2_DI on (P_GPIO[16..19]) + + + PIN_SPI_CFG_CH3 = 0x100, ///< Enable channel 3. Eanble SPI3_CS/SPI3_CLK/SPI3_DO on SB_CS2/SB_CK23/SB_DAT23 (P_GPIO[23]/P_GPIO[25..26]) + PIN_SPI_CFG_CH3_2BITS = 0x200, ///< Enable channel 3. Eanble SPI3_CS/SPI3_DI/SPI3_CLK/SPI3_DO on SB_CS2/SB_CS3/SB_CK23/SB_DAT23 (P_GPIO[23..26]) + PIN_SPI_CFG_CH3_2ND_PINMUX = 0x400, ///< Enable 2nd pinmux of channel 3. Enable SPI3_CLK/SPI3_CS/SPI3_DO/SPI3_DI on PWM[12..15] (P_GPIO[12..15]) + PIN_SPI_CFG_CH3_3RD_PINMUX = 0x800, ///< Backward compatible + PIN_SPI_CFG_CH3_RDY = 0x1000, + PIN_SPI_CFG_CH3_RDY_2ND_PINMUX = 0x2000, + + PIN_SPI_CFG_CH4 = 0x10000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_CLK/SPI4_DO on MC[28..29]/MC[31] (C_GPIO[28..29]/C_GPIO[31]) + PIN_SPI_CFG_CH4_2BITS = 0x20000, ///< Enable channel 4. Eanble SPI4_CS/SPI4_DI/SPI4_CLK/SPI4_DO on MC[28..31] (C_GPIO[28..31]) + PIN_SPI_CFG_CH4_2ND_PINMUX = 0x40000, ///< Enable 2nd pinmux of channel 4. Enable SPI4_CLK/SPI4_CS/SPI4_DO/SPI4_DI on PWM[8..11] (P_GPIO[8..11]) + PIN_SPI_CFG_CH4_RDY = 0x80000, ///< Backward compatible + PIN_SPI_CFG_CH4_3RD_PINMUX = 0x100000, ///< Enable 3rd pinmux of channel 4. + + PIN_SPI_CFG_CH5 = 0x1000000,///< Backward compatible + PIN_SPI_CFG_CH5_2BITS = 0x2000000,///< Backward compatible + PIN_SPI_CFG_CH5_2ND_PINMUX = 0x4000000,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_SPI_CFG) +} PIN_SPI_CFG; + +/** + PIN config for REMOTE + + @note For pinmux_init() with PIN_FUNC_REMOTE.\n + For example, you can use {PIN_FUNC_REMOTE, PIN_REMOTE_CFG_CH1}\n + to declare remote pinmux is enabled. +*/ +typedef enum +{ + PIN_REMOTE_CFG_NONE, + PIN_REMOTE_CFG_CH1, ///< Enable remote rx channel 1. Enable REMOTE_RX (on P_GPIO[39]) + + ENUM_DUMMY4WORD(PIN_REMOTE_CFG) +} PIN_REMOTE_CFG; + +/** + PIN config for PWM + + @note For pinmux_init() with PIN_FUNC_PWM.\n + For example, you can use {PIN_FUNC_PWM, PIN_PWM_CFG_PWM0|PIN_PWM_CFG_PWM1|PIN_PWM_CFG_PWM2|PIN_PWM_CFG_PWM3}\n + to declare your system need PWM channel0/1/2/3. +*/ +typedef enum +{ + PIN_PWM_CFG_NONE, + PIN_PWM_CFG_PWM0 = 0x01, ///< Enable PWM0 (on P_GPIO[0]) + PIN_PWM_CFG_PWM1 = 0x02, ///< Enable PWM1 (on P_GPIO[1]) + PIN_PWM_CFG_PWM2 = 0x04, ///< Enable PWM2 (on P_GPIO[2]) + PIN_PWM_CFG_PWM3 = 0x08, ///< Enable PWM3 (on P_GPIO[3]) + PIN_PWM_CFG_PWM4 = 0x10, ///< Enable PWM4 (on P_GPIO[4]) + PIN_PWM_CFG_PWM5 = 0x20, ///< Enable PWM5 (on P_GPIO[5]) + PIN_PWM_CFG_PWM6 = 0x40, ///< Enable PWM6 (on P_GPIO[6]) + PIN_PWM_CFG_PWM7 = 0x80, ///< Enable PWM7 (on P_GPIO[7]) + PIN_PWM_CFG_PWM8 = 0x100, ///< Enable PWM8 (on P_GPIO[8]) + PIN_PWM_CFG_PWM9 = 0x200, ///< Enable PWM9 (on P_GPIO[9]) + PIN_PWM_CFG_PWM10= 0x400, ///< Enable PWM10 (on P_GPIO[10]) + PIN_PWM_CFG_PWM11= 0x800, ///< Enable PWM11 (on P_GPIO[11]) + PIN_PWM_CFG_PWM12= 0x1000, ///< Enable PWM12 (on P_GPIO[12]) + PIN_PWM_CFG_PWM13= 0x2000, ///< Enable PWM13 (on P_GPIO[13]) + PIN_PWM_CFG_PWM14= 0x4000, ///< Enable PWM14 (on P_GPIO[14]) + PIN_PWM_CFG_PWM15= 0x8000, ///< Enable PWM15 (on P_GPIO[15]) + PIN_PWM_CFG_PWM16= 0x10000, ///< Enable PWM16 (on P_GPIO[16]) + PIN_PWM_CFG_PWM17= 0x20000, ///< Enable PWM17 (on P_GPIO[17]) + PIN_PWM_CFG_PWM18= 0x40000, ///< Enable PWM18 (on P_GPIO[18]) + PIN_PWM_CFG_PWM19= 0x80000, ///< Enable PWM19 (on P_GPIO[19]) + + PIN_PWM_CFG_CCNT = 0x1000000, ///< Enable PICNT_1 + PIN_PWM_CFG_CCNT_2ND = 0x2000000, ///< Enable PICNT_2 + PIN_PWM_CFG_CCNT2 = 0x4000000, ///< Enable PICNT2_1 + PIN_PWM_CFG_CCNT2_2ND = 0x8000000, ///< Enable PICNT2_2 + PIN_PWM_CFG_CCNT3 = 0x10000000, ///< Enable PICNT3 + PIN_PWM_CFG_CCNT3_2ND = 0x20000000, ///< Enable PICNT3_2 + PIN_PWM_CFG_CCNT4 = 0x40000000, ///< Enable PICNT4_1 + PIN_PWM_CFG_CCNT4_2ND = 0x80000000, ///< Enable PICNT4_2 + + ENUM_DUMMY4WORD(PIN_PWM_CFG) +} PIN_PWM_CFG; + +/** + PIN config for AUDIO + + @note For pinmux_init() with PIN_FUNC_AUDIO.\n + For example, you can use {PIN_FUNC_AUDIO, PIN_AUDIO_CFG_I2S|PIN_AUDIO_CFG_MCLK}\n + to declare pinmux of I2S and I2S MCLK are enabled. +*/ +typedef enum +{ + PIN_AUDIO_CFG_NONE, + PIN_AUDIO_CFG_I2S = 0x01, ///< Enable I2S channel. Enable I2S_BCK/I2S_FCK/I2S_DO/I2S_DI/ (on P_GPIO[31..34]) + PIN_AUDIO_CFG_I2S_2ND_PINMUX = 0x02,///< Backward compatible + + PIN_AUDIO_CFG_MCLK = 0x10, ///< Enable audio MCLK. Enable I2S_MCLK (on P_GPIO[20]) + PIN_AUDIO_CFG_MCLK_2ND_PINMUX = 0x20,///< Backward compatible + + ENUM_DUMMY4WORD(PIN_AUDIO_CFG) +} PIN_AUDIO_CFG; + +/** + PIN config of LCD modes + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD | PINMUX_LCDMODE_RGB_SERIAL}\n + to tell display object that PIN_FUNC_LCD is located on primary LCD pinmux,\n + and it's LCD mode is RGB serial. +*/ +typedef enum +{ + PINMUX_LCDMODE_RGB_SERIAL = 0, ///< LCD MODE is RGB Serial or UPS051 + PINMUX_LCDMODE_RGB_PARALL = 1, ///< LCD MODE is RGB Parallel (888) + PINMUX_LCDMODE_YUV640 = 2, ///< LCD MODE is YUV640 + PINMUX_LCDMODE_YUV720 = 3, ///< LCD MODE is YUV720 + PINMUX_LCDMODE_RGBD360 = 4, ///< LCD MODE is RGB Dummy 360 + PINMUX_LCDMODE_RGBD320 = 5, ///< LCD MODE is RGB Dummy 320 + PINMUX_LCDMODE_RGB_THROUGH = 6, ///< LCD MODE is RGB through mode + PINMUX_LCDMODE_CCIR601 = 7, ///< LCD MODE is CCIR601 + PINMUX_LCDMODE_CCIR656 = 8, ///< LCD MODE is CCIR656 + PINMUX_LCDMODE_RGB_PARALL666 = 9, ///< LCD MODE is RGB Parallel 666 + PINMUX_LCDMODE_RGB_PARALL565 = 10, ///< LCD MODE is RGB Parallel 565 + PINMUX_LCDMODE_RGB_PARALL_DELTA = 11, ///< LCD MODE is RGB Parallel Delta + PINMUX_LCDMODE_MIPI = 12, ///< LCD MODE is MIPI Display + + PINMUX_LCDMODE_MI_OFFSET = 32, ///< Memory LCD MODE offset + PINMUX_LCDMODE_MI_FMT0 = 32+0, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT1 = 32+1, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT2 = 32+2, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT3 = 32+3, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT4 = 32+4, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT5 = 32+5, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT6 = 32+6, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT7 = 32+7, ///< LCD MODE is Memory(Parallel Interface) 9bits + PINMUX_LCDMODE_MI_FMT8 = 32+8, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT9 = 32+9, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT10 = 32+10, ///< LCD MODE is Memory(Parallel Interface) 18bits + PINMUX_LCDMODE_MI_FMT11 = 32+11, ///< LCD MODE is Memory(Parallel Interface) 8bits + PINMUX_LCDMODE_MI_FMT12 = 32+12, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT13 = 32+13, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_FMT14 = 32+14, ///< LCD MODE is Memory(Parallel Interface) 16bits + PINMUX_LCDMODE_MI_SERIAL_BI = 32+20, ///< LCD MODE is Serial Interface bi-direction + PINMUX_LCDMODE_MI_SERIAL_SEP = 32+21, ///< LCD MODE is Serial Interface separation + + PINMUX_LCDMODE_AUTO_PINMUX = 0x01<<22, ///< Set display device to GPIO mode when display device is closed. Select this filed will inform display object to switch to GPIO when display device is closed. + + + PINMUX_HDMIMODE_OFFSET = 64, ///< HDMI MODE offset + PINMUX_HDMIMODE_640X480P60 = 64+1, ///< HDMI Video format is 640x480 & Progressive 60fps + PINMUX_HDMIMODE_720X480P60 = 64+2, ///< HDMI Video format is 720x480 & Progressive 60fps & 4:3 + PINMUX_HDMIMODE_720X480P60_16X9 = 64+3, ///< HDMI Video format is 720x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1280X720P60 = 64+4, ///< HDMI Video format is 1280x720 & Progressive 60fps + PINMUX_HDMIMODE_1920X1080I60 = 64+5, ///< HDMI Video format is 1920x1080 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60 = 64+6, ///< HDMI Video format is 720x480 & Interlaced 60fps + PINMUX_HDMIMODE_720X480I60_16X9 = 64+7, ///< HDMI Video format is 720x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_720X240P60 = 64+8, ///< HDMI Video format is 720x240 & Progressive 60fps + PINMUX_HDMIMODE_720X240P60_16X9 = 64+9, ///< HDMI Video format is 720x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480I60 = 64+10, ///< HDMI Video format is 1440x480 & Interlaced 60fps + PINMUX_HDMIMODE_1440X480I60_16X9 = 64+11, ///< HDMI Video format is 1440x480 & Interlaced 60fps & 16:9 + PINMUX_HDMIMODE_1440X240P60 = 64+12, ///< HDMI Video format is 1440x240 & Progressive 60fps + PINMUX_HDMIMODE_1440X240P60_16X9 = 64+13, ///< HDMI Video format is 1440x240 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_1440X480P60 = 64+14, ///< HDMI Video format is 1440x480 & Progressive 60fps + PINMUX_HDMIMODE_1440X480P60_16X9 = 64+15, ///< HDMI Video format is 1440x480 & Progressive 60fps & 16:9 + PINMUX_HDMIMODE_720X576P50 = 64+17, ///< HDMI Video format is 720x576 & Progressive 50fps + PINMUX_HDMIMODE_720X576P50_16X9 = 64+18, ///< HDMI Video format is 720x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1280X720P50 = 64+19, ///< HDMI Video format is 1280x720 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080I50 = 64+20, ///< HDMI Video format is 1920x1080 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50 = 64+21, ///< HDMI Video format is 720x576 & Interlaced 50fps + PINMUX_HDMIMODE_720X576I50_16X9 = 64+22, ///< HDMI Video format is 720x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_720X288P50 = 64+23, ///< HDMI Video format is 720x288 & Progressive 50fps + PINMUX_HDMIMODE_720X288P50_16X9 = 64+24, ///< HDMI Video format is 720x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576I50 = 64+25, ///< HDMI Video format is 1440x576 & Interlaced 50fps + PINMUX_HDMIMODE_1440X576I50_16X9 = 64+26, ///< HDMI Video format is 1440x576 & Interlaced 50fps & 16:9 + PINMUX_HDMIMODE_1440X288P50 = 64+27, ///< HDMI Video format is 1440x288 & Progressive 50fps + PINMUX_HDMIMODE_1440X288P50_16X9 = 64+28, ///< HDMI Video format is 1440x288 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1440X576P50 = 64+29, ///< HDMI Video format is 1440x576 & Progressive 50fps + PINMUX_HDMIMODE_1440X576P50_16X9 = 64+30, ///< HDMI Video format is 1440x576 & Progressive 50fps & 16:9 + PINMUX_HDMIMODE_1920X1080P50 = 64+31, ///< HDMI Video format is 1920x1080 & Progressive 50fps + PINMUX_HDMIMODE_1920X1080P24 = 64+32, ///< HDMI Video format is 1920x1080 & Progressive 24fps + PINMUX_HDMIMODE_1920X1080P25 = 64+33, ///< HDMI Video format is 1920x1080 & Progressive 25fps + PINMUX_HDMIMODE_1920X1080P30 = 64+34, ///< HDMI Video format is 1920x1080 & Progressive 30fps + PINMUX_HDMIMODE_1920X1080I50_VT1250 = 64+39, ///< HDMI Video format is 1920x1080 & Interlaced 50fps & V-total is 1250 lines + PINMUX_HDMIMODE_1920X1080I100 = 64+40, ///< HDMI Video format is 1920x1080 & Interlaced 100fps + PINMUX_HDMIMODE_1280X720P100 = 64+41, ///< HDMI Video format is 1280X720 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100 = 64+42, ///< HDMI Video format is 720X576 & Progressive 100fps + PINMUX_HDMIMODE_720X576P100_16X9 = 64+43, ///< HDMI Video format is 720X576 & Progressive 100fps & 16:9 + PINMUX_HDMIMODE_720X576I100 = 64+44, ///< HDMI Video format is 720X576 & Interlaced 100fps + PINMUX_HDMIMODE_720X576I100_16X9 = 64+45, ///< HDMI Video format is 720X576 & Interlaced 100fps & 16:9 + PINMUX_HDMIMODE_1920X1080I120 = 64+46, ///< HDMI Video format is 1920X1080 & Interlaced 120fps + PINMUX_HDMIMODE_1280X720P120 = 64+47, ///< HDMI Video format is 1280X720 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120 = 64+48, ///< HDMI Video format is 720X480 & Progressive 120fps + PINMUX_HDMIMODE_720X480P120_16X9 = 64+49, ///< HDMI Video format is 720X480 & Progressive 120fps & 16:9 + PINMUX_HDMIMODE_720X480I120 = 64+50, ///< HDMI Video format is 720X480 & Interlaced 120fps + PINMUX_HDMIMODE_720X480I120_16X9 = 64+51, ///< HDMI Video format is 720X480 & Interlaced 120fps & 16:9 + PINMUX_HDMIMODE_720X576P200 = 64+52, ///< HDMI Video format is 720X576 & Progressive 200fps + PINMUX_HDMIMODE_720X576P200_16X9 = 64+53, ///< HDMI Video format is 720X576 & Progressive 200fps & 16:9 + PINMUX_HDMIMODE_720X576I200 = 64+54, ///< HDMI Video format is 720X576 & Interlaced 200fps + PINMUX_HDMIMODE_720X576I200_16X9 = 64+55, ///< HDMI Video format is 720X576 & Interlaced 200fps & 16:9 + PINMUX_HDMIMODE_720X480P240 = 64+56, ///< HDMI Video format is 720X480 & Progressive 240fps + PINMUX_HDMIMODE_720X480P240_16X9 = 64+57, ///< HDMI Video format is 720X480 & Progressive 240fps & 16:9 + PINMUX_HDMIMODE_720X480I240 = 64+58, ///< HDMI Video format is 720X480 & Interlaced 240fps + PINMUX_HDMIMODE_720X480I240_16X9 = 64+59, ///< HDMI Video format is 720X480 & Interlaced 240fps & 16:9 + + PINMUX_DSI_1_LANE_CMD_MODE_RGB565 = 128+0, ///< DSI command mode with RGB565 format + PINMUX_DSI_1_LANE_CMD_MODE_RGB666P = 128+1, ///< DSI command mode with RGB666 packed + PINMUX_DSI_1_LANE_CMD_MODE_RGB666L = 128+2, ///< DSI command mode with RGB666 loosely + PINMUX_DSI_1_LANE_CMD_MODE_RGB888 = 128+3, ///< DSI command mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB565 = 128+4, ///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666P = 128+5, ///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB666L = 128+6, ///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_PULSE_RGB888 = 128+7, ///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB565 = 128+8, ///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666P = 128+9, ///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB666L = 128+10,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_1_LANE_VDO_SYNC_EVENT_RGB888 = 128+11,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_2_LANE_CMD_MODE_RGB565 = 128+12,///< DSI command mode with RGB565 format + PINMUX_DSI_2_LANE_CMD_MODE_RGB666P = 128+13,///< DSI command mode with RGB666 packed + PINMUX_DSI_2_LANE_CMD_MODE_RGB666L = 128+14,///< DSI command mode with RGB666 loosely + PINMUX_DSI_2_LANE_CMD_MODE_RGB888 = 128+15,///< DSI command mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB565 = 128+16,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666P = 128+17,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB666L = 128+18,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_PULSE_RGB888 = 128+19,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB565 = 128+20,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666P = 128+21,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB666L = 128+22,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_2_LANE_VDO_SYNC_EVENT_RGB888 = 128+23,///< DSI video sync event burst mode with RGB888 + + PINMUX_DSI_4_LANE_CMD_MODE_RGB565 = 128+24,///< DSI command mode with RGB565 format + PINMUX_DSI_4_LANE_CMD_MODE_RGB666P = 128+25,///< DSI command mode with RGB666 packed + PINMUX_DSI_4_LANE_CMD_MODE_RGB666L = 128+26,///< DSI command mode with RGB666 loosely + PINMUX_DSI_4_LANE_CMD_MODE_RGB888 = 128+27,///< DSI command mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB565 = 128+28,///< DSI video sync pulse mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666P = 128+29,///< DSI video sync pulse mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB666L = 128+30,///< DSI video sync pulse mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_PULSE_RGB888 = 128+31,///< DSI video sync pulse mode with RGB888 + + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB565 = 128+32,///< DSI video sync event burst mode with RGB565 format + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666P = 128+33,///< DSI video sync event burst mode with RGB666 packed + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB666L = 128+34,///< DSI video sync event burst mode with RGB666 loosely + PINMUX_DSI_4_LANE_VDO_SYNC_EVENT_RGB888 = 128+35,///< DSI video sync event burst mode with RGB888 + + + + ENUM_DUMMY4WORD(PINMUX_LCDINIT) +} PINMUX_LCDINIT; + +/** + PIN config for Parallel MI + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD|PINMUX_PMI_CFG_NORMAL|PINMUX_LCDMODE_MI_FMT0}\n + to tell display object that PIN_FUNC_LCD is bound to MI and format is FMT0,\n + and MI is located at primary location. +*/ +typedef enum +{ + PINMUX_PMI_CFG_NORMAL = 0x00, ///< Normal Parallel MI location (at LCD) + PINMUX_PMI_CFG_2ND_PINMUX = 0x01<<26, ///< Secondary Parallel MI location (at LGPIO[12..25]) + + PINMUX_PMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_PMI_CFG) +} PINMUX_PMI_CFG; + +/** + PIN config for TV/HDMI + + @note For pinmux_init() for PIN_FUNC_TV or PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_TV_HDMI_CFG_NORMAL|PINMUX_HDMIMODE_1280X720P60}\n + to tell display object that HDMI activation will disable PANEL,\n + and HDMI mode is 1280x720 P60. +*/ +typedef enum +{ + PINMUX_TV_HDMI_CFG_GPIO = 0x00, ///< TV activation will disable PINMUX to GPIO + PINMUX_TV_HDMI_CFG_NORMAL = 0x00, ///< TV activation will disable PANEL which shared the same IDE + PINMUX_TV_HDMI_CFG_PINMUX_ON = 0x01<<28, ///< TV activation will keep PINMUX setting + + PINMUX_TV_HDMI_CFG_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_TV_HDMI_CFG) +} PINMUX_TV_HDMI_CFG; + +/** + PIN config for HDMI + + @note For pinmux_init() for PIN_FUNC_HDMI.\n + For example, you can use {PIN_FUNC_HDMI, PINMUX_HDMI_CFG_CEC|PINMUX_TV_HDMI_CFG_NORMAL}\n + to declare HDMI CEC pinmux is enabled. +*/ +typedef enum +{ + PINMUX_HDMI_CFG_GPIO = 0x00, ///< HDMI specific PIN to GPIO + PINMUX_HDMI_CFG_HOTPLUG = 0x01<<26, ///< HDMI HOTPLUG. Enable HDMI_PLUG (on P_GPIO[30]) + PINMUX_HDMI_CFG_CEC = 0x02<<26, ///< HDMI CEC. Enable HDMI_CEC (on P_GPIO[27]) + + PINMUX_HDMI_CFG_MASK = 0x03<<26, + ENUM_DUMMY4WORD(PINMUX_HDMI_CFG) +} PINMUX_HDMI_CFG; + +/** + PIN location of LCD + + @note For pinmux_init() with PIN_FUNC_LCD or PIN_FUNC_LCD2.\n + For example, you can use {PIN_FUNC_LCD, PINMUX_DISPMUX_SEL_LCD2|PINMUX_LCDMODE_XXX}\n + to tell display object that PIN_FUNC_LCD is located on secondary LCD pinmux. +*/ +typedef enum +{ + PINMUX_DISPMUX_SEL_NONE = 0x00<<28, ///< PINMUX none + PINMUX_DISPMUX_SEL_LCD = 0x01<<28, ///< PINMUX at LCD interface + PINMUX_DISPMUX_SEL_LCD2 = 0x02<<28, ///< PINMUX at LCD2 interface + + PINMUX_DISPMUX_SEL_MASK = 0x03<<28, + ENUM_DUMMY4WORD(PINMUX_DISPMUX_SEL) +} PINMUX_DISPMUX_SEL; + +/** + PIN config for ETH + + @note For pinmux_init() for PIN_FUNC_ETH.\n + For example, you can use {PIN_FUNC_ETH, PINMUX_ETH_CFG_MII}\n + to select USB as device. +*/ +typedef enum +{ + PIN_ETH_CFG_NONE = 0x00, ///< PINMUX none + PIN_ETH_CFG_MII = 0x01, ///< ETH MII + PIN_ETH_CFG_RMII = 0x02, ///< ETH RMII + PIN_ETH_CFG_GMII = 0x04, ///< ETH GMII + PIN_ETH_CFG_RGMII = 0x08, ///< ETH RGMII + PIN_ETH_CFG_REVMII_10_100 = 0x10, ///< ETH REVMII_10_100 + PIN_ETH_CFG_REVMII_10_1000 = 0x20, ///< ETH REVMII_10_1000 + + ENUM_DUMMY4WORD(PINMUX_ETH_CFG) +} PINMUX_ETH_CFG; + + +/** + Pinmux Function identifier + + @note For pinmux_getDispMode(), pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_LCD, ///< 1st Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + ///< - @b PINMUX_LCD_SEL_TE_ENABLE + PINMUX_FUNC_ID_LCD2, ///< 2nd Panel (LCD), pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + ///< - @b PINMUX_LCD_SEL_CCIR656 + ///< - @b PINMUX_LCD_SEL_CCIR601 + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_6BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_RGB_8BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_8BITS + ///< - @b PINMUX_LCD_SEL_PARALLE_MI_9BITS + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDIO + ///< - @b PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO + ///< ORed with + ///< - @b PINMUX_LCD_SEL_DE_ENABLE + PINMUX_FUNC_ID_TV, ///< TV, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_HDMI, ///< HDMI, pinmux can be: + ///< - @b PINMUX_LCD_SEL_GPIO + PINMUX_FUNC_ID_SN_MES0, ///< Sensor MES0, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES1, ///< Sensor MES1, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES2, ///< Sensor MES2, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MES3, ///< Sensor MES3, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_FLCTR, ///< Sensor Flash Control, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SN_MCLK, ///< Sensor MCLK, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_SPI2, ///< SPI channel2 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI3, ///< SPI channel3 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI4, ///< SPI channel4 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_SPI5, ///< SPI channel5 pinmux switch, pinmux can be: + ///< - @b PINMUX_SPI_SEL_INACTIVE + ///< - @b PINMUX_SPI_SEL_ACTIVE + PINMUX_FUNC_ID_COUNT, //< Total function count + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID) +} PINMUX_FUNC_ID; + +/** + Pinmux selection for LCD + + @note For PINMUX_FUNC_ID_LCD, PINMUX_FUNC_ID_LCD2 +*/ +typedef enum +{ + PINMUX_LCD_SEL_GPIO, ///< GPIO + PINMUX_LCD_SEL_CCIR656, ///< CCIR-656 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK on LCD[0..8] (L_GPIO[0..8]) + PINMUX_LCD_SEL_CCIR656_16BITS, ///< CCIR-656 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_C[0..7] on LCD[0..8]/LCD[12..19] (L_GPIO[0..8]/L_GPIO[12..19]) + PINMUX_LCD_SEL_CCIR601, ///< CCIR-601 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_CCIR601_16BITS, ///< CCIR-601 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_SERIAL_RGB_6BITS, ///< Serial RGB 6 bits. Enable RGB_D[2..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[2..10] (L_GPIO[2..10]) + PINMUX_LCD_SEL_SERIAL_RGB_8BITS, ///< Serial RGB 8 bits. Enable RGB_D[0..7]/RGB_CLK/RGB_VD/RGB_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_SERIAL_YCbCr_8BITS, ///< Serial YCbCr 8 bits. Enable CCIR_YC[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD on LCD[0..10] (L_GPIO[0..10]) + PINMUX_LCD_SEL_PARALLE_RGB565, ///< Parallel RGB565. Enable RGB_C0_[0..4]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..4] on LCD[3..10]/LCD[14..19]/LCD[23..27] (L_GPIO[3..10]/L_GPIO[14..19]/L_GPIO[23..27]) + PINMUX_LCD_SEL_PARALLE_RGB666, ///< Parallel RGB666. Enable RGB_C0_[0..5]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..5]/RGB_C2_[0..5] on LCD[2..10]/LCD[14..19]/LCD[22..27] (L_GPIO[2..10]/L_GPIO[14..19]/L_GPIO[22..27]) + PINMUX_LCD_SEL_PARALLE_RGB888, ///< Parallel RGB888. Enable RGB_C0_[0..7]/RGB_DCLK/RGB_VS/RGB_HS/RGB_C1_[0..7]/RGB_C2_[0..7] on LCD[0..10]/LCD[12..27] (L_GPIO[2..10]/L_GPIO[12..27]) + PINMUX_LCD_SEL_RGB_16BITS, ///< RGB 16 bits. Enable CCIR_Y[0..7]/CCIR_CLK/CCIR_VD/CCIR_HD/CCIR_C[0..7] on LCD[0..19] (L_GPIO[0..19]) + PINMUX_LCD_SEL_PARALLE_MI_8BITS, ///< Parallel MI 8 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..7]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..12] (L_GPIO[0..7]/L_GPIO[9..12]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..7]/MPU2_WR/MPU2_RD on LCD[12..22]/LCD[24] (L_GPIO[12..22]/L_GPIO[24]) + PINMUX_LCD_SEL_PARALLE_MI_9BITS, ///< Parallel MI 9 bits. + ///< When PINMUX_PMI_CFG_NORMAL is set, Enable MPU_D[0..8]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..13] (L_GPIO[0..7]/L_GPIO[9..13]) + ///< When PINMUX_PMI_CFG_2ND_PINMUX is set, Enable MPU2_RS/MPU2_CS/MPU2_D[0..8]/MPU2_WR/MPU2_RD on LCD[12..24] (L_GPIO[12..24]) + PINMUX_LCD_SEL_PARALLE_MI_16BITS, ///< Parallel MI 16 bits. Enable MPU_D[0..15]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..20] (L_GPIO[0..7]/L_GPIO[9..20]) + PINMUX_LCD_SEL_PARALLE_MI_18BITS, ///< Parallel MI 18 bits. Enable MPU_D[0..17]/MPU_CS/MPU_RS/MPU_WR/MPU_RD on LCD[0..7]/LCD[9..22] (L_GPIO[0..7]/L_GPIO[9..22]) + PINMUX_LCD_SEL_SERIAL_MI_SDIO, ///< Serial MI SDIO bi-direction. Enable MPU_CS/MPU_RS/MPU_CLK/MPU_SDIO on LCD[15..18] (L_GPIO[15..18]) + PINMUX_LCD_SEL_SERIAL_MI_SDI_SDO, ///< Serial MI SDI/SDO seperate. Enable MPU_SDO/MPU_SDI/MPU_CS/MPU_RS/MPU_CLK on LCD[13..17] (L_GPIO[13..17]) + PINMUX_LCD_SEL_MIPI, ///< MIPI DSI + + PINMUX_LCD_SEL_TE_ENABLE = 0x01<<23, ///< TE Enable (For Parallel/Serial MI) + ///< When normal (PINMUX_PMI_CFG_NORMAL) parallel MI, enable MPU_TE on LCD8 (L_GPIO[8]). + ///< When 2nd (PINMUX_PMI_CFG_2ND_PINMUX) parallel MI, enable MPU_TE on LCD25 (L_GPIO[25]). + ///< When serial MI, enable MI_TE on LCD19 (L_GPIO[19]). + PINMUX_LCD_SEL_DE_ENABLE = 0x01<<24, ///< DE Enable (For CCIR656 8/16bits, CCIR601 16bits, Serial RGB 6/8bits, Serial YCbCr 8 bits, RGB 16 bits) + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD, enable CCIR_DE on LCD11 (L_GPIO[11]). + ///< When corresponding item in pinmux_init() is set with PINMUX_DISPMUX_SEL_LCD2, enable CCIR2_DE on LCD23 (L_GPIO[23]). + PINMUX_LCD_SEL_HVLD_VVLD = 0x01<<25, ///< HVLD/VVLD Enable (For CCIR-601 8 bits). Enable CCIR_HVLD/CCIR_VVLD on LCD[12..13] (L_GPIO[12..13]) + PINMUX_LCD_SEL_FIELD = 0x01<<26, ///< FIELD Enable (For CCIR-601 8 bits). Enable CCIR_FIELD on LCD14 (L_GPIO[14]) + + PINMUX_LCD_SEL_FEATURE_MSK = 0x0F<<23, + + ENUM_DUMMY4WORD(PINMUX_LCD_SEL) +} PINMUX_LCD_SEL; + +/** + Pinmux selection for Storage + + @note For PINMUX_FUNC_ID_SDIO, PINMUX_FUNC_ID_SPI, PINMUX_FUNC_ID_NAND +*/ +typedef enum +{ + PINMUX_STORAGE_SEL_INACTIVE, ///< Inactive storage + PINMUX_STORAGE_SEL_ACTIVE, ///< Active storage + PINMUX_STORAGE_SEL_INEXIST, ///< Inexist storage + PINMUX_STORAGE_SEL_EXIST, ///< Exist storage + ENUM_DUMMY4WORD(PINMUX_STORAGE_SEL) +} PINMUX_STORAGE_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_SN_MES0, PINMUX_FUNC_ID_SN_MES1, PINMUX_FUNC_ID_SN_FLCTR +*/ +typedef enum +{ + PINMUX_SENSOR_SEL_INACTIVE, ///< Inactive + PINMUX_SENSOR_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SENSOR_SEL) +} PINMUX_SENSOR_SEL; + +/** + Pinmux selection for sensor + + @note For PINMUX_FUNC_ID_USB_VBUSI +*/ +typedef enum +{ + PINMUX_USB_SEL_INACTIVE, ///< Inactive + PINMUX_USB_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_USB_SEL) +} PINMUX_USB_SEL; + +/** + Pinmux selection for SPI + + @note For PINMUX_FUNC_ID_SPI2, PINMUX_FUNC_ID_SPI3 +*/ +typedef enum +{ + PINMUX_SPI_SEL_INACTIVE, ///< Inactive + PINMUX_SPI_SEL_ACTIVE, ///< Active + ENUM_DUMMY4WORD(PINMUX_SPI_SEL) +} PINMUX_SPI_SEL; + +/** + Pinmux group + + @note For pinmux_init() +*/ +typedef struct +{ + PIN_FUNC pin_function; ///< PIN Function group + UINT32 config; ///< Configuration for pinFunction +} PIN_GROUP_CONFIG; + +/* + Pinmux Function identifier for driver only + + @note For pinmux_setPinmux(). +*/ +typedef enum +{ + PINMUX_FUNC_ID_SDIO = 0x8000000, ///< SDIO, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO2, ///< SDIO2, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SDIO3, ///< SDIO3, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_SPI, ///< SPI, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_NAND, ///< NAND, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_BMC, ///< BMC, pinmux can be: + ///< - @b PINMUX_STORAGE_SEL_INACTIVE + ///< - @b PINMUX_STORAGE_SEL_ACTIVE + PINMUX_FUNC_ID_USB_VBUSI, ///< USB VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_USB2_VBUSI, ///< USB2 VBUSI, pinmux can be: + ///< - @b PINMUX_USB_SEL_INACTIVE + ///< - @b PINMUX_USB_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_1ST, ///< I2C channel1 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C1_2ND, ///< I2C channel1 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_1ST, ///< I2C channel2 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C2_2ND, ///< I2C channel2 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_1ST, ///< I2C channel3 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_2ND, ///< I2C channel3 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C3_3RD, ///< I2C channel3 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_1ST, ///< I2C channel4 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_2ND, ///< I2C channel4 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_3RD, ///< I2C channel4 3rd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C4_4TH, ///< I2C channel4 4th pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_1ST, ///< I2C channel5 1st pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_I2C5_2ND, ///< I2C channel5 2nd pinmux, pinmux can be: + ///< - @b PINMUX_I2C_SEL_INACTIVE + ///< - @b PINMUX_I2C_SEL_ACTIVE + PINMUX_FUNC_ID_SN_VDHD, ///< SN VD/HD, pinmux can be: + ///< - @b PINMUX_SENSOR_SEL_INACTIVE + ///< - @b PINMUX_SENSOR_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_0, ///< PWM channel 0 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_1, ///< PWM channel 1 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_2, ///< PWM channel 2 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_3, ///< PWM channel 3 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_4, ///< PWM channel 4 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_5, ///< PWM channel 5 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_6, ///< PWM channel 6 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_7, ///< PWM channel 7 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_8, ///< PWM channel 8 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_9, ///< PWM channel 9 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_10, ///< PWM channel 10 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_11, ///< PWM channel 11 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_12, ///< PWM channel 12 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_13, ///< PWM channel 13 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_14, ///< PWM channel 14 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_15, ///< PWM channel 15 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_16, ///< PWM channel 16 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_17, ///< PWM channel 17 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_18, ///< PWM channel 18 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_PWM_19, ///< PWM channel 19 + ///< - @b PINMUX_PWM_SEL_INACTIVE + ///< - @b PINMUX_PWM_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_0, ///< SIF channel 0 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_1, ///< SIF channel 1 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_2, ///< SIF channel 2 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_3, ///< SIF channel 3 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_4, ///< SIF channel 4 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_5, ///< SIF channel 5 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_6, ///< SIF channel 6 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_SIF_7, ///< SIF channel 7 + ///< - @b PINMUX_SIF_SEL_INACTIVE + ///< - @b PINMUX_SIF_SEL_ACTIVE + PINMUX_FUNC_ID_UART_1, ///< UART channel 1 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_2, ///< UART channel 2 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_3, ///< UART channel 3 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_UART_4, ///< UART channel 4 + ///< - @b PINMUX_UART_SEL_INACTIVE + ///< - @b PINMUX_UART_SEL_ACTIVE + PINMUX_FUNC_ID_I2S, ///< I2S + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + PINMUX_FUNC_ID_I2S_MCLK, ///< I2S MCLK + ///< - @b PINMUX_I2S_SEL_INACTIVE + ///< - @b PINMUX_I2S_SEL_ACTIVE + + ENUM_DUMMY4WORD(PINMUX_FUNC_ID_DRV) +} PINMUX_FUNC_ID_DRV; + +// +// API for Top controller +// +extern void pinmux_select_debugport(PINMUX_DEBUGPORT uiDebug); +extern void pinmux_select_ocp_debugport(PINMUX_DEBUGPORT_OCP uiDebug); + +extern ER pinmux_init(PIN_GROUP_CONFIG *pConfig); +extern ER pinmux_setDispMode(PINMUX_FUNC_ID id, PINMUX_LCDINIT dispMode); +extern PINMUX_LCDINIT pinmux_getDispMode(PINMUX_FUNC_ID id); +extern ER pinmux_set_pinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +extern BOOL pinmux_chkPinmux(PINMUX_FUNC_ID id, UINT32 pinmux); +//@} //addtogroup mIHALSysCfg + +#endif + diff --git a/loader/Include/nvtpack/nvtpack.h b/loader/Include/nvtpack/nvtpack.h new file mode 100755 index 000000000..d59c5c000 --- /dev/null +++ b/loader/Include/nvtpack/nvtpack.h @@ -0,0 +1,193 @@ +#ifndef _NVTPACK_H +#define _NVTPACK_H + +#define NVTPACK_CHKSUM_HDR_VERSION 0x16040719U +#define NVTPACK_FW_HDR2_VERSION 0x16071515U + +typedef enum _NVTPACK_ER { + NVTPACK_ER_SUCCESS = 0, + NVTPACK_ER_FAILED = -1, + NVTPACK_ER_UNKNOWN_FORMAT = -2, + NVTPACK_ER_CHECK_SUM = -3, + NVTPACK_ER_NOT_FOUND = -4, + NVTPACK_ER_USER_BREAK = -5, + NVTPACK_ER_PARAM = -6, + NVTPACK_ER_MEM_NOT_ENOUGH = -7, + NVTPACK_ER_UITRON_SIZE_ALIGN4 = -8, ///< uITRON size must align by 4 + NVTPACK_ER_INVALID_WHOLE_SIZE = -9, ///< after nvtpack, whole size must align by 4 + NVTPACK_ER_SRC_NAME_BLANK = -10, ///< resource's SrcName cannot be NULL or blank + NVTPACK_ER_SRC_NAME_EXCEED = -11, ///< resource's SrcName cannot exceed 12 bytes + NVTPACK_ER_SRC_NAME_INVALID = -12, ///< resource's SrcName include invalid character + NVTPACK_ER_SRC_NAME_ALIKE = -13, ///< there resource's SrcName are alike. +} NVTPACK_ER; + +typedef enum _NVTPACK_VER { + NVTPACK_VER_UNKNOWN, ///< UNKNOWN + NVTPACK_VER_13012816, ///< NT9666X, NT9850X + NVTPACK_VER_16072017, ///< NT9668X +} NVTPACK_VER; + +#if !defined(_WIN32) +typedef struct _GUID { + unsigned int Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} GUID; +#endif + +typedef struct _NVTPACK_RES_HDR { + GUID guid; ///< {B5CB64AE-05DD-46FA-B906-0C62D22958D6} + unsigned int TotalSize; + unsigned int CheckSum; + unsigned int ContentSize; + char SrcName[16]; ///< original packed bin file name + char DstName[16]; ///< target file name +} NVTPACK_RES_HDR; + +typedef struct _NVTPACK_FW_HDR { + GUID guid; ///< {8827BE90-36CD-4FC2-A987-73A8484E84B1} + unsigned int TotalSize; ///< sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int CheckSum; ///< check sum of sizeof(NVTPACK_FW_HDR) + n*sizeof(NVTPACK_PARTITION_HDR) + unsigned int TotalRes; ///< total partitions +} NVTPACK_FW_HDR; + +typedef struct _NVTPACK_FW_HDR2 { + GUID guid; ///< {D6012E07-10BC-4F91-B28A-352F82261A50} + unsigned int uiVersion; ///< NVTPACK_FW_HDR2_VERSION + unsigned int uiHdrSize; ///< sizeof(NVTPACK_FW_HDR2); + unsigned int TotalRes; ///< total resource counts + unsigned int TotalSize; ///< whole bin size + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_FW_HDR2 + unsigned int uiUserData[4]; ///< user defined data that may be used in future + unsigned int uiReversed[18];///< align to 128 bytes +} NVTPACK_FW_HDR2; + +typedef struct _NVTPACK_PARTITION_HDR { + unsigned int Offset; + unsigned int Size; + unsigned int PartitionID; +} NVTPACK_PARTITION_HDR; + +typedef struct _NVTPACK_CHKSUM_HDR { + unsigned int uiFourCC ; ///< 'C','K','S','M' + unsigned int uiVersion; ///< NVTPACK_CHKSUM_HDR header version + unsigned int uiChkMethod; ///< 0: CheckSum + unsigned int uiChkValue; ///< check sum value or crc value within NVTPACK_CHKSUM_HDR + unsigned int uiDataOffset; ///< real data starting offset without NVTPACK_CHKSUM_HDR + unsigned int uiDataSize; ///< real data size without NVTPACK_CHKSUM_HDR + unsigned int uiPaddingSize; ///< padding bytes for check sum + unsigned int uiEmbType; ///< relate to EMBTYPE_????? + unsigned int uiReversed[8]; ///< align to 64 bytes +} NVTPACK_CHKSUM_HDR; + +typedef struct _NVTPACK_BFC_HDR { + unsigned int uiFourCC; ///< FourCC = BCL1 + unsigned int uiAlgorithm; ///< algorithm always is 9 + unsigned int uiSizeUnComp;///< big endian uncompressed size + unsigned int uiSizeComp; ///< big endian compressed size +} NVTPACK_BFC_HDR; + +typedef struct _NVTPACK_BININFO_HDR { + unsigned int CodeEntry; ///< [0x00] fw CODE entry (4) ----- r by Ld + unsigned int Resv1[19]; ///< [0x04~0x50] reserved (4*19) -- reserved, its mem value will filled by Ld + char BinInfo_1[8]; ///< [0x50~0x58] CHIP-NAME (8) ---- r by Ep + char BinInfo_2[8]; ///< [0x58~0x60] SDK version (8) + char BinInfo_3[8]; ///< [0x60~0x68] SDK release-date (8) + unsigned int BinLength; ///< [0x68] Bin File Length (4) --- w by Ep/bfc + unsigned int Checksum; ///< [0x6c] Check Sum or CRC (4) ----- w by Ep/Epcrc + unsigned int CRCLenCheck; ///< [0x70~0x74] Length check for CRC (4) ----- w by Epcrc (total len ^ 0xAA55) + unsigned int Resv2; ///< [0x74~0x78] reserved (4) --- reserved for other bin tools + unsigned int BinCtrl; ///< [0x78~0x7C] Bin flag (4) --- w by bfc + ///< BIT 0.compressed enable (w by bfc) + unsigned int CRCBinaryTag; ///< [0x7C~0x80] Binary Tag for CRC (4) ----- w by Epcrc (0xAA55 + "NT") +} NVTPACK_BININFO_HDR; + +typedef struct _NVTPACK_MEM { + void *p_data; + unsigned int len; +} NVTPACK_MEM; + +typedef struct _NVTPACK_VERIFY_OUTPUT { + NVTPACK_VER ver; ///< indicate package type + unsigned int partition_cnt; ///< total partition counts +} NVTPACK_VERIFY_OUTPUT; + +typedef struct _NVTPACK_GET_PARTITION_INPUT { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_GET_PARTITION_INPUT; + +typedef struct _NVTPACK_GET_RESOURCE_INPUT { + const char *filename; + NVTPACK_MEM mem; +} NVTPACK_GET_RESOURCE_INPUT; + +typedef struct _NVTPACK_ENUM_PARTITION_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(unsigned int id, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_PARTITION_INPUT; + +typedef struct _NVTPACK_ENUM_RESOURCE_INPUT { + NVTPACK_MEM mem; + void *p_user_data; ///< [Optional] e.g. if use c class, you can pass that class point to your static callback. + int (*fp_enum)(NVTPACK_RES_HDR *p_hdr, NVTPACK_MEM *p_mem, void *p_user_data); +} NVTPACK_ENUM_RESOURCE_INPUT; + +typedef struct _NVTPACK_PARTITION_ITEM { + unsigned int id; + NVTPACK_MEM mem; +} NVTPACK_PARTITION_ITEM; + +typedef struct _NVTPACK_MAKE_PARTITION_INPUT { + NVTPACK_VER ver; ///< package version + NVTPACK_PARTITION_ITEM *p_list; ///< data list + int num; ///< data counts + NVTPACK_MEM mem_work; ///< working buffer +} NVTPACK_MAKE_PARTITION_INPUT; + +typedef struct _NVTPACK_RESOURCE_ITEM { + char SrcName[16]; ///< original name + char DstName[16]; ///< target file name + NVTPACK_MEM mem; +} NVTPACK_RESOURCE_ITEM; + +typedef struct _NVTPACK_MAKE_RESOURCE_INPUT { + NVTPACK_RESOURCE_ITEM *p_list; + int num; + NVTPACK_MEM mem_work; +} NVTPACK_MAKE_RESOURCE_INPUT; + +#ifndef IsEqualGUID +#define IsEqualGUID(rguid1, rguid2) (!memcmp(rguid1, rguid2, sizeof(GUID))) +#endif + +#ifndef MAKEFOURCC +#define MAKEFOURCC(ch0, ch1, ch2, ch3) ((unsigned int)(unsigned char)(ch0) | ((unsigned int)(unsigned char)(ch1) << 8) | ((unsigned int)(unsigned char)(ch2) << 16) | ((unsigned int)(unsigned char)(ch3) << 24 )) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned int nvtpack_calc_nvt_sum(NVTPACK_MEM *p_mem); +extern NVTPACK_ER nvtpack_getver(NVTPACK_MEM *p_mem, NVTPACK_VER *p_ver); +extern NVTPACK_ER nvtpack_verify(NVTPACK_MEM *p_mem, NVTPACK_VERIFY_OUTPUT *p_output); +extern NVTPACK_ER nvtpack_get_partition(NVTPACK_GET_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_partition(NVTPACK_ENUM_PARTITION_INPUT *p_input); +//NVTPACK_VER_13012816: need sizeof(NVTPACK_FW_HDR) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +//NVTPACK_VER_16072017: need sizeof(NVTPACK_FW_HDR2) +n*(sizeof(NVTPACK_PARTITION_HDR) + 4) + whole_data_size +extern NVTPACK_ER nvtpack_make_parition_pkg(NVTPACK_MAKE_PARTITION_INPUT *p_input, NVTPACK_MEM *p_out); + +extern NVTPACK_ER nvtpack_get_resource(NVTPACK_GET_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); +extern NVTPACK_ER nvtpack_enum_resource(NVTPACK_ENUM_RESOURCE_INPUT *p_input); +//buf need n*(sizeof(NVTPACK_RES_HDR)+32)+ whole_data_size +extern NVTPACK_ER nvtpack_make_resource_pkg(NVTPACK_MAKE_RESOURCE_INPUT *p_input, NVTPACK_MEM *p_out); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/loader/Include/rtc.h b/loader/Include/rtc.h new file mode 100755 index 000000000..fb0fa3999 --- /dev/null +++ b/loader/Include/rtc.h @@ -0,0 +1,49 @@ +/** + Header file for RTC module. + + This file is the header file that define the API and data type + for RTC module. + + @file rtc.h + @ingroup mIHALRTC + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __RTC_H +#define __RTC_H +#include "IOReg.h" + +/** + @addtogroup mIHALRTC +*/ +//@{ + +/** + @name RTC power on source + + RTC power on source + + @note For rtc_getPWRONSource() +*/ +//@{ +#define RTC_PWR_SW_STS 0x00000100 ///< Power on from switch +#define RTC_PWR_SW2_STS 0x00000200 ///< power on from power switch 2 +#define RTC_PWR_SW3_STS 0x00000400 ///< power on from power switch 3 (Usually for USB VBUS, depend on project) +#define RTC_PWR_VBUS_STS (RTC_PWR_SW3_STS) ///< power on from VBUS (identical to RTC_PWR_SW3_STS) +#define RTC_PWR_SW4_STS 0x00000800 ///< power on from power switch 4 (Usually for VBAT, depend on project) +#define RTC_PWR_VBAT_STS (RTC_PWR_SW4_STS) ///< power on from VBAT (identical to RTC_PWR_SW4_STS) +#define RTC_PWR_ALARM_STS 0x00010000 ///< Power on from PWR ALARM +//@} + +extern void rtc_resetShutDownTimer(void); +extern void rtc_poweroffPWR(void); +extern UINT32 rtc_getPWRONSource(void); +extern UINT32 rtc_chkS3boot_init(void) __attribute__ ((section (".part1"))); +extern void rtc_chkS3boot_wait_init(void) __attribute__ ((section (".part1"))); +extern UINT32 rtc_chkS3boot(void) __attribute__ ((section (".part1"))); + +//@} +#endif // __RTC_H + diff --git a/loader/Include/scsi_op.h b/loader/Include/scsi_op.h new file mode 100755 index 000000000..bda03aa4f --- /dev/null +++ b/loader/Include/scsi_op.h @@ -0,0 +1,205 @@ +#ifndef _SCSI_OP_H +#define _SCSI_OP_H + +/** +Only Support MSDC Vendor command code 0xF0/0xE0/0xC0. +Others vendor code would STALL OUT EP. Sense data would return illegal request sense code. +*/ +#define SCSI_OP_SET0 0xF0 +#define SCSI_OP_SET1 0xE0 +#define SCSI_OP_SET2 0xC0 + + +/////////////////////////////////////////////////////////////////////////////// +// Uart's return status: CDB[13] +// Uart's extra data len: CDB[6] ~ CDB[9] except SCSIOP_OUT_ADDR_WRITE +// Checksum rule: The CDB[0] ~ CDB[15]'s sum LSB 8bits shall be 0x00 +// Checksum is fixed CDB[14] ~ CDB[15] +// When Checksum failed. CSW Status 0x1 means command failed. +/////////////////////////////////////////////////////////////////////////////// +#define IDX_CDB_UART_DATA_LEN_LWLB 6 ///< uart's data len low word low byte +#define IDX_CDB_UART_DATA_LEN_LWHB 7 ///< uart's data len low word high byte +#define IDX_CDB_UART_DATA_LEN_HWLB 8 ///< uart's data len high word low byte +#define IDX_CDB_UART_DATA_LEN_HWHB 9 ///< uart's data len high word low byte +#define IDX_CDB_UART_STATUS_ER 13 ///< uart's csw status +#define IDX_CDB_CHKSUM_LB 14 ///< check sum low bytes +#define IDX_CDB_CHKSUM_HB 15 ///< check sum high bytes + +/////////////////////////////////////////////////////////////////////////////// +// SCSI CBW +/////////////////////////////////////////////////////////////////////////////// +typedef struct _NVT_SCSI_CBW { + unsigned int dCBWSignature; + unsigned int dCBWTag; + unsigned int dCBWDataTransferLength; + unsigned char bmCBWFlags; + unsigned char bCBWLUN; + unsigned char bCBWCBLength; + unsigned char CBWCB[16]; +} NVT_SCSI_CBW; + +/** +Open NVT Device + +The commands except SCSIOP_IN_IS_NVT can be run if open device success. +If not open first, the operation commands got CSW Status 0x1 means command failed. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_OPEN_DEVICE 0x01 + + +/** +Send Write Loader + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_WRLOADER 0x02 + +/** +Address WRITE WORD (DRAM/REG/SRAM dont care) + +The Write Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +The Write DATA @ CDB[6]~[9]. +For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_ADDR_WRITE 0x03 + +/** +Write Memory + +The Write Starting Address @ CDB[2]~[5]; +For example offset 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_OUT_MEM_WRITE 0x04 + +/** +Read / Write flash + +send SCSIOP_FLASH_OP to loader +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. except CDB[10] +UART: CDB[6]~[9] is SCSIOP_FLASH_OP size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define FLASH_ACCESS_TYPE_AUTO 0 +#define FLASH_ACCESS_TYPE_NAND 1 +#define FLASH_ACCESS_TYPE_NOR 2 +#define FLASH_ACCESS_TYPE_EMMC 3 +typedef struct _SCSIOP_FLASH_OP { + unsigned int type; //FLASH_ACCESS_TYPE + unsigned int is_write; //indicate write + unsigned long long offset; //flash r/w offset + unsigned long long size; //flash r/w size + unsigned long long partition_size; //flash partition size +} SCSIOP_FLASH_OP; +#define SCSIOP_OUT_FLASH_ACCESS 0x05 + + +/** +Ask if NVT Device + +No need to SCSIOP_IN_OPEN_DEVICE +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_IS_NVT 0x81 + + +/** +End USB ROM CODE. + +Exit USB ROM code after receiving this command. The checksum must be correct. +After SCSIOP_IN_WRLOADER is invoked, PC invoked this to confirm write loader is ok. + +CDB[2]~[15] shall follow checksum rule + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_WAIT_DONE 0x82 + + +/** +Address READ WORD (DRAM/REG/SRAM dont care) + +The READ Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [4] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_ADDR_READ 0x83 + + +/** +The Read Starting Address @ CDB[2]~[5]; +For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE +CDB[6]~[9] is read data size +CDB[10]~[15] shall follow checksum rule. Content is dont care. + +@DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define SCSIOP_IN_MEM_READ 0x84 + + +/** +Get Temp Buffer Address + +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: Read out DATA is [3] ~[7]. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_GET_TMP_ADDR 0x85 + +/** +Notify fdt has send + +The fdt has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) + +@DATA_PHASE: None. +@CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define SCSIOP_IN_FDT 0x86 + + +/** +Notify uboot or nvtpack has send + +The uboot or nvtpack has sent into loader's temp buffer. notify loader to check its sanity. +CDB[2]~[5] is status result in word. +MSDC: CDB[6]~[15] shall follow checksum rule. Content is dont care. +UART: CDB[6]~[9] is data size (because uart has no CBW to tell transmitting size) +*/ +#define SCSIOP_IN_UBOOT 0x87 + +#endif \ No newline at end of file diff --git a/loader/Include/signal.h b/loader/Include/signal.h new file mode 100755 index 000000000..5a2a7078c --- /dev/null +++ b/loader/Include/signal.h @@ -0,0 +1,4 @@ +#ifndef _NVT_LIBC_SIGNAL_H__ +#define _NVT_LIBC_SIGNAL_H__ +int raise(int sig); +#endif diff --git a/loader/Include/stdarg.h b/loader/Include/stdarg.h new file mode 100755 index 000000000..f9af31232 --- /dev/null +++ b/loader/Include/stdarg.h @@ -0,0 +1,19 @@ +#ifndef __NVT_STDARG_H__ +#define __NVT_STDARG_H__ + +typedef char *va_list; + +/* + * Storage alignment properties + */ +#define _AUPBND (sizeof (int) - 1) +#define _ADNBND (sizeof (int) - 1) + +/* + * Variable argument list macro definitions + */ +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) +#endif diff --git a/loader/Include/stdio.h b/loader/Include/stdio.h new file mode 100755 index 000000000..ec8eff431 --- /dev/null +++ b/loader/Include/stdio.h @@ -0,0 +1,23 @@ +/** + STDIO header + + STDIO header + + @file stdio.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_STDIO_H__ +#define __NVT_STDIO_H__ + +/** \addtogroup mISYSClib */ +//@{ + +int sprintf(char * buf, const char *fmt, ...); +int sscanf(const char * buf, const char * fmt, ...); + +//@} +#endif diff --git a/loader/Include/stdlib.h b/loader/Include/stdlib.h new file mode 100755 index 000000000..9f8540807 --- /dev/null +++ b/loader/Include/stdlib.h @@ -0,0 +1,4 @@ +#ifndef __NVT_LIBC_STDLIB_H__ +#define __NVT_LIBC_STDLIB_H__ +int atoi(const char *nptr); +#endif diff --git a/loader/Include/string.h b/loader/Include/string.h new file mode 100755 index 000000000..aed82db58 --- /dev/null +++ b/loader/Include/string.h @@ -0,0 +1,47 @@ +/** + string header + + string header + + @file string.h + @ingroup mISYSClib + @note Nothing + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef __NVT_LIBC_STRING_H__ +#define __NVT_LIBC_STRING_H__ + +/** \addtogroup mISYSClib */ +//@{ + +/** + size_t data type + + data type to store value return by sizeof keyword +*/ +typedef unsigned int size_t; + +extern size_t strlen(const char *s); +extern size_t strnlen(const char *s, size_t count); +extern char *strncpy(char *dest, const char *src, size_t count); +extern char *strncat(char *dest, const char *src, size_t count); +extern char *strstr(const char *s1, const char *s2); +extern int strncmp(const char *cs, const char *ct, size_t count); +extern char *strrchr(const char *s, int c); +extern char *strcpy(char *dest, const char *src); +extern char *strcat(char *dest, const char *src); +extern char *strchr(const char *s, int c); +extern char* strtok(char *s, const char *delim); +extern int strcmp(const char *cs, const char *ct); + +extern void *utl_memset(void *s, int c, size_t count); +extern void *utl_memcpy(void *dest, const void *src, size_t count); +extern int memcmp(const void *cs, const void *ct, size_t count); +extern void *memmove(void *dest, const void *src, size_t count); +extern void *memchr(const void *ptr, int value, size_t count); +//@} + +#endif + diff --git a/loader/Include/timer.h b/loader/Include/timer.h new file mode 100755 index 000000000..22992bc11 --- /dev/null +++ b/loader/Include/timer.h @@ -0,0 +1,31 @@ +/** + Public header file for timer module. + + This file is the header file that define the API and data type for timer + module. + + @file timer.h + @ingroup mIHALTimer + @note Nothing. + + Copyright Novatek Microelectronics Corp. 2012. All rights reserved. +*/ + +#ifndef _TIMER_H +#define _TIMER_H + +#include "IOReg.h" + +/** + @addtogroup mIHALTimer +*/ +//@{ + +extern UINT32 timer_getLdrElapse(void); +extern void timer_delay(UINT32 US); +#define timer_getLdrElapse() INREG32(0xF0040108) +#define timer_getSysTick() INREG32(0xF0040108) +//extern UINT32 timer_getSysTick(void) __attribute__ ((section (".part1"))); + //@} + +#endif diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile b/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile new file mode 100755 index 000000000..b4bab9925 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/Makefile @@ -0,0 +1,59 @@ +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ../../../Project/Model/ModelConfig.txt +include ../../../Project/Model/ModelConfig_$(MODEL).txt +include ../../../Project/Model/MakeConfig.txt + +#---------------------------------------------------------------------- +# set the library name here +#---------------------------------------------------------------------- +PRJ_NAME = Ctrl_Flow + + +#---------------------------------------------------------------------- +# add/delete source files here +#---------------------------------------------------------------------- +SRC = \ + bl_func.c \ + main.c \ + nand_ids.c\ + spi_nor_ids.c\ + bl_u2.c + +ASM = + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../../Include + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = ../../../ARC/Lib + +#---------------------------------------------------------------------- +# add additional C and assembly flags here +#---------------------------------------------------------------------- +CFLAGS_D = -O2 +ASMFLAGS_D = + +CFLAGS_R = -O2 +ASMFLAGS_R = + +C_DEFINE_EXT = \ + $(EXTSTRG_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(SECURE_DECRYPT_OPTEE_PARAM) \ + $(OPTEE_UBOOT_SIGNATURE_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + +CFLAGS_R = $(C_DEFINE_EXT) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputLib.txt diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c new file mode 100755 index 000000000..1de9e15f4 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c @@ -0,0 +1,3325 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "bl_func.h" +#include "Cache.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "CC.h" +#include "loader.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "emb_partition_info.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" +#include "gic.h" +#include "libfdt.h" +#include +#include "bl_u2.h" +#include "crypto.h" +#include "nand.h" +#include "nor.h" + +//#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +//static uint32_t global_timer_freq = 3000000; //3MHz = 3000000 Hz +//#endif +PSTORAGE_OBJ int_strg_obj = NULL; + +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +//#define TEE_HEADER_SIZE 0x1C // refer to: optee_header_t + +#define _THUMB2 __attribute__((target("thumb2"))) + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 + +#define HEADINFO_UBOOT(p_parti) ((HEADINFO *)(p_parti->uboot_addr + BIN_INFO_OFFSET_UBOOT)) +#define HEADINFO_TEEOS(p_parti) ((HEADINFO *)(p_parti->teeos_addr + BIN_INFO_OFFSET_TEEOS)) +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) + +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +extern void set_usb_suspend(void); +#endif + +#if (_ROM_PUBLIC_API_ == 1) +#define ROM_LZMA_POSITION 0x7fd0 +UINT8 lzma_temp_buffer[65536]; +int (*rom_lzma_inflate)(UINT8 *in_ptr, UINT32 in_size, UINT8 *out_ptr, UINT32 out_size, UINT8 *p_tmp, UINT32 tmp_size); +#endif + +extern char _loader_exec_compres_start[]; +//extern char _load_nand_table_start_base[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base[]; +extern void core1_reset(void); + +// Function from Timer.c +//extern UINT32 timer_getLdrElapse(void); + +// Define in MakeConfig.txt +static UINT8 UPDATE_FW_NAME[] = {"FW98520A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98520A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98520T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"WRKEY.BIN"}; +#if UPDATE_SIM_CODE +static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"SIM.BIN"}; +#endif +#endif +static UINT8 RECOVERY_FW_NAME[] = {"FW98520R.BIN"}; +static UINT32 g_uiPartitionID = 2; + +static UINT32 g_uiVersion = 0; + +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +UINT32 TopOfStack; +UINT32 BaseOfStack; + +extern char _loader_heap_base[]; + +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. + +static LDR_FASTBOOT_KEY_CB gFastbootKeyCallBack = NULL; +static LDR_SPECIAL_KEY_CB gSpecialKeyCallBack = NULL; +static LDR_CARD_DETECT_CB gCardDetectCallBack = NULL; +static STORAGEINT gStorageIntType = STORAGEINT_UNOKNOWN; + +static LDR_RECOVERY_TRIGGER_CB gRecoveryTriggerCallBack = NULL; +//#if (!USB_WRITELOADER) +//#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static BOOL g_is_recovery_triggered = FALSE; // indicate recovery flow is triggered. +//#endif +_THUMB2 static int bl_is_smp(unsigned char *p_fdt); +static UINT32 g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; +static UINT32 g_uiNandBlkSize = 0; +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_TEEOS "/nvt_memory_cfg/teeos" +#define PATH_MEM_HDAL "/hdal-memory/media" +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#define PATH_NVT_INFO "/nvt_info" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_TEEOS "partition_teeos" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +#define PROPERTY_NVT_LINUX_SMP "NVT_LINUX_SMP" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +static EMB_PARTITION g_emb_teeos = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00007E00, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x01800000, + .fdt_size = 0x00040000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0xC0000, + .PartitionSize = 0xA0000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +static EMB_PARTITION g_emb_teeos = { ///< optional, only for optee, + .PartitionOffset = 0, + .PartitionSize = 0, +}; +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_TEEOS -1 +#define NVTPACK_IDX_RTOS 10 +#endif + + + +#if (UART_UPDATE_ == ENABLE) +static char g_strLength[80]; // buffer to store length string +#endif + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +int bl_boot_uboot(unsigned char *p_fdt); + +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + debug_msg(Msg); + // Loop forever + while (1) { + ; + } +} + + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +_THUMB2 static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) + + +_THUMB2 static void get_bininfo_size_offset(unsigned char* bininfo,unsigned int* size,unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5]<<8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] <<24; +} + + + + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned int len) +{ + + CRYPT_OP crypt_op_param; + if(len &0x0f) + { + debug_msg_var("enc size", len); + debug_err("not align 16\r\n"); + return -21; + } + if((input & 0x03) || (output & 0x03) || (len & 0x03) ){ //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + + #if 0 + debug_msg_var("input",input); + debug_msg_var("output",output); + debug_msg_var("len",len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + debug_msg_var("encryped buf addr",(unsigned int)tmp); + for(i=0;i<16;i++){ + debug_msg_var("encryped buf",(unsigned int)tmp[i]); + } + #endif + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) + { + //debug_err("aes dec fail\r\n"); + return -23; + } + #if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr",(unsigned int)&tmp[0]); + for(i=0;i<16;i++){ + debug_msg_var("decryped buf",(unsigned int)tmp[i]); + } + + #endif + return 0; + +} +#if (SECURE_SIGNATURE_BY_AES == 0) +_THUMB2 static void data_reverse(unsigned char* input_data, unsigned int size) +{ + unsigned int i=0; + unsigned char tmp=0; + for(i=0;i< (size/2);i++) + { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} +#endif +_THUMB2 static int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int* output_size,unsigned int partition_size) +{ + + unsigned int encrypt_offset =0; + unsigned int encrypt_size =0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int signature_offset =0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int sha256_align_size =0; + UINT32 * signature_buff = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + #if (SECURE_SIGNATURE_BY_AES == 0) + unsigned int key_offset =0; + unsigned int key_size =0; + unsigned int n_size=0; + unsigned int e_size=0; + UINT32 sign_rsa_output[64]; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n),n_size); + data_reverse((unsigned char *)(key_e),e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if(er == 0) + { + debug_err("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size,sign_rsa_output); + + data_reverse((unsigned char *)sign_rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&sign_rsa_output[(sizeof(sign_rsa_output)/4 ) - (32/4 )];// offset need devided by 4, because of UINT32 type + #else + //UINT32 sign_aes_output[8]; + + er = decrypt_aes_cbc((UINT32 )(input_data + signature_offset), output_data,signature_size); + if(er != 0) + { + debug_err("decrypt_aes_cbc fail\r\n"); + return -20; + } + signature_buff =(UINT32 *)output_data; + + #endif + //hash encrypt data + + if((data_size & 0x3f) != 0) + { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((data_size/0x40) + 1)*0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + data_size),0, sha256_align_size - data_size); + } + else + { + sha256_align_size = data_size; + } + + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + + //compare signature and current hash + if(memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) + { + debug_err("sig fail\r\n"); + return -20; + } +#endif + + //decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if((input_data + encrypt_offset) & 0x03) + { + utl_memcpy((void *)input_data,(unsigned char*)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } + else + { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if(er != 0) + { + debug_err("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if( plaintext_size > 0) + { + utl_memcpy(&p_output[encrypt_size], (unsigned char*)(input_data + encrypt_offset+ encrypt_size),plaintext_size); + } + return 0; + +} +#endif + +//#NT#2013/04/25#Steven Wang -begin +//#NT#Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) +void BL_showROMLog(UINT32 buffer) +{ + UINT32 value; + UINT32 index; + UINT32 P_duty; + UINT32 N_duty; + UINT32 diff; + + index = 0; + diff = 0; + P_duty = 0; + N_duty = 0; + uart_putSystemUARTStr("\r\n"); + while (1) { + value = INREG32(buffer + index); + + if ((value & 0xF0000000) == 0xF0000000) { + value &= ~(0x40000000); + uart_putSystemUARTStr(Dec2HexStr(value)); + uart_putSystemUARTStr(" = "); + } + + else if ((value & 0xF0000000) == 0x50000000) { + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x20000000) { +// uart_putSystemUARTStr("P_duty = "); + P_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(P_duty)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x30000000) { +// uart_putSystemUARTStr("N_duty = "); + N_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(N_duty)); + uart_putSystemUARTStr("\r\n"); + if (P_duty > N_duty) { + if (diff == 2) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 1; + } + } else { + if (diff == 1) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 2; + } + } + } else if ((value & 0xF0000000) == 0x60000000) { + uart_putSystemUARTStr("N+P = "); + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } else if ((value & 0xF0000000) == 0x70000000) { + if ((value & 0xFFFFFFF) == 0x0654321) { + break; + } + } else { + uart_putSystemUARTStr("Unknow \r\n"); + } + index += 4; + } + uart_putSystemUARTStr("\r\n[0xC0001000] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC0001000))); + uart_putSystemUARTStr(" [0xC000101C] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC000101C))); + uart_putSystemUARTStr("\r\n"); +} +#endif +//#NT#2013/04/25#Steven Wang -end + + +#if (DRAM_RANGE_SCAN_EN == ENABLE) +/** + Check Sram code. + + Check is dram scan code or not + + @param[in] uiAddress Scan FW code in DRAM starting address + @return void +*/ +static BOOL bl_checkDramScanFW(UINT32 uiAddress) +{ + if ((*(UINT32 *)uiAddress & SRAM_TAG) == SRAM_TAG) { + return TRUE; + } else { + return FALSE; + } +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} +#endif + +/* + Update multi-binary image + + + @param[in] uiFwBuf buffer store fw read from card + + @return + -@ b TRUE: success + -@ b FALSE: fail +*/ + +#if !REMOVED_FLASH +#if 0 +static void bl_interrupt_init(void) +{ + debug_msg("arm_gic_distif_setup\r\n"); + arm_gic_distif_setup(); + debug_msg("arm_gic_cpuif_setup\r\n"); + arm_gic_cpuif_setup(); + + // + //debug_dump_addr(0xF1500000+0x1000,0x500); + //debug_dump_addr(0xF1500000+0x2000,0x100); +} +#endif + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +#define OUTW(addr,value) (*(UINT32 volatile *)(addr) = (UINT32)(value)) +#define INW(addr) (*(UINT32 volatile *)(addr)) + + +static void bl_cpu_timer_init(UINT32 value) +{ + UINT32 dwVal; + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_LOAD_OFFSET, value); + + dwVal = INW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET); + /* Enable Auto reload mode. */ + dwVal |= ARM_TIMER_CONTROL_AUTO_RELOAD_MASK; + /* Clear prescaler control bits */ + dwVal &= ~ARM_TIMER_CONTROL_PRESCALER_MASK; + /* Set prescaler value */ + dwVal |= ((CYGHWR_HAL_RTC_PRESCALER - 1) << ARM_TIMER_CONTROL_PRESCALER_SHIFT); + /* Enable the decrementer */ + //dwVal |= ARM_TIMER_CONTROL_ENABLE_MASK; + /* Enable the interrupt */ + dwVal |= ARM_TIMER_CONTROL_IRQ_ENABLE_MASK; + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET, dwVal); + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_ISR_OFFSET, + ARM_TIMER_ISR_EVENT_FLAG_MASK); + +} +#endif +#endif +_THUMB2 int bl_flash_open(void) +{ + int er; + //UINT32 uiStorageVersion = (UINT32)&_load_nand_table_start_base; + + if (g_is_flash_open) { + return 0; + } + //========================================================================== + //= User define SPI-NAND id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + //========================================================================== + //= User define SPI-NOR id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_installIdentifyCB(nor_identify); + + er = int_strg_obj->flash_open(); + if (er < 0) { + debug_err("flash open fail\r\n"); + return -1; + } + + //OUTREG32(NAND_TABLE_VERSION_ADDR, INREG32(uiStorageVersion)); + + //if (er == E_OK) { + // OUTREG32(NAND_TABLE_FLAG_ADDR, 0x46495053); //'S''P''I''F' + //} else { // E_OK_TABLE_FOUND(1) or E_OK_TABLE_NOT_FOUND(2) + // OUTREG32(NAND_TABLE_FLAG_ADDR, er); + //} + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; + } + + g_is_flash_open = TRUE; + return 0; +} + +#if 0 //[-Werror=unused-function] +static int bl_flash_close(void) +{ + if (!g_is_flash_open) { + return 0; + } + + flash_close(); + g_is_flash_open = FALSE; + return 0; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} + +_THUMB2 static const void *bl_get_fdt_nvt_memory_cfg_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + static int nodeoffset_nvt_memory_cfg = -FDT_ERR_NOTFOUND;; /* next node offset from libfdt */ + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (strncmp(p_path, "/nvt_memory_cfg/", 3) != 0) { + debug_err("path prefix must be /nvt_memory_cfg/\r\n"); + return NULL; + } + + if (nodeoffset_nvt_memory_cfg == -FDT_ERR_NOTFOUND) { + nodeoffset_nvt_memory_cfg = fdt_path_offset(p_dtb, "/nvt_memory_cfg"); + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_nvt_memory_cfg, &p_path[16]); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_TEEOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.teeos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.teeos_size = be32_to_cpu(nodep[1]); + } + + p_rt = (UINT8 *)&g_dram_partition; + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (fdt_check_full((void *)addr, size) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot and teeos + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + +// if ((addr < p_dram_partition->uboot_addr && addr + size > p_dram_partition->uboot_addr) || +// (addr > p_dram_partition->uboot_addr && addr + size < p_dram_partition->uboot_addr + p_dram_partition->uboot_size)) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->uboot_addr, p_dram_partition->uboot_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("uboot olp\r\n"); + return -1; + } +#if 1 + //if ((addr < p_dram_partition->teeos_addr && addr + size > p_dram_partition->teeos_addr) || + // (addr > p_dram_partition->teeos_addr && addr + size < p_dram_partition->teeos_addr + p_dram_partition->teeos_size)) { + if (p_dram_partition->teeos_size) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->teeos_addr, p_dram_partition->teeos_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("teeos olp\r\n"); + return -1; + } + } +#endif + // check if memory size matched real size + UINT32 ld_dram1_size = dma_get_dram_capacity(DMA_ID_1); + if (p_dram_partition->dram_size > ld_dram1_size) { + debug_err_var("fw_d1_s", p_dram_partition->dram_size); + debug_err_var("ld_d1_s", ld_dram1_size); + debug_err("d1 s not matched.\r\n"); + return -1; + } + return 0; +} +#endif + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_uboot(unsigned int addr, unsigned int size) +{ +#if (_FPGA_EMULATION_ == 0) + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail"); + return -1; + } +#endif + return 0; +} + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +static void bl_core2_reset(void) +{ + UINT32 core_reg; + + debug_msg("core2_reset\r\n"); + + core_reg = *(volatile UINT32 *)0xF0E400F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF0E400F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF0E400F0 = core_reg; +} + +static void bl_core2_prepare(DRAM_PARTITION *p_dram_partition, unsigned int last_addr) +{ + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen, code2EntryCodelen; + + //check core2_entry1 must at addr 0 + if (p_dram_partition->core2_entry1_addr != CORE2_JUMP_ADDR) { + bl_displayErrMsg("core2entry1 != 0"); + } + + // copy core2 jump code to dram 0x0 + code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry1_addr, code2JumpCodelen); + + debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)p_dram_partition->core2_entry2_addr); + + // copy core2 entry code to dram specified by fdt + *(volatile UINT32 *)(NVT_CORE2_START) = p_dram_partition->core2_entry2_addr; + code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry2_addr, code2EntryCodelen); + + debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + + *(volatile UINT32 *)0xF07F8000 = last_addr; + + debug_msg_var("0xF07F8000=", (int)*(volatile UINT32 *)0xF07F8000); +} + +static int bl_smp_start(unsigned char *p_modelext, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_DRAM_PARTITION); + if (p_bininfo == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_modelext); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_modelext; + debug_msg_var("p_bininfo->boot.fdt_addr", p_bininfo->boot.fdt_addr); + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + if(utl_get_bootsrc() == BOOT_SOURCE_UART) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } else if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#else +// if (card_get_type() == EXT_STORAGE_TYPE_ETH) +// p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +// else if (g_is_recovery_triggered) +// p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; +// else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg("smp(no tee)\r\n"); + + bl_core2_prepare(p_dram_partition, 0); + +//#if USB_WRITELOADER +#if 0 + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif + + + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + //reset core2 + bl_core2_reset(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} +#endif +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + if(utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } +#else + if (card_get_type() == EXT_STORAGE_TYPE_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; + // else if (g_is_recovery_triggered) + // p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; + else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} + +_THUMB2 int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + return bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt); + } + } + return -1; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + UINT32 uItron_fw_addr= 0; + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + HEADINFO *p_headinfo; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return 0; + } + + np_get_input.id = 5; // rtos must always put in partition[5] for now + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt);//&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return 0; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg("get rtos partition ok\r\n"); + + p_headinfo = (HEADINFO *)(emb_fdt.p_data + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + + utl_memcpy((void *)uItron_fw_addr, emb_fdt.p_data, emb_fdt.len); + CPUflushWriteCache(uItron_fw_addr, emb_fdt.len); + } + debug_msg_var("uItron_fw_addr=", uItron_fw_addr); + return uItron_fw_addr; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + + // read first block to get dtb size + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + + int total_size = ALIGN_CEIL(fdt_totalsize(p_tmp), blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", fdt_totalsize(p_tmp)); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW+1, total_size, p_tmp+blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + } + + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + return bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt); + } + + return -1; +} + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition_fdt_offset(unsigned char *p_fdt) +{ + static int nodeoffset= -FDT_ERR_NOTFOUND; + + if (nodeoffset > 0) { + return nodeoffset; + } + + const static char *p_names[3] = { + "/nand", + "/nor", + "/mmc@f0510000" + }; + + const char *name = NULL; + switch(gStorageIntType) { + case STORAGEINT_SPI_NAND: + name = p_names[0]; + break; + case STORAGEINT_SPI_NOR: + name = p_names[1]; + break; + case STORAGEINT_EMMC: + name = p_names[2]; + break; + default: + debug_err("loader_setStorageIntType needs.\r\n"); + return NULL; + } + + nodeoffset = fdt_path_offset(p_fdt, name); + + if (nodeoffset < 0) { + debug_err("E:bl_get_partition_name\r\n"); + } + return nodeoffset; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_partition_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset_partition = bl_get_partition_fdt_offset((unsigned char *)p_dtb); + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (nodeoffset_partition < 0) { + debug_err("nodeoffset_partition invalid \r\n"); + return NULL; + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_partition, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + int nodeoffset_partition = bl_get_partition_fdt_offset(p_fdt); + int nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset_partition, "nvtpack"); + nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset, "index"); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static void *bl_get_nuttx_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ + if (bl_get_partition(p_fdt, PATH_PARTITION_NUTTX, &g_emb_nuttx, p_id) != 0) { + return NULL; + } + g_emb_nuttx.EmbType = EMBTYPE_NUTTX; + + return &g_emb_nuttx; +} +#endif + +_THUMB2 static void *bl_get_teeos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_TEEOS, &g_emb_teeos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_TEEOS; +#endif + g_emb_teeos.EmbType = EMBTYPE_TEEOS; + + return &g_emb_teeos; +} +#endif + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Un_compress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); +// debug_msg_var("uboot_size", p_dram_partition->uboot_size); +# if 0 + if(0) { +#else +#if (_FPGA_EMULATION_ == 0) + if(is_secure_enable() == 0) { +#else + if (1) { +#endif +#endif + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); + +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + debug_msg("lz"); + } + } else { + debug_msg("nml"); + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size =0; + + if((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0 ) + { + //debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT\r\n"); + return -1; +#endif + } + + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_load_nuttx_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_nuttx; + int nuttx_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_nuttx = bl_get_nuttx_partition(p_fdt, &nuttx_partition_id); + + if (p_emb_partition_nuttx == NULL) { + debug_err("null p_emb_partition_nuttx\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)nuttx_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_nuttx); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)mem_nuttx.p_data, mem_nuttx.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_nuttx.p_data + BIN_INFO_OFFSET_NUTTX); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_nuttx.p_data; // describe compressed u-boot + + // load nuttx bin to dram partiton location + debug_msg_var("nuttx_addr", p_dram_partition->nuttx_addr); + debug_msg_var("nuttx_size", p_dram_partition->nuttx_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_nuttx.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->nuttx_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->nuttx_addr, mem_nuttx.p_data, p_headinfo->BinLength); + } + + return 0; +} +#endif + +_THUMB2 static int bl_load_teeos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_teeos; + int teeos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + HEADINFO *p_headinfo = NULL; + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)teeos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_teeos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size =0; + utl_memcpy((void *)p_dram_partition->teeos_addr, mem_teeos.p_data, mem_teeos.len); + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr,&plaintext_size, p_dram_partition->teeos_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + //this is the second headinfo information , not encrpyted headinfo + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); +#else + debug_err("please enable SECURE_DECRYPT_OPTEE_OS"); + return -1; +#endif + } + else{ + p_headinfo = (HEADINFO *)(mem_teeos.p_data + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + utl_memcpy((void *)p_dram_partition->teeos_addr, (unsigned char*)mem_teeos.p_data, p_headinfo->BinLength); + } + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + + //check addr matched or not + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + return 0; +} + +_THUMB2 static int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + +#if (SECURE_DECRYPT_UBOOT) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } +#else + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } + +#endif + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +#if 0 + if(0){ +#else + if(is_secure_enable() == 0) { +#endif + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) + { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le, blk_size),p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + } + else + { + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } + else + { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size=0; + if((er =do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } +#else + debug_msg("plase enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + } + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if(bl_is_smp(p_fdt)) { + bl_core2_prepare(p_dram_partition, 0); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } +#endif + + // load 1st block of rtos to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) + { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le, blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET, blk_size) - bininfo_preload_size; + + if (preload_size!= 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + debug_msg_var("part1_size",part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset /blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + return 0; +} + +_THUMB2 static int bl_load_teeos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int teeos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_TEEOS + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read teeos failed + } + + // flow to handle compressed u-boot and uncompressed one. +#if (SECURE_DECRYPT_OPTEE_OS) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot +#else + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + +#endif + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(p_headinfo->BinLength, blk_size), (UINT8 *)p_dram_partition->teeos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); // read bfc-teeos failed + bl_displayErrMsg(RWErrorMsg); + } +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + + unsigned int plaintext_size=0; + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot +#else + debug_err("please ENABLE SECURE_DECRYPT_OPTEE_OS config\n"); + return -1; +#endif + } + + // load teeos bin to dram partiton location + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + //check check sum + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + return 0; +} +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +#if 0//(STORAGE_EXT_TYPE == STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_usb_raw(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + // assume usb write loader receive full fw at 0x0200_0000, decompress it to smaller address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr - SIZE_PRESERVE_USB); + p_headinfo = (HEADINFO *)(src_addr - SIZE_PRESERVE_USB + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + utl_memcpy((void *)(uncompress_addr + uncompress_size), (void *)src_addr, compress_size); + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = compress_size; + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + debug_msg("uncompressed t.bin\r\n"); + utl_memcpy((void *)uncompress_addr, (void *)src_addr, uncompress_size); + src_size = uncompress_size; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw. NOt Support from USB\r\n"); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +//#if !USB_WRITELOADER +#if !((STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART)) +_THUMB2 static int bl_load_rtos_from_uart(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ +#if UART_UPDATE_ + UINT32 tick_kms = 10; // timeout 1000 ms + char key; + + debug_msg("UART press Enter to\r\n"); + + while (--tick_kms) { + uart_chkChar(&key); + + if (key != 0x00) { + break; + } + timer_delay(100000); //100000 + debug_msg("."); + } + + if (tick_kms) { + UINT32 uiLength; + debug_msg("\r\nEnter uboot length (Decimal):\r\n"); //must \r\n at the end because of auto_test tool + uart_getStr_polling(g_strLength); + uiLength = DecStr2Int(g_strLength); + debug_msg("\r\nPlz pass uboot bin > "); + uart_getBinary((char *)src_addr, uiLength); // Temp Receive to DRAM start + debug_msg("\r\nGot it\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + if (bl_checkDramScanFW(src_addr) == TRUE) { + UINT32 i; + + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + uiLength = ((uiLength + 3) & 0xFFFFFFFC); + + for (i = 0; i < uiLength; i += 4) { + *(UINT32 *)(src_addr + i) = *(UINT32 *)(src_addr + i); + } + *(UINT32 *)(src_addr) = *(UINT32 *)(src_addr); + return 1; + } +#endif + if (*(UINT32 *)src_addr == MAKEFOURCC('B', 'C', 'L', '1')) { + HEADINFO *p_headinfo = NULL; + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + bl_checkFW(src_addr, uiLength); + debug_msg_var("uiLength", uiLength); + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + uiLength); + p_headinfo = (HEADINFO *)(src_addr + uiLength + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned int ori_src_addr = src_addr; + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = uncompress_size; + utl_memcpy((void *)src_addr, (void *)ori_src_addr, uiLength); + *p_dst_addr = src_addr; + *p_dst_size = compress_size; + return 0; + } else { + return -1; + } + return 0; + } + } +#endif + return -1; +} +#endif + +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; +#if (UITRON_FW == ENABLE) + BININFO *pBinInfo; +#endif + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + } else { + pHeadInfo->ModelextAddr = 0; +#if (UITRON_FW == ENABLE) + pBinInfo = (BININFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + pBinInfo->ld.Resv[0] = LoaderInternalInfo[1]; + pBinInfo->ld.LdPackage = (LoaderInternalInfo[3] & 0xFFFF); +#endif + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + BOOTINFO *p_ld; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + p_ld = &p_shminfo->boot; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getLdrElapse(); + p_ld->LdResvSize = 0; //unused + p_ld->FWResvSize = 0; //unused + return 0; +} + +_THUMB2 static int bl_is_smp(unsigned char *p_fdt) +{ +#if (FDT_SUPPORT) + int len; + const char *nodep; + nodep = (const char *)bl_get_fdt_property(p_fdt, PATH_NVT_INFO, PROPERTY_NVT_LINUX_SMP, &len); + debug_msg_var("nodep", (UINT32)nodep); + if (nodep == NULL) { + return 0; + } + debug_msg((char *)nodep); + if (strcmp(nodep, "NVT_LINUX_SMP_ON") == 0) { + return 1; + } + return 0; +#else + return 0; +#endif +} + +#if !REMOVED_FLASH +_THUMB2 int bl_boot_uboot(unsigned char *p_fdt) +{ +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + UINT32 No_CPU; +#endif + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update shminfo + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_shminfo->boot.LdPackage = p_param[3] & 0xFFFF; + p_shminfo->boot.LdStorage = (p_param[3] >> 16) & 0xFF; + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + UINT32 isSMP = bl_is_smp(p_fdt); + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + No_CPU = *(UINT32 *)0xFFD00004; + No_CPU &= 0x3; + debug_msg_var("core No.=", No_CPU+1); +#endif + // init cpu timer +// bl_cpu_timer_init(CPU_TIMER_SETTING); +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if (!isSMP || !No_CPU) +#else + if (!isSMP) +#endif + { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + debug_msg_var("Bin core=", isSMP+1); +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + } else { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + // init cpu timer + bl_cpu_timer_init(global_timer_freq); + + bl_smp_start(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader +#else + //bl_smp_start(p_fdt, p_headinfo->CodeEntry); + debug_err("not support smp\r\n"); +#endif + } + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_boot_nuttx(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->nuttx_addr + BIN_INFO_OFFSET_NUTTX); + + if (bl_chk_uboot(p_dram_partition->nuttx_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + // start cpu2 + if (p_dram_partition->nuttx_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-nuttx_addr ", (int)p_dram_partition->nuttx_addr); + debug_err_var("bin-nuttx_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + bl_cpu_timer_init(CPU_TIMER_SETTING); + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot nuttx and never return back to loader + return 0; +} +#endif + +_THUMB2 static int bl_boot_teeos(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + + // update uboot addr for teeos + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR] = p_dram_partition->uboot_addr; + + +#if 0 //do not checksum, because teeos header has removed cause checksum failed + if (bl_chk_uboot(p_dram_partition->teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } +#endif + + //flush uboot + CPUflushWriteCache(p_dram_partition->uboot_addr, p_dram_partition->uboot_size); + //flush teeos + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + bl_cpu_timer_init(CPU_TIMER_SETTING); + // boot core2 (after teeos is loaded) + if (HEADINFO_UBOOT(p_dram_partition)->BinCtrl & 0x00000002) { + //if SMP, trigger core2 + debug_msg("smp(tee)\r\n"); + bl_core2_prepare(p_dram_partition, p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } else { + debug_msg_var("not smp\r\n", p_headinfo->BinCtrl); + } +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot teeos and never return back to loader + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + unsigned int ver; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + BOOTINFO *p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + + return 0; +} + +// return uItron_fw_addr +_THUMB2 unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + //if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + if (1) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->nuttx_size == 0 && p_dram_partition->teeos_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if (p_dram_partition->nuttx_size) { +#if (NUTTX_SUPPORT) + // load nuttx + er = bl_load_nuttx_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load nuttx failed\r\n"); + } + er = bl_boot_nuttx((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot nuttx failed\r\n"); + } +#else + bl_displayErrMsg("NUTTX_SUPPORT disabled\r\n"); +#endif + } else if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } + return er; + } else { + // update rtos information + // the following is for uncompressed-rtos only, others needing uboot + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return bl_load_rtos_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + } +} +#endif + +// return uItron_fw_addr, no need to fully decode +_THUMB2 static unsigned int bl_process_rtos_only(UINT32 uiFwBuf, UINT32 uiFwBufSize, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + UINT32 uItron_fw_addr; + NVTPACK_BFC_HDR *pBFC; + HEADINFO *p_headinfo; + + debug_msg("\r\nbl_process_rtos_only\r\n"); + pBFC = (NVTPACK_BFC_HDR *)uiFwBuf; + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 compressSize; + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + LZ_Un_compress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + compressSize = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //debug_dump_addr(tmpBuf,0x200); + debug_msg_var("F compress uItron_fw_addr", uItron_fw_addr); + // uiFwBuf has adjusted on bl_load_rtos_from_non_nvtpack() + *p_comp_addr = uiFwBuf; + *p_comp_size = compressSize; + } else { + p_headinfo = (HEADINFO *)(uiFwBuf + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + + debug_msg_var("Normal uItron_fw_addr", uItron_fw_addr); + *p_comp_addr = 0; + *p_comp_size = 0; + } + return uItron_fw_addr; +} +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } +#if 1 + else if (p_dram_partition->rtos_addr == 0 || DUAL_RTOS_SUPPORT || (gFastbootKeyCallBack == NULL) || (!gFastbootKeyCallBack())) { + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } + #endif + else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + debug_msg("sf load rtos\r\n"); + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +/** + bl_process_update_loader. + + Write loader will update loader binary file + + @param[in] loader_addr loader in DRAM starting address + @param[in] loader_size loader code length (from loader header offset 0x24) + @return void +*/ +_THUMB2 static int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card + if(is_data_area_encrypted() == 0) { + +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + //UINT32 uiOffset; + //uiOffset = *((UINT32 *)(loader_addr + 0x80)); + //if(uiOffset) {//Combo loader + // if(*(UINT32*)0xF00100F0 == 0x50210000) { + // debug_msg("combo loader 528\r\n"); + // bl_checkLoader(loader_addr+uiOffset, COMBINATION_LOADER_SIZE - uiOffset); //check 528 + // } else{ + // debug_msg("combo loader 52X\r\n"); + // bl_checkLoader(loader_addr, loader_size); //check 52x + // } + //}else + bl_checkLoader(loader_addr, loader_size); +#else +#if 0//(LOADER_TYPE == COMBINATION_528) + debug_msg("CB8\r\n"); + bl_checkLoader(loader_addr + loader_size, (COMBINATION_LOADER_SIZE - loader_size)); +#else //STAND_ALONE_LOADER or combination 52x loader + //debug_msg("STD\r\n"); + bl_checkLoader(loader_addr, loader_size); +#endif +#endif + } + debug_msg("update loader\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program loader +#if 0 +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + UINT32 uiOffset; + uiOffset = *((UINT32 *)(loader_addr + 0x80)); + if(uiOffset) //Combo loader + loader_size = COMBINATION_LOADER_SIZE; + //If single loader , it already got +#else +#if (LOADER_TYPE == STAND_ALONE_LOADER_560) || (LOADER_TYPE == STAND_ALONE_LOADER_528) +#else //Combination loader + loader_size = COMBINATION_LOADER_SIZE; +#endif +#endif +#endif + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#if UPDATE_EMU_CODE +_THUMB2 static int bl_process_update_emu_firmware(unsigned int emu_addr, unsigned int emu_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +// bl_checkFW(emu_addr, emu_size); + debug_msg("update emu firmware size"); + uart_putSystemUARTStr(Dec2HexStr(emu_size)); + uart_putSystemUARTStr("\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program firmware + if (int_strg_obj->flash_writeSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)emu_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = emu_addr + emu_size; + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)reload_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)emu_addr, (void *)reload_addr, emu_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#endif + +_THUMB2 void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize) +{ + *pLoadAddr = g_rtos_load_addr; + *pTargetAddr = g_rtos_target_addr; + *pSize = g_rtos_size; +} + +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 32 * 1024; // pre-assume 32KB, actual size is parsed from loader + //Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) + UINT32 uiLoaderAddress; + UINT32 uiLogSramAddress; +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; +#endif + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; +// UINT32 uiheapBufferAddr = BaseOfStack + 0x40000; // reserve 16KB for tmp buffer usage + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + + // UART initial sequence + //uart_openSystemUART(); + // rtc reset shutdown timer + // rtc_resetShutDownTimer(); + + + + +#if 0 + // adjust PAD driving (if required) + bl_adjustDriving(); + /* + - @b RTC_PWR_SW_STS: Power on source is PWR_SW + - @b RTC_PWR_VBAT_STS: Power on source is PWR_VBAT + - @b RTC_PWR_VBUS_STS: Power on source is PWR_VBUS + */ + uiPowerOnSrc = rtc_getPWRONSource(); + + if (uiPowerOnSrc & RTC_PWR_SW_STS) { + uart_putSystemUARTStr("\r\nSW PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBAT_STS) { + uart_putSystemUARTStr("\r\nVBAT PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBUS_STS) { + uart_putSystemUARTStr("\r\nVBUS PON\r\n"); + } else if (rtc_getIsAlarmPowerOn()) { + uart_putSystemUARTStr("\r\nPwrAlarm PON\r\n"); + } else { + uart_putSystemUARTStr("\r\nPOR PON\r\n"); + } +#endif + // Display Loader Version + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + + +#if 0 // for now, reduce code size + if (rtc_chkS3boot()) { + UINT32 resume_addr; + + uart_putSystemUARTStr("main selfing..\r\n"); + resume_addr = bl_resume_cpu1((unsigned char *)_BOARD_IPC_ADDR_); + if (resume_addr == 0) { + // in codition for MODELEXT_BUILT_IN_ON + resume_addr = RESUME_ADDR; + } + return resume_addr; + } else { + + uart_putSystemUARTStr("main not selfing..\r\n"); + } +#endif + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + prj_main(); + +#if !(USB_WRITELOADER) + set_usb_suspend(); +#endif + + if(utl_get_bootsrc() == BOOT_SOURCE_UART) + { +#if UART_UPDATE + debug_msg("Boot from UART ...\r\n"); + bl_uart();//never returned. +#else + bl_displayErrMsg("UART_UPDATE must enable on loader\r\n"); +#endif + } + + if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) + { +#if USB_WRITELOADER + debug_msg("Boot from USB ...\r\n"); + bl_usb(); //never returned. +#else + bl_displayErrMsg("USB_WRITELOADER must enable on loader\r\n"); +#endif + } + +#if !(USB_WRITELOADER || UART_UPDATE) + if (bl_load_rtos_from_uart(uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH, &adjusted_addr, &adjusted_size) == 0) { + //specail case, load small rtos from uart + uiUpdateMainBinBufAddr = adjusted_addr; + uiUpdateFileLen = adjusted_size; + uiLoaderFunc |= FUNC_RUN_CARD; + } else if ((int_strg_obj->flash_getBlockSize() == EMMC_BLOCK_SIZE) && gRecoveryTriggerCallBack && gRecoveryTriggerCallBack()) { + debug_msg("Recovery triggered not support currently.\r\n"); +#if 0 + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } else { + flash_mount_fs(0, BaseOfStack + 0x4000, FAT_HEAP_BUFFER_SIZE); + if (flash_mount_partition(g_uiPartitionID) == E_OK) { + if (flash_open_file(RECOVERY_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + g_is_recovery_triggered = TRUE; + } else { + debug_msg("Recovery should be all in one bin!\r\n"); + } + } else { + debug_msg("no recovery bin!\r\n"); + } + } else { + debug_msg("Partition error!\r\n"); + } + } +#endif + } +#if 1 + else if ((gSpecialKeyCallBack()) && (gCardDetectCallBack())) { + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + debug_msg("card close\r\n"); + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } + } +#endif +#if 0 + else if (((gCardDetectCallBack == NULL) || gCardDetectCallBack())) + { + debug_msg("sf gCardDetectCallBack gCardDetectCallBack\r\n"); + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + debug_msg("sf ld\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + debug_msg("sf fw\r\n"); // for line end RRRRRRR.... + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } + } +#endif + else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack != NULL) || (gCardDetectCallBack() == FALSE))) { + debug_msg("No card inserted\r\n"); + } +#endif + + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +#if (REMOVED_FLASH == ENABLE) + bl_displayErrMsg("cannot process all-in-one fw"); +#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +#endif + } else { + // non-all-in-one flow + // check valid + if (uiLoaderFunc & FUNC_UPDATE_FW) { +#if UPDATE_EMU_CODE + bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +#else + bl_displayErrMsg("cannot write non-all-in-one fw"); +#endif + } + uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + } + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } + +#else + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + } + +#if UPDATE_EMU_CODE + debug_msg_var("emu fw len", uiUpdateFileLen); +#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} + +_THUMB2 void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback) +{ + gSpecialKeyCallBack = callback; +} + +_THUMB2 void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback) +{ + gCardDetectCallBack = callback; +} + +_THUMB2 void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback) +{ + gRecoveryTriggerCallBack = callback; +} + +_THUMB2 void loader_installFastbootKeyCB(LDR_FASTBOOT_KEY_CB callback) +{ + gFastbootKeyCallBack = callback; +} + +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.bak b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.bak new file mode 100755 index 000000000..47831ca29 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.bak @@ -0,0 +1,3253 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "bl_func.h" +#include "Cache.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "CC.h" +#include "loader.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "emb_partition_info.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" +#include "gic.h" +#include "libfdt.h" +#include +#include "bl_u2.h" +#include "crypto.h" +#include "nand.h" +#include "nor.h" + +//#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +//static uint32_t global_timer_freq = 3000000; //3MHz = 3000000 Hz +//#endif +PSTORAGE_OBJ int_strg_obj = NULL; + +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +//#define TEE_HEADER_SIZE 0x1C // refer to: optee_header_t + +#define _THUMB2 __attribute__((target("thumb2"))) + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 + +#define HEADINFO_UBOOT(p_parti) ((HEADINFO *)(p_parti->uboot_addr + BIN_INFO_OFFSET_UBOOT)) +#define HEADINFO_TEEOS(p_parti) ((HEADINFO *)(p_parti->teeos_addr + BIN_INFO_OFFSET_TEEOS)) +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) + +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +extern void set_usb_suspend(void); +#endif + +#if (_ROM_PUBLIC_API_ == 1) +#define ROM_LZMA_POSITION 0x7fd0 +UINT8 lzma_temp_buffer[65536]; +int (*rom_lzma_inflate)(UINT8 *in_ptr, UINT32 in_size, UINT8 *out_ptr, UINT32 out_size, UINT8 *p_tmp, UINT32 tmp_size); +#endif + +extern char _loader_exec_compres_start[]; +//extern char _load_nand_table_start_base[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base[]; +extern void core1_reset(void); + +// Function from Timer.c +//extern UINT32 timer_getLdrElapse(void); + +// Define in MakeConfig.txt +static UINT8 UPDATE_FW_NAME[] = {"FW98520A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98520A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98520T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"WRKEY.BIN"}; +#if UPDATE_SIM_CODE +static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"SIM.BIN"}; +#endif +#endif +static UINT8 RECOVERY_FW_NAME[] = {"FW98520R.BIN"}; +static UINT32 g_uiPartitionID = 2; + +static UINT32 g_uiVersion = 0; + +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +UINT32 TopOfStack; +UINT32 BaseOfStack; + +extern char _loader_heap_base[]; + +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. + +static LDR_FASTBOOT_KEY_CB gFastbootKeyCallBack = NULL; +static LDR_SPECIAL_KEY_CB gSpecialKeyCallBack = NULL; +static LDR_CARD_DETECT_CB gCardDetectCallBack = NULL; +static STORAGEINT gStorageIntType = STORAGEINT_UNOKNOWN; + +static LDR_RECOVERY_TRIGGER_CB gRecoveryTriggerCallBack = NULL; +//#if (!USB_WRITELOADER) +//#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static BOOL g_is_recovery_triggered = FALSE; // indicate recovery flow is triggered. +//#endif +_THUMB2 static int bl_is_smp(unsigned char *p_fdt); +static UINT32 g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; +static UINT32 g_uiNandBlkSize = 0; +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_TEEOS "/nvt_memory_cfg/teeos" +#define PATH_MEM_HDAL "/hdal-memory/media" +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#define PATH_NVT_INFO "/nvt_info" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_TEEOS "partition_teeos" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +#define PROPERTY_NVT_LINUX_SMP "NVT_LINUX_SMP" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +static EMB_PARTITION g_emb_teeos = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00007E00, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x01800000, + .fdt_size = 0x00040000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0xC0000, + .PartitionSize = 0xA0000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +static EMB_PARTITION g_emb_teeos = { ///< optional, only for optee, + .PartitionOffset = 0, + .PartitionSize = 0, +}; +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_TEEOS -1 +#define NVTPACK_IDX_RTOS 10 +#endif + + + +#if (UART_UPDATE_ == ENABLE) +static char g_strLength[80]; // buffer to store length string +#endif + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +int bl_boot_uboot(unsigned char *p_fdt); + +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + debug_msg(Msg); + // Loop forever + while (1) { + ; + } +} + + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +_THUMB2 static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) + + +_THUMB2 static void get_bininfo_size_offset(unsigned char* bininfo,unsigned int* size,unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5]<<8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] <<24; +} + + + + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned int len) +{ + + CRYPT_OP crypt_op_param; + if(len &0x0f) + { + debug_msg_var("enc size", len); + debug_err("not align 16\r\n"); + return -21; + } + if((input & 0x03) || (output & 0x03) || (len & 0x03) ){ //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + + #if 0 + debug_msg_var("input",input); + debug_msg_var("output",output); + debug_msg_var("len",len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + debug_msg_var("encryped buf addr",(unsigned int)tmp); + for(i=0;i<16;i++){ + debug_msg_var("encryped buf",(unsigned int)tmp[i]); + } + #endif + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) + { + //debug_err("aes dec fail\r\n"); + return -23; + } + #if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr",(unsigned int)&tmp[0]); + for(i=0;i<16;i++){ + debug_msg_var("decryped buf",(unsigned int)tmp[i]); + } + + #endif + return 0; + +} +#if (SECURE_SIGNATURE_BY_AES == 0) +_THUMB2 static void data_reverse(unsigned char* input_data, unsigned int size) +{ + unsigned int i=0; + unsigned char tmp=0; + for(i=0;i< (size/2);i++) + { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} +#endif +_THUMB2 static int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int* output_size,unsigned int partition_size) +{ + + unsigned int encrypt_offset =0; + unsigned int encrypt_size =0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int signature_offset =0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int sha256_align_size =0; + UINT32 * signature_buff = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + #if (SECURE_SIGNATURE_BY_AES == 0) + unsigned int key_offset =0; + unsigned int key_size =0; + unsigned int n_size=0; + unsigned int e_size=0; + UINT32 sign_rsa_output[64]; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n),n_size); + data_reverse((unsigned char *)(key_e),e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if(er == 0) + { + debug_err("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size,sign_rsa_output); + + data_reverse((unsigned char *)sign_rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&sign_rsa_output[(sizeof(sign_rsa_output)/4 ) - (32/4 )];// offset need devided by 4, because of UINT32 type + #else + //UINT32 sign_aes_output[8]; + + er = decrypt_aes_cbc((UINT32 )(input_data + signature_offset), output_data,signature_size); + if(er != 0) + { + debug_err("decrypt_aes_cbc fail\r\n"); + return -20; + } + signature_buff =(UINT32 *)output_data; + + #endif + //hash encrypt data + + if((data_size & 0x3f) != 0) + { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((data_size/0x40) + 1)*0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + data_size),0, sha256_align_size - data_size); + } + else + { + sha256_align_size = data_size; + } + + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + + //compare signature and current hash + if(memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) + { + debug_err("sig fail\r\n"); + return -20; + } +#endif + + //decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if((input_data + encrypt_offset) & 0x03) + { + utl_memcpy((void *)input_data,(unsigned char*)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } + else + { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if(er != 0) + { + debug_err("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if( plaintext_size > 0) + { + utl_memcpy(&p_output[encrypt_size], (unsigned char*)(input_data + encrypt_offset+ encrypt_size),plaintext_size); + } + return 0; + +} +#endif + +//#NT#2013/04/25#Steven Wang -begin +//#NT#Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) +void BL_showROMLog(UINT32 buffer) +{ + UINT32 value; + UINT32 index; + UINT32 P_duty; + UINT32 N_duty; + UINT32 diff; + + index = 0; + diff = 0; + P_duty = 0; + N_duty = 0; + uart_putSystemUARTStr("\r\n"); + while (1) { + value = INREG32(buffer + index); + + if ((value & 0xF0000000) == 0xF0000000) { + value &= ~(0x40000000); + uart_putSystemUARTStr(Dec2HexStr(value)); + uart_putSystemUARTStr(" = "); + } + + else if ((value & 0xF0000000) == 0x50000000) { + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x20000000) { +// uart_putSystemUARTStr("P_duty = "); + P_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(P_duty)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x30000000) { +// uart_putSystemUARTStr("N_duty = "); + N_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(N_duty)); + uart_putSystemUARTStr("\r\n"); + if (P_duty > N_duty) { + if (diff == 2) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 1; + } + } else { + if (diff == 1) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 2; + } + } + } else if ((value & 0xF0000000) == 0x60000000) { + uart_putSystemUARTStr("N+P = "); + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } else if ((value & 0xF0000000) == 0x70000000) { + if ((value & 0xFFFFFFF) == 0x0654321) { + break; + } + } else { + uart_putSystemUARTStr("Unknow \r\n"); + } + index += 4; + } + uart_putSystemUARTStr("\r\n[0xC0001000] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC0001000))); + uart_putSystemUARTStr(" [0xC000101C] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC000101C))); + uart_putSystemUARTStr("\r\n"); +} +#endif +//#NT#2013/04/25#Steven Wang -end + + +#if (DRAM_RANGE_SCAN_EN == ENABLE) +/** + Check Sram code. + + Check is dram scan code or not + + @param[in] uiAddress Scan FW code in DRAM starting address + @return void +*/ +static BOOL bl_checkDramScanFW(UINT32 uiAddress) +{ + if ((*(UINT32 *)uiAddress & SRAM_TAG) == SRAM_TAG) { + return TRUE; + } else { + return FALSE; + } +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} +#endif + +/* + Update multi-binary image + + + @param[in] uiFwBuf buffer store fw read from card + + @return + -@ b TRUE: success + -@ b FALSE: fail +*/ + +#if !REMOVED_FLASH +#if 0 +static void bl_interrupt_init(void) +{ + debug_msg("arm_gic_distif_setup\r\n"); + arm_gic_distif_setup(); + debug_msg("arm_gic_cpuif_setup\r\n"); + arm_gic_cpuif_setup(); + + // + //debug_dump_addr(0xF1500000+0x1000,0x500); + //debug_dump_addr(0xF1500000+0x2000,0x100); +} +#endif + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +#define OUTW(addr,value) (*(UINT32 volatile *)(addr) = (UINT32)(value)) +#define INW(addr) (*(UINT32 volatile *)(addr)) + + +static void bl_cpu_timer_init(UINT32 value) +{ + UINT32 dwVal; + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_LOAD_OFFSET, value); + + dwVal = INW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET); + /* Enable Auto reload mode. */ + dwVal |= ARM_TIMER_CONTROL_AUTO_RELOAD_MASK; + /* Clear prescaler control bits */ + dwVal &= ~ARM_TIMER_CONTROL_PRESCALER_MASK; + /* Set prescaler value */ + dwVal |= ((CYGHWR_HAL_RTC_PRESCALER - 1) << ARM_TIMER_CONTROL_PRESCALER_SHIFT); + /* Enable the decrementer */ + //dwVal |= ARM_TIMER_CONTROL_ENABLE_MASK; + /* Enable the interrupt */ + dwVal |= ARM_TIMER_CONTROL_IRQ_ENABLE_MASK; + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET, dwVal); + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_ISR_OFFSET, + ARM_TIMER_ISR_EVENT_FLAG_MASK); + +} +#endif +#endif +_THUMB2 int bl_flash_open(void) +{ + int er; + //UINT32 uiStorageVersion = (UINT32)&_load_nand_table_start_base; + + if (g_is_flash_open) { + return 0; + } + //========================================================================== + //= User define SPI-NAND id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + //========================================================================== + //= User define SPI-NOR id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_installIdentifyCB(nor_identify); + + er = int_strg_obj->flash_open(); + if (er < 0) { + debug_err("flash open fail\r\n"); + return -1; + } + + //OUTREG32(NAND_TABLE_VERSION_ADDR, INREG32(uiStorageVersion)); + + //if (er == E_OK) { + // OUTREG32(NAND_TABLE_FLAG_ADDR, 0x46495053); //'S''P''I''F' + //} else { // E_OK_TABLE_FOUND(1) or E_OK_TABLE_NOT_FOUND(2) + // OUTREG32(NAND_TABLE_FLAG_ADDR, er); + //} + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; + } + + g_is_flash_open = TRUE; + return 0; +} + +#if 0 //[-Werror=unused-function] +static int bl_flash_close(void) +{ + if (!g_is_flash_open) { + return 0; + } + + flash_close(); + g_is_flash_open = FALSE; + return 0; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} + +_THUMB2 static const void *bl_get_fdt_nvt_memory_cfg_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + static int nodeoffset_nvt_memory_cfg = -FDT_ERR_NOTFOUND;; /* next node offset from libfdt */ + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (strncmp(p_path, "/nvt_memory_cfg/", 3) != 0) { + debug_err("path prefix must be /nvt_memory_cfg/\r\n"); + return NULL; + } + + if (nodeoffset_nvt_memory_cfg == -FDT_ERR_NOTFOUND) { + nodeoffset_nvt_memory_cfg = fdt_path_offset(p_dtb, "/nvt_memory_cfg"); + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_nvt_memory_cfg, &p_path[16]); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_TEEOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.teeos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.teeos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_HDAL, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get hdal fail\r\n"); + return NULL; + } + g_dram_partition.hdal1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.hdal1_size = be32_to_cpu(nodep[1]); + if (len >= 16) { + g_dram_partition.hdal2_addr = be32_to_cpu(nodep[2]); + g_dram_partition.hdal2_size = be32_to_cpu(nodep[3]); + } + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_CORE2_ENTRY1, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry1_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry1_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_CORE2_ENTRY2, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.core2_entry2_addr = be32_to_cpu(nodep[0]); + g_dram_partition.core2_entry2_size = be32_to_cpu(nodep[1]); + } +#endif + p_rt = (UINT8 *)&g_dram_partition; + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (fdt_check_full((void *)addr, size) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot and teeos + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + +// if ((addr < p_dram_partition->uboot_addr && addr + size > p_dram_partition->uboot_addr) || +// (addr > p_dram_partition->uboot_addr && addr + size < p_dram_partition->uboot_addr + p_dram_partition->uboot_size)) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->uboot_addr, p_dram_partition->uboot_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("uboot olp\r\n"); + return -1; + } +#if 1 + //if ((addr < p_dram_partition->teeos_addr && addr + size > p_dram_partition->teeos_addr) || + // (addr > p_dram_partition->teeos_addr && addr + size < p_dram_partition->teeos_addr + p_dram_partition->teeos_size)) { + if (p_dram_partition->teeos_size) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->teeos_addr, p_dram_partition->teeos_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("teeos olp\r\n"); + return -1; + } + } +#endif + // check if memory size matched real size + UINT32 ld_dram1_size = dma_get_dram_capacity(DMA_ID_1); + if (p_dram_partition->dram_size > ld_dram1_size) { + debug_err_var("fw_d1_s", p_dram_partition->dram_size); + debug_err_var("ld_d1_s", ld_dram1_size); + debug_err("d1 s not matched.\r\n"); + return -1; + } + UINT32 ld_dram2_size = dma_get_dram_capacity(DMA_ID_2); + if (p_dram_partition->hdal2_size > ld_dram2_size) { + debug_err_var("fw_d2_s", p_dram_partition->hdal2_size); + debug_err_var("ld_d2_s", ld_dram2_size); + debug_err("d2 s not matched.\r\n"); + return -1; + } + return 0; +} +#endif + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_uboot(unsigned int addr, unsigned int size) +{ +#if (_FPGA_EMULATION_ == 0) + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail"); + return -1; + } +#endif + return 0; +} + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +static void bl_core2_reset(void) +{ + UINT32 core_reg; + + debug_msg("core2_reset\r\n"); + + core_reg = *(volatile UINT32 *)0xF0E400F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF0E400F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF0E400F0 = core_reg; +} + +static void bl_core2_prepare(DRAM_PARTITION *p_dram_partition, unsigned int last_addr) +{ + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen, code2EntryCodelen; + + //check core2_entry1 must at addr 0 + if (p_dram_partition->core2_entry1_addr != CORE2_JUMP_ADDR) { + bl_displayErrMsg("core2entry1 != 0"); + } + + // copy core2 jump code to dram 0x0 + code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry1_addr, code2JumpCodelen); + + debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)p_dram_partition->core2_entry2_addr); + + // copy core2 entry code to dram specified by fdt + *(volatile UINT32 *)(NVT_CORE2_START) = p_dram_partition->core2_entry2_addr; + code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry2_addr, code2EntryCodelen); + + debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + + *(volatile UINT32 *)0xF07F8000 = last_addr; + + debug_msg_var("0xF07F8000=", (int)*(volatile UINT32 *)0xF07F8000); +} + +static int bl_smp_start(unsigned char *p_modelext, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_DRAM_PARTITION); + if (p_bininfo == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_modelext); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_modelext; + debug_msg_var("p_bininfo->boot.fdt_addr", p_bininfo->boot.fdt_addr); + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + if(utl_get_bootsrc() == BOOT_SOURCE_UART) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } else if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#else +// if (card_get_type() == EXT_STORAGE_TYPE_ETH) +// p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +// else if (g_is_recovery_triggered) +// p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; +// else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg("smp(no tee)\r\n"); + + bl_core2_prepare(p_dram_partition, 0); + +//#if USB_WRITELOADER +#if 0 + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif + + + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + //reset core2 + bl_core2_reset(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} +#endif +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + if(utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } +#else + if (card_get_type() == EXT_STORAGE_TYPE_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; + // else if (g_is_recovery_triggered) + // p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; + else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} + +_THUMB2 int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + return bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt); + } + } + return -1; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + UINT32 uItron_fw_addr= 0; + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + HEADINFO *p_headinfo; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return 0; + } + + np_get_input.id = 5; // rtos must always put in partition[5] for now + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt);//&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return 0; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg("get rtos partition ok\r\n"); + + p_headinfo = (HEADINFO *)(emb_fdt.p_data + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + + utl_memcpy((void *)uItron_fw_addr, emb_fdt.p_data, emb_fdt.len); + CPUflushWriteCache(uItron_fw_addr, emb_fdt.len); + } + debug_msg_var("uItron_fw_addr=", uItron_fw_addr); + return uItron_fw_addr; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + + // read first block to get dtb size + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + + int total_size = ALIGN_CEIL(fdt_totalsize(p_tmp), blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", fdt_totalsize(p_tmp)); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW+1, total_size, p_tmp+blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + } + + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + return bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt); + } + + return -1; +} + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition_fdt_offset(unsigned char *p_fdt) +{ + static int nodeoffset= -FDT_ERR_NOTFOUND; + + if (nodeoffset > 0) { + return nodeoffset; + } + + const static char *p_names[3] = { + "/nand", + "/nor", + "/mmc@f0510000" + }; + + const char *name = NULL; + switch(gStorageIntType) { + case STORAGEINT_SPI_NAND: + name = p_names[0]; + break; + case STORAGEINT_SPI_NOR: + name = p_names[1]; + break; + case STORAGEINT_EMMC: + name = p_names[2]; + break; + default: + debug_err("loader_setStorageIntType needs.\r\n"); + return NULL; + } + + nodeoffset = fdt_path_offset(p_fdt, name); + + if (nodeoffset < 0) { + debug_err("E:bl_get_partition_name\r\n"); + } + return nodeoffset; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_partition_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset_partition = bl_get_partition_fdt_offset((unsigned char *)p_dtb); + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (nodeoffset_partition < 0) { + debug_err("nodeoffset_partition invalid \r\n"); + return NULL; + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_partition, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + int nodeoffset_partition = bl_get_partition_fdt_offset(p_fdt); + int nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset_partition, "nvtpack"); + nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset, "index"); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static void *bl_get_nuttx_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ + if (bl_get_partition(p_fdt, PATH_PARTITION_NUTTX, &g_emb_nuttx, p_id) != 0) { + return NULL; + } + g_emb_nuttx.EmbType = EMBTYPE_NUTTX; + + return &g_emb_nuttx; +} +#endif + +_THUMB2 static void *bl_get_teeos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_TEEOS, &g_emb_teeos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_TEEOS; +#endif + g_emb_teeos.EmbType = EMBTYPE_TEEOS; + + return &g_emb_teeos; +} +#endif + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Un_compress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); +// debug_msg_var("uboot_size", p_dram_partition->uboot_size); +# if 0 + if(0) { +#else +#if (_FPGA_EMULATION_ == 0) + if(is_secure_enable() == 0) { +#else + if (1) { +#endif +#endif + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); + +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + debug_msg("lz"); + } + } else { + debug_msg("nml"); + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size =0; + + if((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0 ) + { + //debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT\r\n"); + return -1; +#endif + } + + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_load_nuttx_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_nuttx; + int nuttx_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_nuttx = bl_get_nuttx_partition(p_fdt, &nuttx_partition_id); + + if (p_emb_partition_nuttx == NULL) { + debug_err("null p_emb_partition_nuttx\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)nuttx_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_nuttx); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)mem_nuttx.p_data, mem_nuttx.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_nuttx.p_data + BIN_INFO_OFFSET_NUTTX); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_nuttx.p_data; // describe compressed u-boot + + // load nuttx bin to dram partiton location + debug_msg_var("nuttx_addr", p_dram_partition->nuttx_addr); + debug_msg_var("nuttx_size", p_dram_partition->nuttx_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_nuttx.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->nuttx_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->nuttx_addr, mem_nuttx.p_data, p_headinfo->BinLength); + } + + return 0; +} +#endif + +_THUMB2 static int bl_load_teeos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_teeos; + int teeos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + HEADINFO *p_headinfo = NULL; + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)teeos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_teeos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size =0; + utl_memcpy((void *)p_dram_partition->teeos_addr, mem_teeos.p_data, mem_teeos.len); + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr,&plaintext_size, p_dram_partition->teeos_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + //this is the second headinfo information , not encrpyted headinfo + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); +#else + debug_err("please enable SECURE_DECRYPT_OPTEE_OS"); + return -1; +#endif + } + else{ + p_headinfo = (HEADINFO *)(mem_teeos.p_data + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + utl_memcpy((void *)p_dram_partition->teeos_addr, (unsigned char*)mem_teeos.p_data, p_headinfo->BinLength); + } + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + + //check addr matched or not + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + return 0; +} + +_THUMB2 static int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + +#if (SECURE_DECRYPT_UBOOT) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } +#else + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } + +#endif + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +#if 0 + if(0){ +#else + if(is_secure_enable() == 0) { +#endif + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) + { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le, blk_size),p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + } + else + { + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } + else + { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size=0; + if((er =do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } +#else + debug_msg("plase enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + } + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if(bl_is_smp(p_fdt)) { + bl_core2_prepare(p_dram_partition, 0); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } +#endif + + // load 1st block of rtos to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) + { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le, blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET, blk_size) - bininfo_preload_size; + + if (preload_size!= 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + debug_msg_var("part1_size",part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset /blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + return 0; +} + +_THUMB2 static int bl_load_teeos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int teeos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_TEEOS + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read teeos failed + } + + // flow to handle compressed u-boot and uncompressed one. +#if (SECURE_DECRYPT_OPTEE_OS) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot +#else + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + +#endif + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(p_headinfo->BinLength, blk_size), (UINT8 *)p_dram_partition->teeos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); // read bfc-teeos failed + bl_displayErrMsg(RWErrorMsg); + } +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + + unsigned int plaintext_size=0; + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot +#else + debug_err("please ENABLE SECURE_DECRYPT_OPTEE_OS config\n"); + return -1; +#endif + } + + // load teeos bin to dram partiton location + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + //check check sum + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + return 0; +} +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +#if 0//(STORAGE_EXT_TYPE == STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_usb_raw(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + // assume usb write loader receive full fw at 0x0200_0000, decompress it to smaller address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr - SIZE_PRESERVE_USB); + p_headinfo = (HEADINFO *)(src_addr - SIZE_PRESERVE_USB + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + utl_memcpy((void *)(uncompress_addr + uncompress_size), (void *)src_addr, compress_size); + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = compress_size; + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + debug_msg("uncompressed t.bin\r\n"); + utl_memcpy((void *)uncompress_addr, (void *)src_addr, uncompress_size); + src_size = uncompress_size; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw. NOt Support from USB\r\n"); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +//#if !USB_WRITELOADER +#if !((STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART)) +_THUMB2 static int bl_load_rtos_from_uart(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ +#if UART_UPDATE_ + UINT32 tick_kms = 10; // timeout 1000 ms + char key; + + debug_msg("UART press Enter to\r\n"); + + while (--tick_kms) { + uart_chkChar(&key); + + if (key != 0x00) { + break; + } + timer_delay(100000); //100000 + debug_msg("."); + } + + if (tick_kms) { + UINT32 uiLength; + debug_msg("\r\nEnter uboot length (Decimal):\r\n"); //must \r\n at the end because of auto_test tool + uart_getStr_polling(g_strLength); + uiLength = DecStr2Int(g_strLength); + debug_msg("\r\nPlz pass uboot bin > "); + uart_getBinary((char *)src_addr, uiLength); // Temp Receive to DRAM start + debug_msg("\r\nGot it\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + if (bl_checkDramScanFW(src_addr) == TRUE) { + UINT32 i; + + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + uiLength = ((uiLength + 3) & 0xFFFFFFFC); + + for (i = 0; i < uiLength; i += 4) { + *(UINT32 *)(src_addr + i) = *(UINT32 *)(src_addr + i); + } + *(UINT32 *)(src_addr) = *(UINT32 *)(src_addr); + return 1; + } +#endif + if (*(UINT32 *)src_addr == MAKEFOURCC('B', 'C', 'L', '1')) { + HEADINFO *p_headinfo = NULL; + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + bl_checkFW(src_addr, uiLength); + debug_msg_var("uiLength", uiLength); + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + uiLength); + p_headinfo = (HEADINFO *)(src_addr + uiLength + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned int ori_src_addr = src_addr; + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = uncompress_size; + utl_memcpy((void *)src_addr, (void *)ori_src_addr, uiLength); + *p_dst_addr = src_addr; + *p_dst_size = compress_size; + return 0; + } else { + return -1; + } + return 0; + } + } +#endif + return -1; +} +#endif + +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; +#if (UITRON_FW == ENABLE) + BININFO *pBinInfo; +#endif + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + } else { + pHeadInfo->ModelextAddr = 0; +#if (UITRON_FW == ENABLE) + pBinInfo = (BININFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + pBinInfo->ld.Resv[0] = LoaderInternalInfo[1]; + pBinInfo->ld.LdPackage = (LoaderInternalInfo[3] & 0xFFFF); +#endif + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + BOOTINFO *p_ld; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + p_ld = &p_shminfo->boot; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getLdrElapse(); + p_ld->LdResvSize = 0; //unused + p_ld->FWResvSize = 0; //unused + return 0; +} + +_THUMB2 static int bl_is_smp(unsigned char *p_fdt) +{ +#if (FDT_SUPPORT) + int len; + const char *nodep; + nodep = (const char *)bl_get_fdt_property(p_fdt, PATH_NVT_INFO, PROPERTY_NVT_LINUX_SMP, &len); + debug_msg_var("nodep", (UINT32)nodep); + if (nodep == NULL) { + return 0; + } + debug_msg((char *)nodep); + if (strcmp(nodep, "NVT_LINUX_SMP_ON") == 0) { + return 1; + } + return 0; +#else + return 0; +#endif +} + +#if !REMOVED_FLASH +_THUMB2 int bl_boot_uboot(unsigned char *p_fdt) +{ +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + UINT32 No_CPU; +#endif + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update shminfo + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_shminfo->boot.LdPackage = p_param[3] & 0xFFFF; + p_shminfo->boot.LdStorage = (p_param[3] >> 16) & 0xFF; + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + UINT32 isSMP = bl_is_smp(p_fdt); + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + No_CPU = *(UINT32 *)0xFFD00004; + No_CPU &= 0x3; + debug_msg_var("core No.=", No_CPU+1); +#endif + // init cpu timer +// bl_cpu_timer_init(CPU_TIMER_SETTING); +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if (!isSMP || !No_CPU) +#else + if (!isSMP) +#endif + { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + debug_msg_var("Bin core=", isSMP+1); +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + } else { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + // init cpu timer + bl_cpu_timer_init(global_timer_freq); + + bl_smp_start(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader +#else + //bl_smp_start(p_fdt, p_headinfo->CodeEntry); + debug_err("not support smp\r\n"); +#endif + } + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_boot_nuttx(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->nuttx_addr + BIN_INFO_OFFSET_NUTTX); + + if (bl_chk_uboot(p_dram_partition->nuttx_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + // start cpu2 + if (p_dram_partition->nuttx_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-nuttx_addr ", (int)p_dram_partition->nuttx_addr); + debug_err_var("bin-nuttx_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + bl_cpu_timer_init(CPU_TIMER_SETTING); + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot nuttx and never return back to loader + return 0; +} +#endif + +_THUMB2 static int bl_boot_teeos(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + + // update uboot addr for teeos + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR] = p_dram_partition->uboot_addr; + + +#if 0 //do not checksum, because teeos header has removed cause checksum failed + if (bl_chk_uboot(p_dram_partition->teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } +#endif + + //flush uboot + CPUflushWriteCache(p_dram_partition->uboot_addr, p_dram_partition->uboot_size); + //flush teeos + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + bl_cpu_timer_init(CPU_TIMER_SETTING); + // boot core2 (after teeos is loaded) + if (HEADINFO_UBOOT(p_dram_partition)->BinCtrl & 0x00000002) { + //if SMP, trigger core2 + debug_msg("smp(tee)\r\n"); + bl_core2_prepare(p_dram_partition, p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } else { + debug_msg_var("not smp\r\n", p_headinfo->BinCtrl); + } +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot teeos and never return back to loader + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + unsigned int ver; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + BOOTINFO *p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + + return 0; +} + +// return uItron_fw_addr +_THUMB2 unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + //if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + if (1) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->nuttx_size == 0 && p_dram_partition->teeos_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if (p_dram_partition->nuttx_size) { +#if (NUTTX_SUPPORT) + // load nuttx + er = bl_load_nuttx_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load nuttx failed\r\n"); + } + er = bl_boot_nuttx((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot nuttx failed\r\n"); + } +#else + bl_displayErrMsg("NUTTX_SUPPORT disabled\r\n"); +#endif + } else if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } + return er; + } else { + // update rtos information + // the following is for uncompressed-rtos only, others needing uboot + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return bl_load_rtos_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + } +} +#endif + +// return uItron_fw_addr, no need to fully decode +_THUMB2 static unsigned int bl_process_rtos_only(UINT32 uiFwBuf, UINT32 uiFwBufSize, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + UINT32 uItron_fw_addr; + NVTPACK_BFC_HDR *pBFC; + HEADINFO *p_headinfo; + + debug_msg("\r\nbl_process_rtos_only\r\n"); + pBFC = (NVTPACK_BFC_HDR *)uiFwBuf; + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 compressSize; + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + LZ_Un_compress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + compressSize = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //debug_dump_addr(tmpBuf,0x200); + debug_msg_var("F compress uItron_fw_addr", uItron_fw_addr); + // uiFwBuf has adjusted on bl_load_rtos_from_non_nvtpack() + *p_comp_addr = uiFwBuf; + *p_comp_size = compressSize; + } else { + p_headinfo = (HEADINFO *)(uiFwBuf + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + + debug_msg_var("Normal uItron_fw_addr", uItron_fw_addr); + *p_comp_addr = 0; + *p_comp_size = 0; + } + return uItron_fw_addr; +} +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } else if (p_dram_partition->rtos_addr == 0 || DUAL_RTOS_SUPPORT || (gFastbootKeyCallBack == NULL) || (!gFastbootKeyCallBack())) { + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +/** + bl_process_update_loader. + + Write loader will update loader binary file + + @param[in] loader_addr loader in DRAM starting address + @param[in] loader_size loader code length (from loader header offset 0x24) + @return void +*/ +_THUMB2 static int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card + if(is_data_area_encrypted() == 0) { + +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + //UINT32 uiOffset; + //uiOffset = *((UINT32 *)(loader_addr + 0x80)); + //if(uiOffset) {//Combo loader + // if(*(UINT32*)0xF00100F0 == 0x50210000) { + // debug_msg("combo loader 528\r\n"); + // bl_checkLoader(loader_addr+uiOffset, COMBINATION_LOADER_SIZE - uiOffset); //check 528 + // } else{ + // debug_msg("combo loader 52X\r\n"); + // bl_checkLoader(loader_addr, loader_size); //check 52x + // } + //}else + bl_checkLoader(loader_addr, loader_size); +#else +#if 0//(LOADER_TYPE == COMBINATION_528) + debug_msg("CB8\r\n"); + bl_checkLoader(loader_addr + loader_size, (COMBINATION_LOADER_SIZE - loader_size)); +#else //STAND_ALONE_LOADER or combination 52x loader + //debug_msg("STD\r\n"); + bl_checkLoader(loader_addr, loader_size); +#endif +#endif + } + debug_msg("update loader\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program loader +#if 0 +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + UINT32 uiOffset; + uiOffset = *((UINT32 *)(loader_addr + 0x80)); + if(uiOffset) //Combo loader + loader_size = COMBINATION_LOADER_SIZE; + //If single loader , it already got +#else +#if (LOADER_TYPE == STAND_ALONE_LOADER_560) || (LOADER_TYPE == STAND_ALONE_LOADER_528) +#else //Combination loader + loader_size = COMBINATION_LOADER_SIZE; +#endif +#endif +#endif + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#if UPDATE_EMU_CODE +_THUMB2 static int bl_process_update_emu_firmware(unsigned int emu_addr, unsigned int emu_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +// bl_checkFW(emu_addr, emu_size); + debug_msg("update emu firmware size"); + uart_putSystemUARTStr(Dec2HexStr(emu_size)); + uart_putSystemUARTStr("\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program firmware + if (int_strg_obj->flash_writeSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)emu_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = emu_addr + emu_size; + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)reload_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)emu_addr, (void *)reload_addr, emu_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#endif + +_THUMB2 void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize) +{ + *pLoadAddr = g_rtos_load_addr; + *pTargetAddr = g_rtos_target_addr; + *pSize = g_rtos_size; +} + +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 32 * 1024; // pre-assume 32KB, actual size is parsed from loader + //Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) + UINT32 uiLoaderAddress; + UINT32 uiLogSramAddress; +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; +#endif + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; +// UINT32 uiheapBufferAddr = BaseOfStack + 0x40000; // reserve 16KB for tmp buffer usage + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + + // UART initial sequence + //uart_openSystemUART(); + // rtc reset shutdown timer + // rtc_resetShutDownTimer(); + + + + +#if 0 + // adjust PAD driving (if required) + bl_adjustDriving(); + /* + - @b RTC_PWR_SW_STS: Power on source is PWR_SW + - @b RTC_PWR_VBAT_STS: Power on source is PWR_VBAT + - @b RTC_PWR_VBUS_STS: Power on source is PWR_VBUS + */ + uiPowerOnSrc = rtc_getPWRONSource(); + + if (uiPowerOnSrc & RTC_PWR_SW_STS) { + uart_putSystemUARTStr("\r\nSW PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBAT_STS) { + uart_putSystemUARTStr("\r\nVBAT PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBUS_STS) { + uart_putSystemUARTStr("\r\nVBUS PON\r\n"); + } else if (rtc_getIsAlarmPowerOn()) { + uart_putSystemUARTStr("\r\nPwrAlarm PON\r\n"); + } else { + uart_putSystemUARTStr("\r\nPOR PON\r\n"); + } +#endif + // Display Loader Version + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + + +#if 0 // for now, reduce code size + if (rtc_chkS3boot()) { + UINT32 resume_addr; + + uart_putSystemUARTStr("main selfing..\r\n"); + resume_addr = bl_resume_cpu1((unsigned char *)_BOARD_IPC_ADDR_); + if (resume_addr == 0) { + // in codition for MODELEXT_BUILT_IN_ON + resume_addr = RESUME_ADDR; + } + return resume_addr; + } else { + + uart_putSystemUARTStr("main not selfing..\r\n"); + } +#endif + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + prj_main(); + +#if !(USB_WRITELOADER) + set_usb_suspend(); +#endif + + if(utl_get_bootsrc() == BOOT_SOURCE_UART) + { +#if UART_UPDATE + debug_msg("Boot from UART ...\r\n"); + bl_uart();//never returned. +#else + bl_displayErrMsg("UART_UPDATE must enable on loader\r\n"); +#endif + } + + if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) + { +#if USB_WRITELOADER + debug_msg("Boot from USB ...\r\n"); + bl_usb(); //never returned. +#else + bl_displayErrMsg("USB_WRITELOADER must enable on loader\r\n"); +#endif + } + +#if !(USB_WRITELOADER || UART_UPDATE) + if (bl_load_rtos_from_uart(uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH, &adjusted_addr, &adjusted_size) == 0) { + //specail case, load small rtos from uart + uiUpdateMainBinBufAddr = adjusted_addr; + uiUpdateFileLen = adjusted_size; + uiLoaderFunc |= FUNC_RUN_CARD; + } else if ((int_strg_obj->flash_getBlockSize() == EMMC_BLOCK_SIZE) && gRecoveryTriggerCallBack && gRecoveryTriggerCallBack()) { + debug_msg("Recovery triggered not support currently.\r\n"); +#if 0 + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } else { + flash_mount_fs(0, BaseOfStack + 0x4000, FAT_HEAP_BUFFER_SIZE); + if (flash_mount_partition(g_uiPartitionID) == E_OK) { + if (flash_open_file(RECOVERY_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + g_is_recovery_triggered = TRUE; + } else { + debug_msg("Recovery should be all in one bin!\r\n"); + } + } else { + debug_msg("no recovery bin!\r\n"); + } + } else { + debug_msg("Partition error!\r\n"); + } + } +#endif + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack == NULL) || gCardDetectCallBack())) { + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack != NULL) || (gCardDetectCallBack() == FALSE))) { + debug_msg("No card inserted\r\n"); + } +#endif + + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +#if (REMOVED_FLASH == ENABLE) + bl_displayErrMsg("cannot process all-in-one fw"); +#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +#endif + } else { + // non-all-in-one flow + // check valid + if (uiLoaderFunc & FUNC_UPDATE_FW) { +#if UPDATE_EMU_CODE + bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +#else + bl_displayErrMsg("cannot write non-all-in-one fw"); +#endif + } + uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + } + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } + +#else + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + } + +#if UPDATE_EMU_CODE + debug_msg_var("emu fw len", uiUpdateFileLen); +#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} + +_THUMB2 void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback) +{ + gSpecialKeyCallBack = callback; +} + +_THUMB2 void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback) +{ + gCardDetectCallBack = callback; +} + +_THUMB2 void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback) +{ + gRecoveryTriggerCallBack = callback; +} + +_THUMB2 void loader_installFastbootKeyCB(LDR_FASTBOOT_KEY_CB callback) +{ + gFastbootKeyCallBack = callback; +} + +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.jack b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.jack new file mode 100755 index 000000000..9cee3e1ea --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.c.jack @@ -0,0 +1,3221 @@ +/* + Main control function + + This file is implement by user mode + + @file bl_func.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "bl_func.h" +#include "Cache.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "CC.h" +#include "loader.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "emb_partition_info.h" +#include "modelext_parser.h" +#include "bin_info.h" +#include "shm_info.h" +#include "gic.h" +#include "libfdt.h" +#include +#include "bl_u2.h" +#include "crypto.h" +#include "nand.h" +#include "nor.h" + +//#if (LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +//static uint32_t global_timer_freq = 3000000; //3MHz = 3000000 Hz +//#endif +PSTORAGE_OBJ int_strg_obj = NULL; + +#define FW_PART1_SIZE_OFFSET (CODE_SECTION_OFFSET + 0x04) //ref to CodeInfo.S on rtos (addr of _section_01_size) +//#define TEE_HEADER_SIZE 0x1C // refer to: optee_header_t + +#define _THUMB2 __attribute__((target("thumb2"))) + +#define bl_memcpy utl_memcpy +#define bl_memset utl_memset +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#define SIZE_PRELOAD 0x400 +#define SIZE_PRESERVE_USB 0x2000 + +#define HEADINFO_UBOOT(p_parti) ((HEADINFO *)(p_parti->uboot_addr + BIN_INFO_OFFSET_UBOOT)) +#define HEADINFO_TEEOS(p_parti) ((HEADINFO *)(p_parti->teeos_addr + BIN_INFO_OFFSET_TEEOS)) +#define IS_BIN_OVERLAP(addr1, size1, addr2, size2) (!(((addr1 + size1 - 1) < addr2) || (addr1 > (addr2 + size2 - 1)))) + +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +extern void set_usb_suspend(void); +#endif + +#if (_ROM_PUBLIC_API_ == 1) +#define ROM_LZMA_POSITION 0x7fd0 +UINT8 lzma_temp_buffer[65536]; +int (*rom_lzma_inflate)(UINT8 *in_ptr, UINT32 in_size, UINT8 *out_ptr, UINT32 out_size, UINT8 *p_tmp, UINT32 tmp_size); +#endif + +extern char _loader_exec_compres_start[]; +//extern char _load_nand_table_start_base[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base[]; +extern void core1_reset(void); + +// Function from Timer.c +//extern UINT32 timer_getLdrElapse(void); + +// Define in MakeConfig.txt +static UINT8 UPDATE_FW_NAME[] = {"FW98520A.BIN"}; +static UINT8 UPDATE_LOADER_NAME[] = {"LD98520A.BIN"}; +static UINT8 RUN_FW_NAME[] = {"FW98520T.BIN"}; +static UINT8 *LOADER_START_STR = {(UINT8 *)"\r\nLoader Start ..."}; +//#if !USB_WRITELOADER +#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"WRKEY.BIN"}; +#if UPDATE_SIM_CODE +static UINT8 *RUN_WRKEY_NAME = {(UINT8 *)"SIM.BIN"}; +#endif +#endif +static UINT8 RECOVERY_FW_NAME[] = {"FW98520R.BIN"}; +static UINT32 g_uiPartitionID = 2; + +static UINT32 g_uiVersion = 0; + +// Error message +static char FWErrorMsg[] = "\r\nFW check fail\r\n"; +static char RWErrorMsg[] = "\r\nR/W error\r\n"; +static char LoaderErrorMsg[] = "\r\nLoader check fail\r\n"; + +UINT32 TopOfStack; +UINT32 BaseOfStack; + +extern char _loader_heap_base[]; + +static BOOL g_is_flash_open = FALSE; // indicate flash is open for updating non-fully all-in-one bin. + +static LDR_FASTBOOT_KEY_CB gFastbootKeyCallBack = NULL; +static LDR_SPECIAL_KEY_CB gSpecialKeyCallBack = NULL; +static LDR_CARD_DETECT_CB gCardDetectCallBack = NULL; +static STORAGEINT gStorageIntType = STORAGEINT_UNOKNOWN; + +static LDR_RECOVERY_TRIGGER_CB gRecoveryTriggerCallBack = NULL; +//#if (!USB_WRITELOADER) +//#if (STORAGE_EXT_TYPE != STORAGE_EXT_USB) +//static BOOL g_is_recovery_triggered = FALSE; // indicate recovery flow is triggered. +//#endif +_THUMB2 static int bl_is_smp(unsigned char *p_fdt); +static UINT32 g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; +static UINT32 g_uiNandBlkSize = 0; +static UINT32 g_rtos_load_addr = 0; +static UINT32 g_rtos_target_addr = 0; +static UINT32 g_rtos_size = 0; + +#if (FDT_SUPPORT) +#define PATH_MEM_DRAM "/nvt_memory_cfg/dram" +#define PATH_MEM_LOADER "/nvt_memory_cfg/loader" +#define PATH_MEM_UBOOT "/nvt_memory_cfg/uboot" +#define PATH_MEM_FDT "/nvt_memory_cfg/fdt" +#define PATH_MEM_SHMEM "/nvt_memory_cfg/shmem" +#define PATH_MEM_RTOS "/nvt_memory_cfg/rtos" +#define PATH_MEM_NUTTX "/nvt_memory_cfg/nuttx" +#define PATH_MEM_TEEOS "/nvt_memory_cfg/teeos" +#define PATH_MEM_HDAL "/hdal-memory/media" +#define PATH_MEM_CORE2_ENTRY1 "/nvt_memory_cfg/core2entry1" +#define PATH_MEM_CORE2_ENTRY2 "/nvt_memory_cfg/core2entry2" +#define PATH_NVT_INFO "/nvt_info" +#define PATH_NVTPACK_INDEX "nvtpack/index" +#define PATH_PARTITION_LOADER "partition_loader" +#define PATH_PARTITION_FDT "partition_fdt" +#define PATH_PARTITION_UBOOT "partition_uboot" +#define PATH_PARTITION_NUTTX "partition_nuttx" +#define PATH_PARTITION_TEEOS "partition_teeos" +#define PATH_PARTITION_RTOS "partition_rtos" +#define PROPERTY_REG "reg" +#define PROPERTY_LABEL "label" +#define PROPERTY_PARTITION_NAME "partition_name" +#define PROPERTY_NVT_LINUX_SMP "NVT_LINUX_SMP" +static DRAM_PARTITION g_dram_partition = {0}; +static EMB_PARTITION g_emb_uboot = {0}; +static EMB_PARTITION g_emb_teeos = {0}; +static EMB_PARTITION g_emb_rtos = {0}; +#else // NO FDT_SUPPORT +// refer to met-tbl.dtsi /nvt_memory_cfg +static DRAM_PARTITION g_dram_partition = { + .dram_addr = 0x00000000, + .dram_size = 0x20000000, + .rev_addr = 0x00007E00, ///< shmem + .rev_size = 0x00000200, ///< shmem + .loader_addr = 0x01000000, + .loader_size = 0x00800000, + .fdt_addr = 0x01800000, + .fdt_size = 0x00040000, + .uboot_addr = 0x1E000000, + .uboot_size = 0x01FC0000, + .rtos_addr = 0x01840000, ///< optional, only for fast-boot, + .rtos_size = 0x00780000, ///< optional, only for fast-boot + .core2_entry1_addr = 0x00000000, ///< optional, only for dual core IC (fixed here, and must be) + .core2_entry1_size = 0x00004000, ///< optional, only for dual core IC + .core2_entry2_addr = 0x1FFC0000, ///< optional, only for dual core IC (address better in the bottom of dram to avoid memory space overlap) + .core2_entry2_size = 0x00040000, ///< optional, only for dual core IC +}; +// refer to storage-partition.dtsi +static EMB_PARTITION g_emb_uboot = { + .PartitionOffset = 0xC0000, + .PartitionSize = 0xA0000, +}; +static EMB_PARTITION g_emb_rtos = { ///< optional, only for fast-boot, + .PartitionOffset = 0x2B40000, + .PartitionSize = 0xA00000, +}; +static EMB_PARTITION g_emb_teeos = { ///< optional, only for optee, + .PartitionOffset = 0, + .PartitionSize = 0, +}; +//following just for processing all-in-one bin (nvtpack) +//refer to nvtpack.dtsi +#define NVTPACK_IDX_UBOOT 3 +#define NVTPACK_IDX_TEEOS -1 +#define NVTPACK_IDX_RTOS 10 +#endif + + + +#if (UART_UPDATE_ == ENABLE) +static char g_strLength[80]; // buffer to store length string +#endif + +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +int bl_boot_uboot(unsigned char *p_fdt); + +/** + Display error message. + + Display error message. + CPU loop forever and LED is red. + + @param Msg: Message to display + @return void +*/ +_THUMB2 static void bl_displayErrMsg(char *Msg) +{ + // Display error message to UART + debug_msg(Msg); + // Loop forever + while (1) { + ; + } +} + + +/** + Invert endianess of input word + + + @param[in] a input word + + @return translated word +*/ +_THUMB2 static UINT32 invertEndian(UINT32 a) +{ + return __builtin_bswap32(a); +} + + +/** + Check FW code. + + Check FW code and file length. + The FW binary file must be post-proecessd by encrypt_bin.exe. + This function must sync to encrypt_bin.exe. + If FW checking is fail, the CPU will loop forever and LED is red. + + @param[in] uiAddress FW code in DRAM starting address + @param[in] uiFileLen FW code length + @return void +*/ +_THUMB2 static void bl_checkFW(UINT32 uiAddress, UINT32 uiFileLen) +{ + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)uiAddress; + mem.len = uiFileLen; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + bl_displayErrMsg(FWErrorMsg); + } +} + +/** + Check boot loader code. + + Check boot loader code. + + @return void +*/ +_THUMB2 static void bl_checkLoader(UINT32 uiAddr, UINT32 uiSize) +{ + UINT16 *puiValue, uiSum; + UINT32 i; + + puiValue = (UINT16 *)uiAddr; + uiSum = 0; + + for (i = 0; i < (uiSize >> 1); i++) { + uiSum += (*puiValue + i); + puiValue++; + } + + if ((*(UINT16 *)(uiAddr + LOADER_TAG_OFFSET) != LOADER_TAG_VALUE) || + (uiSum != 0)) { + bl_displayErrMsg(LoaderErrorMsg); + } +} +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) + + +_THUMB2 static void get_bininfo_size_offset(unsigned char* bininfo,unsigned int* size,unsigned int *offset) +{ + /****this headinfo is for encrypt header + BinInfo will set partition offset and size + BinInfo_1[0~3] public key offset + BinInfo_1[4~7] public key length + BinInfo_2[0~3] signature offset + BinInfo_2[4~7] signature length + BinInfo_3[0~3] encrypted offset + BinInfo_3[4~7] encrypted size + BinLength total bin size + Checksum total bin checksum + others parameters set 0 + */ + *size = bininfo[4] | bininfo[5]<<8 | bininfo[6] << 16 | bininfo[7] << 24; + *offset = bininfo[0] | bininfo[1] << 8 | bininfo[2] << 16 | bininfo[3] <<24; +} + + + + +_THUMB2 static int decrypt_aes_cbc(unsigned int input, unsigned int output, unsigned int len) +{ + + CRYPT_OP crypt_op_param; + if(len &0x0f) + { + debug_msg_var("enc size", len); + debug_err("not align 16\r\n"); + return -21; + } + if((input & 0x03) || (output & 0x03) || (len & 0x03) ){ //check word alignment + //debug_msg_var("input", input); + //debug_msg_var("output", output); + //debug_msg_var("len", len); + //debug_err("not word align\r\n"); + return -22; + } + crypt_op_param.op_mode = CRYPTO_CBC; + crypt_op_param.en_de_crypt = CRYPTO_DECRYPT; + crypt_op_param.src_addr = input; + crypt_op_param.dst_addr = output; + crypt_op_param.length = len; //Need align to 16bytes align + //debug_msg_var("src",(unsigned int)crypt_op_param.src_addr); + //debug_msg_var("dst",(unsigned int)crypt_op_param.dst_addr); + + #if 0 + debug_msg_var("input",input); + debug_msg_var("output",output); + debug_msg_var("len",len); + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + debug_msg_var("encryped buf addr",(unsigned int)tmp); + for(i=0;i<16;i++){ + debug_msg_var("encryped buf",(unsigned int)tmp[i]); + } + #endif + if(crypto_data_operation(EFUSE_OTP_1ST_KEY_SET_FIELD, crypt_op_param) != 0) + { + //debug_err("aes dec fail\r\n"); + return -23; + } + #if 0 + unsigned char *tmp = (unsigned char *) crypt_op_param.src_addr; + int i=0; + tmp = (unsigned char *) crypt_op_param.dst_addr; + debug_msg_var("decryped addr",(unsigned int)&tmp[0]); + for(i=0;i<16;i++){ + debug_msg_var("decryped buf",(unsigned int)tmp[i]); + } + + #endif + return 0; + +} +#if (SECURE_SIGNATURE_BY_AES == 0) +_THUMB2 static void data_reverse(unsigned char* input_data, unsigned int size) +{ + unsigned int i=0; + unsigned char tmp=0; + for(i=0;i< (size/2);i++) + { + tmp = input_data[size - 1 - i]; + input_data[size - 1 - i] = input_data[i]; + input_data[i] = tmp; + } + +} +#endif +_THUMB2 static int do_decrypt_aes(unsigned int input_data, unsigned int output_data, unsigned int* output_size,unsigned int partition_size) +{ + + unsigned int encrypt_offset =0; + unsigned int encrypt_size =0; + unsigned int data_size = 0; + HEADINFO *p_headinfo = (HEADINFO *)input_data; + int er=0; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_3, &encrypt_size, &encrypt_offset); + data_size = p_headinfo->BinLength - encrypt_offset; +#if 1 //for signature check + unsigned int signature_offset =0; + unsigned int signature_size = 0; + UINT32 hash_buf[8]; + unsigned int sha256_align_size =0; + UINT32 * signature_buff = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_2, &signature_size, &signature_offset); + #if (SECURE_SIGNATURE_BY_AES == 0) + unsigned int key_offset =0; + unsigned int key_size =0; + unsigned int n_size=0; + unsigned int e_size=0; + UINT32 sign_rsa_output[64]; + UINT32 *key_n = NULL; + UINT32 *key_e = NULL; + UINT32 *signature_addr = NULL; + get_bininfo_size_offset((unsigned char *)p_headinfo->BinInfo_1, &key_size, &key_offset); + n_size = signature_size;// if rsa 2048 , signature_size should be 256 bytes + e_size = key_size - n_size; + key_n = (UINT32 *)(input_data + key_offset); + // now only support rsa 2048 + key_e = (UINT32 *)(input_data + key_offset + signature_size); // signature_size should be 256 bytes, n key should be 256 + data_reverse((unsigned char *)(key_n),n_size); + data_reverse((unsigned char *)(key_e),e_size); + + er = rsa_keycheck(key_n, 1);// check rsa n key in efuse 1 and 2 field, 0 field for aes key + if(er == 0) + { + debug_err("key fail\r\n"); + return -20; + } + signature_addr = (UINT32 *)(input_data + signature_offset); + data_reverse((unsigned char *)signature_addr, signature_size); + + //decrypt signature + rsa_decrypt(signature_addr, signature_size, key_n, n_size, key_e, e_size,sign_rsa_output); + + data_reverse((unsigned char *)sign_rsa_output, signature_size); + + //remove pending data 0, the last 32 bytes will be signature data + signature_buff = (UINT32 *)&sign_rsa_output[(sizeof(sign_rsa_output)/4 ) - (32/4 )];// offset need devided by 4, because of UINT32 type + #else + //UINT32 sign_aes_output[8]; + + er = decrypt_aes_cbc((UINT32 )(input_data + signature_offset), output_data,signature_size); + if(er != 0) + { + debug_err("decrypt_aes_cbc fail\r\n"); + return -20; + } + signature_buff =(UINT32 *)output_data; + + #endif + //hash encrypt data + + if((data_size & 0x3f) != 0) + { + // hardware sha256 need align 64, need set pending 0 + sha256_align_size = ((data_size/0x40) + 1)*0x40; + bl_memset((unsigned char *)(input_data + encrypt_offset + data_size),0, sha256_align_size - data_size); + } + else + { + sha256_align_size = data_size; + } + + shahw((unsigned char *)(input_data + encrypt_offset), sha256_align_size, hash_buf); + + + //compare signature and current hash + if(memcmp((void *)hash_buf, (void *)signature_buff, sizeof(hash_buf)) != 0) + { + debug_err("sig fail\r\n"); + return -20; + } +#endif + + //decrypt data + //dma addr should 4 alignment, input_data address is 4 alignment + if((input_data + encrypt_offset) & 0x03) + { + utl_memcpy((void *)input_data,(unsigned char*)(input_data + encrypt_offset), data_size); + er = decrypt_aes_cbc(input_data, output_data, encrypt_size); + } + else + { + er = decrypt_aes_cbc(input_data + encrypt_offset, output_data, encrypt_size); + } + if(er != 0) + { + debug_err("aes fail\r\n"); + return er; + } + + *output_size = data_size; + + //add plaintext data to output buf--> aes should 16 alignment, if data not alignment, the last bytes we will not encrypt data + int plaintext_size = data_size - encrypt_size; + unsigned char *p_output = (unsigned char *)output_data; + if( plaintext_size > 0) + { + utl_memcpy(&p_output[encrypt_size], (unsigned char*)(input_data + encrypt_offset+ encrypt_size),plaintext_size); + } + return 0; + +} +#endif + +//#NT#2013/04/25#Steven Wang -begin +//#NT#Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) +void BL_showROMLog(UINT32 buffer) +{ + UINT32 value; + UINT32 index; + UINT32 P_duty; + UINT32 N_duty; + UINT32 diff; + + index = 0; + diff = 0; + P_duty = 0; + N_duty = 0; + uart_putSystemUARTStr("\r\n"); + while (1) { + value = INREG32(buffer + index); + + if ((value & 0xF0000000) == 0xF0000000) { + value &= ~(0x40000000); + uart_putSystemUARTStr(Dec2HexStr(value)); + uart_putSystemUARTStr(" = "); + } + + else if ((value & 0xF0000000) == 0x50000000) { + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x20000000) { +// uart_putSystemUARTStr("P_duty = "); + P_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(P_duty)); + uart_putSystemUARTStr("\r\n"); + } + + else if ((value & 0xF0000000) == 0x30000000) { +// uart_putSystemUARTStr("N_duty = "); + N_duty = value & 0xFFFFFFF; + //uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr(Dec2HexStr(N_duty)); + uart_putSystemUARTStr("\r\n"); + if (P_duty > N_duty) { + if (diff == 2) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 1; + } + } else { + if (diff == 1) { + uart_putSystemUARTStr("============\r\n"); + P_duty = 0; + N_duty = 0; + diff = 0; +// diff = 3; + } else { + diff = 2; + } + } + } else if ((value & 0xF0000000) == 0x60000000) { + uart_putSystemUARTStr("N+P = "); + uart_putSystemUARTStr(Dec2HexStr(value & 0xFFFFFFF)); + uart_putSystemUARTStr("\r\n"); + } else if ((value & 0xF0000000) == 0x70000000) { + if ((value & 0xFFFFFFF) == 0x0654321) { + break; + } + } else { + uart_putSystemUARTStr("Unknow \r\n"); + } + index += 4; + } + uart_putSystemUARTStr("\r\n[0xC0001000] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC0001000))); + uart_putSystemUARTStr(" [0xC000101C] = 0x"); + uart_putSystemUARTStr(Dec2HexStr(INREG32(0xC000101C))); + uart_putSystemUARTStr("\r\n"); +} +#endif +//#NT#2013/04/25#Steven Wang -end + + +#if (DRAM_RANGE_SCAN_EN == ENABLE) +/** + Check Sram code. + + Check is dram scan code or not + + @param[in] uiAddress Scan FW code in DRAM starting address + @return void +*/ +static BOOL bl_checkDramScanFW(UINT32 uiAddress) +{ + if ((*(UINT32 *)uiAddress & SRAM_TAG) == SRAM_TAG) { + return TRUE; + } else { + return FALSE; + } +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} +#endif + +/* + Update multi-binary image + + + @param[in] uiFwBuf buffer store fw read from card + + @return + -@ b TRUE: success + -@ b FALSE: fail +*/ + +#if !REMOVED_FLASH +#if 0 +static void bl_interrupt_init(void) +{ + debug_msg("arm_gic_distif_setup\r\n"); + arm_gic_distif_setup(); + debug_msg("arm_gic_cpuif_setup\r\n"); + arm_gic_cpuif_setup(); + + // + //debug_dump_addr(0xF1500000+0x1000,0x500); + //debug_dump_addr(0xF1500000+0x2000,0x100); +} +#endif + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +#define OUTW(addr,value) (*(UINT32 volatile *)(addr) = (UINT32)(value)) +#define INW(addr) (*(UINT32 volatile *)(addr)) + + +static void bl_cpu_timer_init(UINT32 value) +{ + UINT32 dwVal; + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_LOAD_OFFSET, value); + + dwVal = INW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET); + /* Enable Auto reload mode. */ + dwVal |= ARM_TIMER_CONTROL_AUTO_RELOAD_MASK; + /* Clear prescaler control bits */ + dwVal &= ~ARM_TIMER_CONTROL_PRESCALER_MASK; + /* Set prescaler value */ + dwVal |= ((CYGHWR_HAL_RTC_PRESCALER - 1) << ARM_TIMER_CONTROL_PRESCALER_SHIFT); + /* Enable the decrementer */ + //dwVal |= ARM_TIMER_CONTROL_ENABLE_MASK; + /* Enable the interrupt */ + dwVal |= ARM_TIMER_CONTROL_IRQ_ENABLE_MASK; + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_CONTROL_OFFSET, dwVal); + + OUTW(configARM_TIMER_BASEADDR + ARM_TIMER_ISR_OFFSET, + ARM_TIMER_ISR_EVENT_FLAG_MASK); + +} +#endif +#endif +_THUMB2 int bl_flash_open(void) +{ + int er; + //UINT32 uiStorageVersion = (UINT32)&_load_nand_table_start_base; + + if (g_is_flash_open) { + return 0; + } + //========================================================================== + //= User define SPI-NAND id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); + + //========================================================================== + //= User define SPI-NOR id table sample code = + //= You can remove // to use it = + //========================================================================== + //int_strg_obj->flash_installIdentifyCB(nor_identify); + + er = int_strg_obj->flash_open(); + if (er < 0) { + debug_err("flash open fail\r\n"); + return -1; + } + + //OUTREG32(NAND_TABLE_VERSION_ADDR, INREG32(uiStorageVersion)); + + //if (er == E_OK) { + // OUTREG32(NAND_TABLE_FLAG_ADDR, 0x46495053); //'S''P''I''F' + //} else { // E_OK_TABLE_FOUND(1) or E_OK_TABLE_NOT_FOUND(2) + // OUTREG32(NAND_TABLE_FLAG_ADDR, er); + //} + g_uiNandBlkSize = int_strg_obj->flash_getBlockSize(); + if (g_uiNandBlkSize == 0x10000) { + debug_msg("SPI NOR\r\n"); + g_uiStartBlkUpdateFW = 1; + } else if (g_uiNandBlkSize == EMMC_BLOCK_SIZE) { + debug_msg("EMMC\r\n"); + g_uiStartBlkUpdateFW = FDT_OFFSET / EMMC_BLOCK_SIZE; + } else { + g_uiStartBlkUpdateFW = StartNandBlkUpdateFW; + } + + g_is_flash_open = TRUE; + return 0; +} + +#if 0 //[-Werror=unused-function] +static int bl_flash_close(void) +{ + if (!g_is_flash_open) { + return 0; + } + + flash_close(); + g_is_flash_open = FALSE; + return 0; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset; /* next node offset from libfdt */ + const void *nodep; /* property node pointer */ + + nodeoffset = fdt_path_offset(p_dtb, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} + +_THUMB2 static const void *bl_get_fdt_nvt_memory_cfg_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + static int nodeoffset_nvt_memory_cfg = -FDT_ERR_NOTFOUND;; /* next node offset from libfdt */ + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (strncmp(p_path, "/nvt_memory_cfg/", 3) != 0) { + debug_err("path prefix must be /nvt_memory_cfg/\r\n"); + return NULL; + } + + if (nodeoffset_nvt_memory_cfg == -FDT_ERR_NOTFOUND) { + nodeoffset_nvt_memory_cfg = fdt_path_offset(p_dtb, "/nvt_memory_cfg"); + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_nvt_memory_cfg, &p_path[16]); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + + +_THUMB2 static unsigned char *bl_get_fdt_cfg(const void *p_dtb, MODELEXT_TYPE type) +{ +#if (FDT_SUPPORT) + int len; + const int *nodep; + + UINT8 *p_rt = NULL; + + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_DRAM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get dram fail\r\n"); + return NULL; + } + g_dram_partition.dram_addr = be32_to_cpu(nodep[0]); + g_dram_partition.dram_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_LOADER, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get loader fail\r\n"); + return NULL; + } + g_dram_partition.loader_addr = be32_to_cpu(nodep[0]); + g_dram_partition.loader_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_UBOOT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get uboot fail\r\n"); + return NULL; + } + g_dram_partition.uboot_addr = be32_to_cpu(nodep[0]); + g_dram_partition.uboot_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_FDT, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get fdt fail\r\n"); + return NULL; + } + g_dram_partition.fdt_addr = be32_to_cpu(nodep[0]); + g_dram_partition.fdt_size = be32_to_cpu(nodep[1]); + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_RTOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.rtos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.rtos_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_NUTTX, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.nuttx_addr = be32_to_cpu(nodep[0]); + g_dram_partition.nuttx_size = be32_to_cpu(nodep[1]); + } + + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_TEEOS, PROPERTY_REG, &len); + if (nodep != NULL) { + g_dram_partition.teeos_addr = be32_to_cpu(nodep[0]); + g_dram_partition.teeos_size = be32_to_cpu(nodep[1]); + } + + p_rt = (UINT8 *)&g_dram_partition; + break; + + case MODELEXT_TYPE_BIN_INFO: + nodep = (const int *)bl_get_fdt_nvt_memory_cfg_property(p_dtb, PATH_MEM_SHMEM, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("dtb get shmem fail\r\n"); + return NULL; + } + + if (sizeof(SHMINFO) > be32_to_cpu(nodep[1])) { + debug_err("shmem size mismatch\r\n"); + return NULL; + } + + p_rt = (UINT8 *)be32_to_cpu(nodep[0]); + break; + + default: + debug_err_var("not handle type\r\n", type); + return NULL; + } + return p_rt; +#else // NO FDT_SUPPORT + switch (type) { + case MODELEXT_TYPE_DRAM_PARTITION: + return (UINT8 *)&g_dram_partition; + case MODELEXT_TYPE_BIN_INFO: + return (UINT8 *)g_dram_partition.rev_addr; + default: + return NULL; + } +#endif +} + +_THUMB2 int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one) +{ + NVTPACK_ER er; + NVTPACK_VER ver; + + er = nvtpack_getver(p_mem_all_in_one, &ver); + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + if (ver == NVTPACK_VER_16072017) { + return 0; + } + + return -1; +} + + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_fdt(unsigned int addr, unsigned int size) +{ + DRAM_PARTITION *p_dram_partition = NULL; + + if (fdt_check_full((void *)addr, size) != 0) { + debug_err("invalid dtb\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)addr, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("invalid dram_partition\r\n"); + return -1; + } + + // check tmp memory (file load) cannot overlap with uboot and teeos + // we allow to overlap with linux, root-fs because uboot will reload bin file later + debug_msg_var("tmp_addr", SDRAM_Start_FW); + +// if ((addr < p_dram_partition->uboot_addr && addr + size > p_dram_partition->uboot_addr) || +// (addr > p_dram_partition->uboot_addr && addr + size < p_dram_partition->uboot_addr + p_dram_partition->uboot_size)) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->uboot_addr, p_dram_partition->uboot_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("uboot olp\r\n"); + return -1; + } +#if 1 + //if ((addr < p_dram_partition->teeos_addr && addr + size > p_dram_partition->teeos_addr) || + // (addr > p_dram_partition->teeos_addr && addr + size < p_dram_partition->teeos_addr + p_dram_partition->teeos_size)) { + if (p_dram_partition->teeos_size) { + if (IS_BIN_OVERLAP(addr, size, p_dram_partition->teeos_addr, p_dram_partition->teeos_size)) { + debug_err_var("a", addr); + debug_err_var("s", size); + debug_err("teeos olp\r\n"); + return -1; + } + } +#endif + // check if memory size matched real size + UINT32 ld_dram1_size = dma_get_dram_capacity(DMA_ID_1); + if (p_dram_partition->dram_size > ld_dram1_size) { + debug_err_var("fw_d1_s", p_dram_partition->dram_size); + debug_err_var("ld_d1_s", ld_dram1_size); + debug_err("d1 s not matched.\r\n"); + return -1; + } + return 0; +} +#endif + +#if !REMOVED_FLASH +_THUMB2 int bl_chk_uboot(unsigned int addr, unsigned int size) +{ +#if (_FPGA_EMULATION_ == 0) + NVTPACK_MEM mem = {0}; + mem.p_data = (void *)addr; + mem.len = size; + if (nvtpack_calc_nvt_sum(&mem) != 0) { + debug_err("uboot check sum fail"); + return -1; + } +#endif + return 0; +} + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) +static void bl_core2_reset(void) +{ + UINT32 core_reg; + + debug_msg("core2_reset\r\n"); + + core_reg = *(volatile UINT32 *)0xF0E400F0; + core_reg &= ~(1<<3); + core_reg &= ~(1<<11); + *(volatile UINT32 *)0xF0E400F0 = core_reg; + core_reg |= (1<<2)|(1<<10) | (1<<21); + core_reg |= (1<<17); + *(volatile UINT32 *)0xF0E400F0 = core_reg; +} + +static void bl_core2_prepare(DRAM_PARTITION *p_dram_partition, unsigned int last_addr) +{ + extern char _load_core2_jump_program_start_base[]; + extern char _load_core2_jump_program_end_base[]; + extern char _load_core2_entry_program_start_base[]; + extern char _load_core2_entry_program_end_base[]; + UINT32 code2JumpCodelen, code2EntryCodelen; + + //check core2_entry1 must at addr 0 + if (p_dram_partition->core2_entry1_addr != CORE2_JUMP_ADDR) { + bl_displayErrMsg("core2entry1 != 0"); + } + + // copy core2 jump code to dram 0x0 + code2JumpCodelen = _load_core2_jump_program_end_base - _load_core2_jump_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry1_addr, _load_core2_jump_program_start_base, code2JumpCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry1_addr, code2JumpCodelen); + + debug_msg_var("core2_jump_program", (int)_load_core2_jump_program_start_base); + debug_msg_var("code2JumpCodelen", (int)code2JumpCodelen); + debug_msg_var("core2_entry2_addr", (int)p_dram_partition->core2_entry2_addr); + + // copy core2 entry code to dram specified by fdt + *(volatile UINT32 *)(NVT_CORE2_START) = p_dram_partition->core2_entry2_addr; + code2EntryCodelen = _load_core2_entry_program_end_base - _load_core2_entry_program_start_base; + utl_memcpy((void *)p_dram_partition->core2_entry2_addr, _load_core2_entry_program_start_base, code2EntryCodelen); +// CPUflushWriteCache(p_dram_partition->core2_entry2_addr, code2EntryCodelen); + + debug_msg_var("core2_entry_program", (int)_load_core2_entry_program_start_base); + debug_msg_var("code2EntryCodelen", (int)code2EntryCodelen); + + *(volatile UINT32 *)0xF07F8000 = last_addr; + + debug_msg_var("0xF07F8000=", (int)*(volatile UINT32 *)0xF07F8000); +} + +static int bl_smp_start(unsigned char *p_modelext, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_modelext, MODELEXT_TYPE_DRAM_PARTITION); + if (p_bininfo == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_modelext); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_modelext; + debug_msg_var("p_bininfo->boot.fdt_addr", p_bininfo->boot.fdt_addr); + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + if(utl_get_bootsrc() == BOOT_SOURCE_UART) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } else if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; + } +#else +// if (card_get_type() == EXT_STORAGE_TYPE_ETH) +// p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +// else if (g_is_recovery_triggered) +// p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; +// else +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; +#else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + debug_msg("smp(no tee)\r\n"); + + bl_core2_prepare(p_dram_partition, 0); + +//#if USB_WRITELOADER +#if 0 + USBStateMachine(); + uart_putSystemUARTStr("USB update Done\n\r"); + timer_delay(1000000); + USBOTGReset(); +#endif + + + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + //reset core2 + bl_core2_reset(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} +#endif +_THUMB2 static int bl_entry_boot(unsigned char *p_fdt, UINT32 uboot_entry) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + + debug_msg_var("fdt", (UINT32)p_fdt); + debug_msg_var("shm", (UINT32)p_bininfo); + + p_bininfo->boot.fdt_addr = (UINT32)p_fdt; + utl_memset(p_bininfo->boot.LdInfo_1, 0, sizeof(p_bininfo->boot.LdInfo_1)); + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + // clear cc_core1_addr, cc_core2_addr +#if USB_WRITELOADER + CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + if(utl_get_bootsrc() == BOOT_SOURCE_USB) { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_USB; + } else { + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_UART; + } +#else + if (card_get_type() == EXT_STORAGE_TYPE_ETH) + p_bininfo->comm.Resv[0] = BOOT_REASON_FROM_ETH; + // else if (g_is_recovery_triggered) + // p_bininfo->comm.Resv[0] = BOOT_REASON_RECOVERY_SYS; + else + p_bininfo->comm.Resv[0] = BOOT_REASON_NORMAL; +#endif + p_bininfo->comm.Resv[1] = 0; // COMM_CORE1_START + p_bininfo->comm.Resv[2] = 0; // COMM_CORE2_START + p_bininfo->comm.Resv[3] = 0; // COMM_UITRON_COMP_ADDR + p_bininfo->comm.Resv[4] = 0; // COMM_UITRON_COMP_LEN + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)uboot_entry; + debug_msg_var("jump", uboot_entry); + p_func(); + } + + return 0; +} + +_THUMB2 int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/) +{ + DRAM_PARTITION *p_dram_partition; + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("bl_copy_fdt_to_fdt_addr failed.\r\n"); + return -1; + } + + // load fdt to fdt buffer + utl_memcpy((void *)p_dram_partition->fdt_addr, p_fdt, fdt_totalsize(p_fdt)); + *pp_fdt = (unsigned char *)p_dram_partition->fdt_addr; + + //reset shminfo + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + bl_memset(p_bininfo, 0, sizeof(SHMINFO)); + return 0; +} + +_THUMB2 static int bl_load_fdt_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return -1; + } + + np_get_input.id = 1; // fdt must always put in partition[1] + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg_var("fdt addr", (int)emb_fdt.p_data); + debug_msg_var("fdt size", (int)emb_fdt.len); + if (bl_chk_fdt((unsigned int)emb_fdt.p_data, emb_fdt.len) == 0) { + return bl_copy_fdt_to_fdt_addr(emb_fdt.p_data, pp_fdt); + } + } + return -1; +} + +_THUMB2 static unsigned int bl_load_rtos_from_all_in_one(unsigned char *p_all_in_one, unsigned int all_in_one_size, unsigned char **pp_fdt /*OUT*/) +{ + UINT32 uItron_fw_addr= 0; + NVTPACK_ER er; + NVTPACK_MEM emb_fdt; + NVTPACK_VERIFY_OUTPUT np_verify = {0}; + NVTPACK_GET_PARTITION_INPUT np_get_input; + NVTPACK_MEM mem_in = {(void *)p_all_in_one, (unsigned int)all_in_one_size}; + HEADINFO *p_headinfo; + + if (nvtpack_verify(&mem_in, &np_verify) != NVTPACK_ER_SUCCESS) { + debug_err("packbin verify failed.\r\n"); + return 0; + } + + np_get_input.id = 5; // rtos must always put in partition[5] for now + np_get_input.mem = mem_in; + er = nvtpack_get_partition(&np_get_input, &emb_fdt);//&np_get_input, &emb_fdt); + + if (er == NVTPACK_ER_NOT_FOUND) { + return 0; + } else if (er == NVTPACK_ER_SUCCESS) { + debug_msg("get rtos partition ok\r\n"); + + p_headinfo = (HEADINFO *)(emb_fdt.p_data + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + + utl_memcpy((void *)uItron_fw_addr, emb_fdt.p_data, emb_fdt.len); + CPUflushWriteCache(uItron_fw_addr, emb_fdt.len); + } + debug_msg_var("uItron_fw_addr=", uItron_fw_addr); + return uItron_fw_addr; +} + +_THUMB2 static int bl_load_fdt_from_flash(unsigned char *p_tmp, unsigned int tmp_size, unsigned char **pp_fdt /*OUT*/) +{ + + // read first block to get dtb size + int blk_size = (int)int_strg_obj->flash_getBlockSize(); + int er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, blk_size, p_tmp, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + + int total_size = ALIGN_CEIL(fdt_totalsize(p_tmp), blk_size); + if ((int)tmp_size < total_size) { + debug_err_var("tmp_size too small, require:", fdt_totalsize(p_tmp)); + return -1; + } + + total_size -= blk_size; + if (total_size > 0) { + // read remain to get uboot starting addr on dram and offset in flash + er = int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW+1, total_size, p_tmp+blk_size, NAND_RW_FIRMWARE); + if (er < 0) { + debug_err("bl_load_fdt_from_flash"); + return -1; + } + } + + if (bl_chk_fdt((unsigned int)p_tmp, fdt_totalsize(p_tmp)) == 0) { + return bl_copy_fdt_to_fdt_addr(p_tmp, pp_fdt); + } + + return -1; +} + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition_fdt_offset(unsigned char *p_fdt) +{ + static int nodeoffset= -FDT_ERR_NOTFOUND; + + if (nodeoffset > 0) { + return nodeoffset; + } + + const static char *p_names[3] = { + "/nand", + "/nor", + "/mmc@f0510000" + }; + + const char *name = NULL; + switch(gStorageIntType) { + case STORAGEINT_SPI_NAND: + name = p_names[0]; + break; + case STORAGEINT_SPI_NOR: + name = p_names[1]; + break; + case STORAGEINT_EMMC: + name = p_names[2]; + break; + default: + debug_err("loader_setStorageIntType needs.\r\n"); + return NULL; + } + + nodeoffset = fdt_path_offset(p_fdt, name); + + if (nodeoffset < 0) { + debug_err("E:bl_get_partition_name\r\n"); + } + return nodeoffset; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static const void *bl_get_fdt_partition_property(const void *p_dtb, const char *p_path, const char *p_property, int *len) +{ + int nodeoffset_partition = bl_get_partition_fdt_offset((unsigned char *)p_dtb); + + int nodeoffset; + const void *nodep; /* property node pointer */ + + if (nodeoffset_partition < 0) { + debug_err("nodeoffset_partition invalid \r\n"); + return NULL; + } + + nodeoffset = fdt_subnode_offset(p_dtb, nodeoffset_partition, p_path); + if (nodeoffset < 0) { + return NULL; + } + nodep = fdt_getprop(p_dtb, nodeoffset, p_property, len); + if (len == 0) { + return NULL; + } + return nodep; +} +#endif + +#if (FDT_SUPPORT) +_THUMB2 static int bl_get_partition(unsigned char *p_fdt /*IN*/, char *p_emb_name /*IN*/, EMB_PARTITION *p_emb/*OUT*/, int *p_id) +{ + int len; + const unsigned long long *nodep; + + // get partition offset and size + nodep = (const unsigned long long *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_REG, &len); + if (nodep == NULL) { + debug_err("bl_get_partition-1\r\n"); + return -1; + } + + p_emb->PartitionOffset = be64_to_cpu(nodep[0]); + p_emb->PartitionSize = be64_to_cpu(nodep[1]); + + // get partition label + char *p_label_name = (char *)bl_get_fdt_partition_property(p_fdt, p_emb_name, PROPERTY_LABEL, &len); + if (p_label_name == NULL) { + debug_err("bl_get_partition-2\r\n"); + return -1; + } + + // get id + int nodeoffset_partition = bl_get_partition_fdt_offset(p_fdt); + int nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset_partition, "nvtpack"); + nodeoffset = fdt_subnode_offset(p_fdt, nodeoffset, "index"); + + for (nodeoffset = fdt_first_subnode(p_fdt, nodeoffset); + (nodeoffset >= 0); + (nodeoffset = fdt_next_subnode(p_fdt, nodeoffset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property(p_fdt, nodeoffset, PROPERTY_PARTITION_NAME, &len))) { + break; + } + const char *p_id_name = fdt_get_name(p_fdt, nodeoffset, &len); + + if (strcmp(p_label_name, (char *)prop->data) == 0) { + *p_id = atoi(p_id_name + strlen("id")); + return 0; + } + } + + return -1; +} +#endif + +_THUMB2 static void *bl_get_uboot_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_UBOOT, &g_emb_uboot, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_UBOOT; +#endif + g_emb_uboot.EmbType = EMBTYPE_UBOOT; + return &g_emb_uboot; +} + +_THUMB2 static void *bl_get_rtos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_RTOS, &g_emb_rtos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_RTOS; +#endif + g_emb_rtos.EmbType = EMBTYPE_RTOS; + return &g_emb_rtos; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static void *bl_get_nuttx_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ + if (bl_get_partition(p_fdt, PATH_PARTITION_NUTTX, &g_emb_nuttx, p_id) != 0) { + return NULL; + } + g_emb_nuttx.EmbType = EMBTYPE_NUTTX; + + return &g_emb_nuttx; +} +#endif + +_THUMB2 static void *bl_get_teeos_partition(unsigned char *p_fdt /*IN*/, int *p_id /*OUT*/) +{ +#if (FDT_SUPPORT) + if (bl_get_partition(p_fdt, PATH_PARTITION_TEEOS, &g_emb_teeos, p_id) != 0) { + return NULL; + } +#else + *p_id = NVTPACK_IDX_TEEOS; +#endif + g_emb_teeos.EmbType = EMBTYPE_TEEOS; + + return &g_emb_teeos; +} +#endif + +// return decompress_fw_size +_THUMB2 static unsigned int bl_decompress_rtos(UINT32 compress_addr, UINT32 compress_size, UINT32 fw_base_addr) +{ + UINT32 decoded_size; + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)compress_addr; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + + size_comp_le = (compress_size < size_comp_le) ? compress_size : size_comp_le; + decoded_size = LZ_Un_compress((UINT8 *)compress_addr + sizeof(NVTPACK_BFC_HDR), (UINT8 *)fw_base_addr, size_comp_le); + //because some padding bytes are decoded, we must return real rtos size + return (decoded_size < size_uncomp_le) ? decoded_size : size_uncomp_le; +} + +#if !REMOVED_FLASH +_THUMB2 static int bl_load_uboot_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_uboot; + int uboot_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)uboot_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_uboot); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); +// debug_msg_var("uboot_size", p_dram_partition->uboot_size); +# if 0 + if(0) { +#else +#if (_FPGA_EMULATION_ == 0) + if(is_secure_enable() == 0) { +#else + if (1) { +#endif +#endif + if (bl_chk_uboot((unsigned int)mem_uboot.p_data, mem_uboot.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_uboot.p_data + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_uboot.p_data; // describe compressed u-boot + + // load uboot bin to dram partiton location + //debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + //debug_msg_var("uboot_size", p_dram_partition->uboot_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); + +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_uboot.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->uboot_addr, size_comp_le); + debug_msg("lz"); + } + } else { + debug_msg("nml"); + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, p_headinfo->BinLength); + } + } else { +#if (SECURE_DECRYPT_UBOOT) + utl_memcpy((void *)p_dram_partition->uboot_addr, mem_uboot.p_data, mem_uboot.len); + unsigned int plaintext_size =0; + + if((er = do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0 ) + { + //debug_err("aes fail\r\n"); + return er; + } + if (bl_chk_uboot((unsigned int)p_dram_partition->uboot_addr, plaintext_size) != 0) { + return -1; + } +#else + debug_msg("please enable SECURE_DECRYPT_UBOOT\r\n"); + return -1; +#endif + } + + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_load_nuttx_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_nuttx; + int nuttx_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_nuttx = bl_get_nuttx_partition(p_fdt, &nuttx_partition_id); + + if (p_emb_partition_nuttx == NULL) { + debug_err("null p_emb_partition_nuttx\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)nuttx_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_nuttx); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)mem_nuttx.p_data, mem_nuttx.len) != 0) { + return -1; + } + + // flow to handle compressed u-boot and uncompressed one. + HEADINFO *p_headinfo = (HEADINFO *)(mem_nuttx.p_data + BIN_INFO_OFFSET_NUTTX); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)mem_nuttx.p_data; // describe compressed u-boot + + // load nuttx bin to dram partiton location + debug_msg_var("nuttx_addr", p_dram_partition->nuttx_addr); + debug_msg_var("nuttx_size", p_dram_partition->nuttx_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + LZ_Un_compress(mem_nuttx.p_data + sizeof(NVTPACK_BFC_HDR), (unsigned char *) p_dram_partition->nuttx_addr, size_comp_le); + } else { + utl_memcpy((void *)p_dram_partition->nuttx_addr, mem_nuttx.p_data, p_headinfo->BinLength); + } + + return 0; +} +#endif + +_THUMB2 static int bl_load_teeos_from_all_in_one(unsigned char *p_fdt, unsigned char *p_all_in_one, unsigned int all_in_one_size) +{ + NVTPACK_ER er; + NVTPACK_MEM mem_teeos; + int teeos_partition_id; + NVTPACK_GET_PARTITION_INPUT input; + DRAM_PARTITION *p_dram_partition = NULL; + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + HEADINFO *p_headinfo = NULL; + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // get partition data address and size + input.id = (unsigned int)teeos_partition_id; + input.mem.p_data = (void *)p_all_in_one; + input.mem.len = all_in_one_size; + er = nvtpack_get_partition(&input, &mem_teeos); + if (er == NVTPACK_ER_NOT_FOUND) { + return -2; + } + + if (er != NVTPACK_ER_SUCCESS) { + return -1; + } + +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + unsigned int plaintext_size =0; + utl_memcpy((void *)p_dram_partition->teeos_addr, mem_teeos.p_data, mem_teeos.len); + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr,&plaintext_size, p_dram_partition->teeos_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + //this is the second headinfo information , not encrpyted headinfo + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); +#else + debug_err("please enable SECURE_DECRYPT_OPTEE_OS"); + return -1; +#endif + } + else{ + p_headinfo = (HEADINFO *)(mem_teeos.p_data + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + utl_memcpy((void *)p_dram_partition->teeos_addr, (unsigned char*)mem_teeos.p_data, p_headinfo->BinLength); + } + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + + //check addr matched or not + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + + // using check uboot's check sum is ok + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + return 0; +} + +_THUMB2 static int bl_load_uboot_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int uboot_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_uboot = bl_get_uboot_partition(p_fdt, &uboot_partition_id); + + if (p_emb_partition_uboot == NULL) { + debug_err("null p_emb_partition_uboot\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + +#if (SECURE_DECRYPT_UBOOT) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } +#else + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(BIN_INFO_OFFSET_UBOOT + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read uboot failed + return -1; + } + +#endif + + debug_msg_var("uboot_addr", p_dram_partition->uboot_addr); + debug_msg_var("uboot_size", p_dram_partition->uboot_size); +#if 0 + if(0){ +#else + if(is_secure_enable() == 0) { +#endif + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_UBOOT); // describe uncompressed u-boot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) + { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(size_comp_le, blk_size),p_tmp, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash_comp,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) { +#if (_ROM_PUBLIC_API_ == 1) + UINT32 lzma_addr = *(UINT32 *)ROM_LZMA_POSITION; + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + UINT32 size_uncomp_le = invertEndian(pBfc->uiSizeUnComp); + rom_lzma_inflate = (int (*)(UINT8 *, UINT32 , UINT8 * , UINT32 , UINT8 *, UINT32 ))((lzma_addr)); + rom_lzma_inflate(p_tmp + sizeof(NVTPACK_BFC_HDR), size_comp_le, (unsigned char *) p_dram_partition->uboot_addr, size_uncomp_le, (UINT8 *)lzma_temp_buffer, 65536); + debug_msg("lzma "); +#else + debug_msg("Can not support LZMA\r\n"); +#endif + } else { + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->uboot_addr, size_comp_le); + } + } + else + { + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + } + else + { +#if (SECURE_DECRYPT_UBOOT) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_uboot->PartitionOffset / blk_size, + ALIGN_CEIL(p_headinfo->BinLength, blk_size), + (UINT8 *)p_dram_partition->uboot_addr, NAND_RW_FIRMWARE)) < 0) + { + debug_err_var("bl_load_uboot_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + unsigned int plaintext_size=0; + if((er =do_decrypt_aes(p_dram_partition->uboot_addr, p_dram_partition->uboot_addr, &plaintext_size, p_dram_partition->uboot_size))!= 0) + { + //debug_err("aes fail\r\n"); + return er; + } +#else + debug_msg("plase enable SECURE_DECRYPT_UBOOT config\r\n"); + return -1; +#endif + } + return 0; +} + +_THUMB2 static int bl_load_rtos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int rtos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_rtos = bl_get_rtos_partition(p_fdt, &rtos_partition_id); + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + if (p_emb_partition_rtos == NULL) { + debug_err("null p_emb_partition_rtos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if(bl_is_smp(p_fdt)) { + bl_core2_prepare(p_dram_partition, 0); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } +#endif + + // load 1st block of rtos to tmp dram (to detect compressed u-boot) + unsigned int bininfo_preload_size = ALIGN_CEIL(BIN_INFO_OFFSET_RTOS + sizeof(HEADINFO), blk_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, bininfo_preload_size, p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read rtos failed + } + + // flow to handle compressed u-boot and uncompressed one. + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)p_tmp; // describe compressed u-boot + + // load rtos bin to dram partiton location + //debug_msg_var("rtos_addr", p_dram_partition->rtos_addr); + //debug_msg_var("rtos_size", p_dram_partition->rtos_size); + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + + if((cpu_to_be32(pBfc->uiAlgorithm) & 0xFF ) == 11) + { + /* lzma compressed image*/ + debug_msg("lzma, use uboot\r\n"); + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + UINT32 size_comp_le = invertEndian(pBfc->uiSizeComp); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, ALIGN_CEIL(size_comp_le, blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_comp,er=", er); // read bfc-rtos failed + bl_displayErrMsg(RWErrorMsg); + } + LZ_Un_compress(p_tmp + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_dram_partition->rtos_addr, size_comp_le); + } + } else { + BININFO *p_bininfo = (BININFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); // describe uncompressed u-boot + if (p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN) { + // copy bininfo_preload to rtos_addr + bl_memcpy((UINT8 *)p_dram_partition->rtos_addr, p_tmp, bininfo_preload_size); + // preload some to get part-1 size for partial load and partial compressed load + UINT32 preload_size = ALIGN_CEIL(FW_PART1_SIZE_OFFSET, blk_size) - bininfo_preload_size; + + if (preload_size!= 0) { + er = int_strg_obj->flash_readSectors( + (p_emb_partition_rtos->PartitionOffset + bininfo_preload_size) / blk_size, + preload_size, + (UINT8 *)(p_dram_partition->rtos_addr + bininfo_preload_size), NAND_RW_FIRMWARE + ); + + if (er < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + } + UINT32 part1_size = *(UINT32 *)(p_dram_partition->rtos_addr + FW_PART1_SIZE_OFFSET); + debug_msg_var("part1_size",part1_size); + part1_size = ALIGN_CEIL(part1_size, blk_size); + //debug_msg_var("part1_size_aligned",part1_size); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset / blk_size, part1_size, (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash_pl1,er=", er); + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = part1_size; + } else { + // full load + debug_msg_var("rtos_size", p_bininfo->head.BinLength); + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_rtos->PartitionOffset /blk_size, ALIGN_CEIL(p_bininfo->head.BinLength, blk_size), (UINT8 *)p_dram_partition->rtos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_rtos_from_flash,er=", er); // read bfc-uboot failed + bl_displayErrMsg(RWErrorMsg); + } + // update loaded size + p_shminfo->boot.LdLoadSize = p_bininfo->head.BinLength; + } + } + return 0; +} + +_THUMB2 static int bl_load_teeos_from_flash(unsigned char *p_fdt, unsigned char *p_tmp) +{ + int er; + int teeos_partition_id; + DRAM_PARTITION *p_dram_partition = NULL; + unsigned int blk_size = int_strg_obj->flash_getBlockSize(); + EMB_PARTITION *p_emb_partition_teeos = bl_get_teeos_partition(p_fdt, &teeos_partition_id); + + if (p_emb_partition_teeos == NULL) { + debug_err("null p_emb_partition_teeos\r\n"); + return -1; + } + + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // load 1st block of u-boot to tmp dram (to detect compressed u-boot) + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(BIN_INFO_OFFSET_TEEOS + sizeof(HEADINFO), blk_size), p_tmp, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); + bl_displayErrMsg(RWErrorMsg); // read teeos failed + } + + // flow to handle compressed u-boot and uncompressed one. +#if (SECURE_DECRYPT_OPTEE_OS) + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp); // describe uncompressed u-boot +#else + HEADINFO *p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot + +#endif + + if ((er = int_strg_obj->flash_readSectors(p_emb_partition_teeos->PartitionOffset / blk_size, ALIGN_CEIL(p_headinfo->BinLength, blk_size), (UINT8 *)p_dram_partition->teeos_addr, NAND_RW_FIRMWARE)) < 0) { + debug_err_var("bl_load_teeos_from_flash,er=", er); // read bfc-teeos failed + bl_displayErrMsg(RWErrorMsg); + } +#if 0 + if(1){ +#else + if(is_secure_enable()) { +#endif +#if (SECURE_DECRYPT_OPTEE_OS) + + unsigned int plaintext_size=0; + if((er = do_decrypt_aes(p_dram_partition->teeos_addr, p_dram_partition->teeos_addr, &plaintext_size, p_dram_partition->teeos_size)) != 0) + { + //debug_err("aes fail\r\n"); + return er; + } + + p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); // describe uncompressed u-boot +#else + debug_err("please ENABLE SECURE_DECRYPT_OPTEE_OS config\n"); + return -1; +#endif + } + + // load teeos bin to dram partiton location + UINT32 teeos_addr = p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_LOAD_ADDR]; + debug_msg_var("teeos_addr", p_dram_partition->teeos_addr); + if (teeos_addr != p_dram_partition->teeos_addr) { + debug_msg_var("teeos_addr(bin)", teeos_addr); + debug_err("teeos addr not matched.\r\n"); + return -1; + } + //check check sum + if (bl_chk_uboot((unsigned int)teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } + return 0; +} +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) +_THUMB2 static int bl_load_rtos_from_non_nvtpack(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(src_addr + SIZE_PRELOAD + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = fat_read_rootfile((UINT8 *)src_addr, compress_size); + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + + src_size = fat_read_rootfile((UINT8 *)src_addr, uncompress_size); + src_addr = uncompress_addr; + src_size = uncompress_size; + debug_msg("uncompressed t.bin\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw\r\n"); + src_size = fat_read_rootfile((UINT8 *)src_addr, FAT_READ_TOTAL_FILE_LENGTH); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +#if 0//(STORAGE_EXT_TYPE == STORAGE_EXT_USB) +_THUMB2 static int bl_load_rtos_from_usb_raw(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + HEADINFO *p_headinfo = (HEADINFO *)(src_addr + BIN_INFO_OFFSET_RTOS); + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + // to avoid rtos_addr is overlapped by src_addr, we need extract some bits to get real rtos addr. + // compressed firmware + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + // assume usb write loader receive full fw at 0x0200_0000, decompress it to smaller address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr - SIZE_PRESERVE_USB); + p_headinfo = (HEADINFO *)(src_addr - SIZE_PRESERVE_USB + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + utl_memcpy((void *)(uncompress_addr + uncompress_size), (void *)src_addr, compress_size); + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = compress_size; + } else { + return -1; + } + } else if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + // uncompressed firmware + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + debug_msg("uncompressed t.bin\r\n"); + utl_memcpy((void *)uncompress_addr, (void *)src_addr, uncompress_size); + src_size = uncompress_size; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + } else if (utl_is_sram_fw(src_addr) == TRUE) { + debug_msg("detected as SRAM fw. NOt Support from USB\r\n"); +#endif + } else { + return -1; + } + + *p_dst_addr = src_addr; + *p_dst_size = src_size; + return 0; +} +#endif + +//#if !USB_WRITELOADER +#if !((STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART)) +_THUMB2 static int bl_load_rtos_from_uart(unsigned int src_addr, unsigned int src_size, unsigned int *p_dst_addr, unsigned int *p_dst_size) +{ +#if UART_UPDATE_ + UINT32 tick_kms = 10; // timeout 1000 ms + char key; + + debug_msg("UART press Enter to\r\n"); + + while (--tick_kms) { + uart_chkChar(&key); + + if (key != 0x00) { + break; + } + timer_delay(100000); //100000 + debug_msg("."); + } + + if (tick_kms) { + UINT32 uiLength; + debug_msg("\r\nEnter uboot length (Decimal):\r\n"); //must \r\n at the end because of auto_test tool + uart_getStr_polling(g_strLength); + uiLength = DecStr2Int(g_strLength); + debug_msg("\r\nPlz pass uboot bin > "); + uart_getBinary((char *)src_addr, uiLength); // Temp Receive to DRAM start + debug_msg("\r\nGot it\r\n"); +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + if (bl_checkDramScanFW(src_addr) == TRUE) { + UINT32 i; + + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + uiLength = ((uiLength + 3) & 0xFFFFFFFC); + + for (i = 0; i < uiLength; i += 4) { + *(UINT32 *)(src_addr + i) = *(UINT32 *)(src_addr + i); + } + *(UINT32 *)(src_addr) = *(UINT32 *)(src_addr); + return 1; + } +#endif + if (*(UINT32 *)src_addr == MAKEFOURCC('B', 'C', 'L', '1')) { + HEADINFO *p_headinfo = NULL; + NVTPACK_BFC_HDR *pBFC = (NVTPACK_BFC_HDR *)src_addr; + bl_checkFW(src_addr, uiLength); + debug_msg_var("uiLength", uiLength); + debug_msg("compressed t.bin\r\n"); + // decode some bytes to get uncompressed address + bl_decompress_rtos(src_addr, SIZE_PRELOAD, src_addr + uiLength); + p_headinfo = (HEADINFO *)(src_addr + uiLength + BIN_INFO_OFFSET_RTOS); + // check if valid after decode + if ((strncmp(p_headinfo->BinInfo_1, "NT", 2) == 0) || + (strncmp(p_headinfo->BinInfo_1, "NC", 2) == 0)) { + UINT32 uncompress_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; + UINT32 uncompress_size = p_headinfo->BinLength; + UINT32 compress_size = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + unsigned int ori_src_addr = src_addr; + //adjust src_addr that lay compressed f.w followed by uncomppressed f.w + src_addr = uncompress_addr + uncompress_size; + src_addr = ALIGN_CEIL(src_addr, 4); + src_size = uncompress_size; + utl_memcpy((void *)src_addr, (void *)ori_src_addr, uiLength); + *p_dst_addr = src_addr; + *p_dst_size = compress_size; + return 0; + } else { + return -1; + } + return 0; + } + } +#endif + return -1; +} +#endif + +_THUMB2 static void bl_update_uItron_headInfo(UINT32 fw_base_addr, DRAM_PARTITION *p_dram_partition) +{ + HEADINFO *pHeadInfo; +#if (UITRON_FW == ENABLE) + BININFO *pBinInfo; +#endif + pHeadInfo = (HEADINFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + if (p_dram_partition) { + pHeadInfo->ModelextAddr = p_dram_partition->fdt_addr; + } else { + pHeadInfo->ModelextAddr = 0; +#if (UITRON_FW == ENABLE) + pBinInfo = (BININFO *)(fw_base_addr + BIN_INFO_OFFSET_RTOS); + pBinInfo->ld.Resv[0] = LoaderInternalInfo[1]; + pBinInfo->ld.LdPackage = (LoaderInternalInfo[3] & 0xFFFF); +#endif + } +} + +_THUMB2 static int bl_update_loader_bininfo(unsigned char *p_fdt, unsigned int ld_flag, unsigned int rtos_loaded_size) +{ + BOOTINFO *p_ld; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + BININFO *p_bininfo = (BININFO *)(p_dram_partition->rtos_addr + BIN_INFO_OFFSET_RTOS); + + p_ld = &p_shminfo->boot; + if (!(p_bininfo->head.Resv1[HEADINFO_RESV_IDX_BOOT_FLAG] & BOOT_FLAG_PARTLOAD_EN)) { + // LdLoadSize updated on uboot or bl_load_rtos_from_flash(), if BOOT_FLAG_PARTLOAD_EN + p_ld->LdLoadSize = rtos_loaded_size; + } + p_ld->LdLoadTime = timer_getLdrElapse(); + p_ld->LdResvSize = 0; //unused + p_ld->FWResvSize = 0; //unused + return 0; +} + +_THUMB2 static int bl_is_smp(unsigned char *p_fdt) +{ +#if (FDT_SUPPORT) + int len; + const char *nodep; + nodep = (const char *)bl_get_fdt_property(p_fdt, PATH_NVT_INFO, PROPERTY_NVT_LINUX_SMP, &len); + debug_msg_var("nodep", (UINT32)nodep); + if (nodep == NULL) { + return 0; + } + debug_msg((char *)nodep); + if (strcmp(nodep, "NVT_LINUX_SMP_ON") == 0) { + return 1; + } + return 0; +#else + return 0; +#endif +} + +#if !REMOVED_FLASH +_THUMB2 int bl_boot_uboot(unsigned char *p_fdt) +{ +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + UINT32 No_CPU; +#endif + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update shminfo + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_shminfo->boot.LdPackage = p_param[3] & 0xFFFF; + p_shminfo->boot.LdStorage = (p_param[3] >> 16) & 0xFF; + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->uboot_addr + BIN_INFO_OFFSET_UBOOT); + + if (bl_chk_uboot(p_dram_partition->uboot_addr, p_headinfo->BinLength) != 0) { + return -1; + } + // start cpu2 + if (p_dram_partition->uboot_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-uboot_addr ", (int)p_dram_partition->uboot_addr); + debug_err_var("bin-uboot_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + // for uboot to indicate this boot is all-in-one fw or non-all-in-one boot from uart or usb + // if boot from uart or usb with non-all-in-one fw, the uboot's ModelextAddr will be zero + p_headinfo->ModelextAddr = p_dram_partition->fdt_addr; + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + UINT32 isSMP = bl_is_smp(p_fdt); + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + No_CPU = *(UINT32 *)0xFFD00004; + No_CPU &= 0x3; + debug_msg_var("core No.=", No_CPU+1); +#endif + // init cpu timer +// bl_cpu_timer_init(CPU_TIMER_SETTING); +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + if (!isSMP || !No_CPU) +#else + if (!isSMP) +#endif + { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + debug_msg_var("Bin core=", isSMP+1); +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + } else { +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + // init cpu timer + bl_cpu_timer_init(global_timer_freq); + + bl_smp_start(p_fdt, p_headinfo->CodeEntry); + // boot u-boot and never return back to loader +#else + //bl_smp_start(p_fdt, p_headinfo->CodeEntry); + debug_err("not support smp\r\n"); +#endif + } + return 0; +} + +#if (NUTTX_SUPPORT) +_THUMB2 static int bl_boot_nuttx(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->nuttx_addr + BIN_INFO_OFFSET_NUTTX); + + if (bl_chk_uboot(p_dram_partition->nuttx_addr, p_headinfo->BinLength) != 0) { + return -1; + } + + // start cpu2 + if (p_dram_partition->nuttx_addr != p_headinfo->CodeEntry) { + debug_err_var("drampat-nuttx_addr ", (int)p_dram_partition->nuttx_addr); + debug_err_var("bin-nuttx_addr ", (int)p_headinfo->CodeEntry); + return -1; + } + + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + bl_cpu_timer_init(CPU_TIMER_SETTING); + + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot nuttx and never return back to loader + return 0; +} +#endif + +_THUMB2 static int bl_boot_teeos(unsigned char *p_fdt) +{ + DRAM_PARTITION *p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition == NULL) { + debug_err("null p_dram_partition\r\n"); + return -1; + } + + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(p_dram_partition->teeos_addr + BIN_INFO_OFFSET_TEEOS); + + // update uboot addr for teeos + p_headinfo->Resv1[HEADINFO_TEEOS_RESV_IDX_UBOOT_ADDR] = p_dram_partition->uboot_addr; + + +#if 0 //do not checksum, because teeos header has removed cause checksum failed + if (bl_chk_uboot(p_dram_partition->teeos_addr, p_headinfo->BinLength) != 0) { + return -1; + } +#endif + + //flush uboot + CPUflushWriteCache(p_dram_partition->uboot_addr, p_dram_partition->uboot_size); + //flush teeos + CPUflushWriteCache(p_headinfo->CodeEntry, p_headinfo->BinLength); + + // init cpu timer + +#if 0//(LOADER_TYPE == STAND_ALONE_LOADER_528) || (LOADER_TYPE == COMBINATION_528) + bl_cpu_timer_init(CPU_TIMER_SETTING); + // boot core2 (after teeos is loaded) + if (HEADINFO_UBOOT(p_dram_partition)->BinCtrl & 0x00000002) { + //if SMP, trigger core2 + debug_msg("smp(tee)\r\n"); + bl_core2_prepare(p_dram_partition, p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + bl_core2_reset(); + } else { + debug_msg_var("not smp\r\n", p_headinfo->BinCtrl); + } +#endif + bl_entry_boot(p_fdt, p_headinfo->CodeEntry); + // boot teeos and never return back to loader + return 0; +} + +_THUMB2 static int bl_update_loader_flag(unsigned char *p_fdt, UINT32 uiLoaderFunc) +{ + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + + utl_memcpy(p_bininfo->boot.LdInfo_1, "LD_NVT", 6); + + p_bininfo->boot.LdCtrl2 = 0; + if (uiLoaderFunc & FUNC_UPDATE_FW) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_FW; + } + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + p_bininfo->boot.LdCtrl2 |= LDCF_UPDATE_LD; + } + if (uiLoaderFunc & FUNC_RUN_CARD) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_CARD; + } + if (uiLoaderFunc & FUNC_RUN_FLASH) { + p_bininfo->boot.LdCtrl2 |= LDCF_BOOT_FLASH; + } + //CPUflushWriteCache((UINT32)p_bininfo, sizeof(BININFO)); + debug_msg_var("LdCtrl2", p_bininfo->boot.LdCtrl2); + + unsigned int ver; + SHMINFO *p_shminfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_fdt, MODELEXT_TYPE_BIN_INFO); + BOOTINFO *p_ld = &p_shminfo->boot; + + utl_memset(p_ld->LdInfo_1, 0, sizeof(p_ld->LdInfo_1)); + utl_memcpy(p_ld->LdInfo_1, "LD_NVT", 6); + + ver = (((LoaderInternalInfo[1] >> 28) & 0xF) << 24) | + (((LoaderInternalInfo[1] >> 24) & 0xF) << 16) | + ((LoaderInternalInfo[1] >> 16) & 0xFF); + + if (g_uiVersion == 0) { + g_uiVersion = ver; + } + + utl_memcpy(&p_ld->LdInfo_1[8], &g_uiVersion, sizeof(g_uiVersion)); + unsigned int *p_param = (unsigned int *)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[0]); + p_ld->LdPackage = p_param[3] & 0xFFFF; + p_ld->LdStorage = (p_param[3] >> 16) & 0xFF; + + return 0; +} + +// return uItron_fw_addr +_THUMB2 unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + + // load fdt + er = bl_load_fdt_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + if (er == -2) { // try to load from nand + debug_msg("fdt from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + + //p_tmp for the case of all-in-one without fdt or uboot + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + er = bl_load_fdt_from_flash(p_tmp, 0x2000000, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + if (uiLoaderFunc & FUNC_UPDATE_FW) { + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + p_bininfo->comm.Resv[5] = uiFwBuf; // COMM_FW_UPD_ADDR + p_bininfo->comm.Resv[6] = uiFwBufSize; // COMM_FW_UPD_LEN + debug_msg_var("upd_src_addr=", uiFwBuf); + debug_msg_var("upd_src_size=", uiFwBufSize); + } + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + //check loader addr is matched with loader self. + extern char _loader_exec_compres_start[]; + if (p_dram_partition->loader_addr != (UINT32)_loader_exec_compres_start) { + debug_msg_var("p_dram_partition->loader_addr", p_dram_partition->loader_addr); + debug_msg_var("_loader_exec_compres_start", (UINT32)_loader_exec_compres_start); + bl_displayErrMsg("loader addr is not match."); + } + //when rtos boot from flash, the boot from loader directly, + //but when rtos need to burn image, the uboot is still required. + //so, any one need to burn image, uboot is always needed to boot. + //if ((uiLoaderFunc & FUNC_UPDATE_FW) || p_dram_partition->rtos_addr == 0) { + if (1) { + // always use uboot to handle all-in-one bin + if (p_dram_partition->nuttx_size == 0 && p_dram_partition->teeos_size == 0) { + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er == -2) { // try to load from nand + debug_msg("uboot from flash.\r\n"); + // open flash + if (bl_flash_open() != 0) { // dont move flash open outside section, consider that T without flash device. + bl_displayErrMsg("flash open failed\r\n"); + } + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + } + + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else if (p_dram_partition->nuttx_size) { +#if (NUTTX_SUPPORT) + // load nuttx + er = bl_load_nuttx_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load nuttx failed\r\n"); + } + er = bl_boot_nuttx((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot nuttx failed\r\n"); + } +#else + bl_displayErrMsg("NUTTX_SUPPORT disabled\r\n"); +#endif + } else if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_all_in_one((unsigned char *)p_dram_partition->fdt_addr, (unsigned char *)uiFwBuf, uiFwBufSize); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } + return er; + } else { + // update rtos information + // the following is for uncompressed-rtos only, others needing uboot + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((const void *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return bl_load_rtos_from_all_in_one((unsigned char *)uiFwBuf, uiFwBufSize, &p_fdt); + } +} +#endif + +// return uItron_fw_addr, no need to fully decode +_THUMB2 static unsigned int bl_process_rtos_only(UINT32 uiFwBuf, UINT32 uiFwBufSize, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + UINT32 uItron_fw_addr; + NVTPACK_BFC_HDR *pBFC; + HEADINFO *p_headinfo; + + debug_msg("\r\nbl_process_rtos_only\r\n"); + pBFC = (NVTPACK_BFC_HDR *)uiFwBuf; + if (pBFC->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 compressSize; + unsigned char *p_tmp = (unsigned char *)(uiFwBuf + ALIGN_CEIL(uiFwBufSize, 4)); + LZ_Un_compress((UINT8 *)uiFwBuf + LDC_HEADER_SIZE, p_tmp, SIZE_PRELOAD); + p_headinfo = (HEADINFO *)(p_tmp + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + compressSize = invertEndian(pBFC->uiSizeComp) + sizeof(NVTPACK_BFC_HDR); + //debug_dump_addr(tmpBuf,0x200); + debug_msg_var("F compress uItron_fw_addr", uItron_fw_addr); + // uiFwBuf has adjusted on bl_load_rtos_from_non_nvtpack() + *p_comp_addr = uiFwBuf; + *p_comp_size = compressSize; + } else { + p_headinfo = (HEADINFO *)(uiFwBuf + BIN_INFO_OFFSET_RTOS); + uItron_fw_addr = p_headinfo->CodeEntry - CODE_SECTION_OFFSET; +#if UITRON_FW + uItron_fw_addr = p_headinfo->CodeEntry - CODE_ENTRY_OFFSET; // cliff +#endif + + if ((uItron_fw_addr & 0x0000FFFF) != 0) { //cc engine's limitation + debug_err_var("rtos addr must match (&0x0000FFFF)==0", uItron_fw_addr); // but 660 allow + uItron_fw_addr = uItron_fw_addr & 0xFFFF0000; + } + + debug_msg_var("Normal uItron_fw_addr", uItron_fw_addr); + *p_comp_addr = 0; + *p_comp_size = 0; + } + return uItron_fw_addr; +} +#if !UPDATE_EMU_CODE && !REMOVED_FLASH +_THUMB2 static unsigned int bl_process_flash_boot(unsigned char *p_tmp, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size) +{ + int er; + unsigned char *p_fdt = NULL; + DRAM_PARTITION *p_dram_partition = NULL; + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // load fdt + er = bl_load_fdt_from_flash(p_tmp, SDRAM_Start_FW, &p_fdt); // dtb size less than 32MB to be safer. + if (er != 0) { + bl_displayErrMsg("load fdt failed\r\n"); + } + + // update loader flag + bl_update_loader_flag(p_fdt, uiLoaderFunc); + + p_dram_partition = (DRAM_PARTITION *)bl_get_fdt_cfg(p_fdt, MODELEXT_TYPE_DRAM_PARTITION); + + if (p_dram_partition->teeos_size) { + // load teeos + er = bl_load_teeos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load teeos failed\r\n"); + } + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + // boot teeos + er = bl_boot_teeos((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot teeos failed\r\n"); + } + } else if (p_dram_partition->rtos_addr == 0 || DUAL_RTOS_SUPPORT || (gFastbootKeyCallBack == NULL) || (!gFastbootKeyCallBack())) { + // load uboot + er = bl_load_uboot_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load uboot failed\r\n"); + } + + // boot uboot + er = bl_boot_uboot((unsigned char *)p_dram_partition->fdt_addr); + if (er != 0) { + bl_displayErrMsg("boot uboot failed\r\n"); + } + } else { + // load rtos + er = bl_load_rtos_from_flash((unsigned char *)p_dram_partition->fdt_addr, p_tmp); + if (er != 0) { + bl_displayErrMsg("load rtos failed\r\n"); + } + } + + // update compressed rtos information + SHMINFO *p_bininfo = (SHMINFO *)bl_get_fdt_cfg((unsigned char *)p_dram_partition->fdt_addr, MODELEXT_TYPE_BIN_INFO); + if (p_bininfo == NULL) { + debug_err("null p_bininfo\r\n"); + return -1; + } + *p_comp_addr = p_bininfo->comm.Resv[3]; // COMM_UITRON_COMP_ADDR + *p_comp_size = p_bininfo->comm.Resv[4]; // COMM_UITRON_COMP_LEN + + *pOut_dram_partition = p_dram_partition; + return p_dram_partition->rtos_addr; +} +#endif + +/** + bl_process_update_loader. + + Write loader will update loader binary file + + @param[in] loader_addr loader in DRAM starting address + @param[in] loader_size loader code length (from loader header offset 0x24) + @return void +*/ +_THUMB2 static int bl_process_update_loader(unsigned int loader_addr, unsigned int loader_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card + if(is_data_area_encrypted() == 0) { + +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + //UINT32 uiOffset; + //uiOffset = *((UINT32 *)(loader_addr + 0x80)); + //if(uiOffset) {//Combo loader + // if(*(UINT32*)0xF00100F0 == 0x50210000) { + // debug_msg("combo loader 528\r\n"); + // bl_checkLoader(loader_addr+uiOffset, COMBINATION_LOADER_SIZE - uiOffset); //check 528 + // } else{ + // debug_msg("combo loader 52X\r\n"); + // bl_checkLoader(loader_addr, loader_size); //check 52x + // } + //}else + bl_checkLoader(loader_addr, loader_size); +#else +#if 0//(LOADER_TYPE == COMBINATION_528) + debug_msg("CB8\r\n"); + bl_checkLoader(loader_addr + loader_size, (COMBINATION_LOADER_SIZE - loader_size)); +#else //STAND_ALONE_LOADER or combination 52x loader + //debug_msg("STD\r\n"); + bl_checkLoader(loader_addr, loader_size); +#endif +#endif + } + debug_msg("update loader\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program loader +#if 0 +#if ((STORAGE_EXT_TYPE == STORAGE_EXT_ETH)|(STORAGE_EXT_TYPE == STORAGE_EXT_USB)) + UINT32 uiOffset; + uiOffset = *((UINT32 *)(loader_addr + 0x80)); + if(uiOffset) //Combo loader + loader_size = COMBINATION_LOADER_SIZE; + //If single loader , it already got +#else +#if (LOADER_TYPE == STAND_ALONE_LOADER_560) || (LOADER_TYPE == STAND_ALONE_LOADER_528) +#else //Combination loader + loader_size = COMBINATION_LOADER_SIZE; +#endif +#endif +#endif + if (int_strg_obj->flash_writeSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)loader_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = loader_addr + loader_size; + if (int_strg_obj->flash_readSectors(StartNandBlkUpdateLoader, loader_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)loader_addr, (void *)reload_addr, loader_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#if UPDATE_EMU_CODE +_THUMB2 static int bl_process_update_emu_firmware(unsigned int emu_addr, unsigned int emu_size) +{ + unsigned int reload_addr; + + // Check boot loader read from SD card +// bl_checkFW(emu_addr, emu_size); + debug_msg("update emu firmware size"); + uart_putSystemUARTStr(Dec2HexStr(emu_size)); + uart_putSystemUARTStr("\r\n"); + + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + + // Program firmware + if (int_strg_obj->flash_writeSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)emu_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + // Read back + reload_addr = emu_addr + emu_size; + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, emu_size, (UINT8 *)reload_addr, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg("rd fail\r\n"); + } + // Verify + if (memcmp((void *)emu_addr, (void *)reload_addr, emu_size) != 0) { + bl_displayErrMsg("verify fail\r\n"); + } + return 0; +} +#endif + +_THUMB2 void bl_read_rtos_addr(UINT32 *pLoadAddr, UINT32 *pTargetAddr, UINT32 *pSize) +{ + *pLoadAddr = g_rtos_load_addr; + *pTargetAddr = g_rtos_target_addr; + *pSize = g_rtos_size; +} + +/** + main flow code + + If there is Calibration Firmware code store in NAND, running flow as follow + O's work flow + + @return fw base addr +*/ + +_THUMB2 UINT32 bl_mainFlow(void) +{ + UINT32 uiUpdateFileLen = 0; + UINT32 uiLoaderFunc = 0; + UINT32 uiLoaderSize = 32 * 1024; // pre-assume 32KB, actual size is parsed from loader + //Show Duty calibration log +#if (_LOADER_DUTY_CALIBRATION_ == ENABLE && _LOADER_DUTY_CALIBRATION_LOG_ == ENABLE) + UINT32 uiLoaderAddress; + UINT32 uiLogSramAddress; +#endif + +#if !(USB_WRITELOADER || UART_UPDATE) + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; +#endif + UINT32 uiFwBaseAddr = SDRAM_Start_FW; // FW base address + DRAM_PARTITION *p_dram_partition = NULL; + + // BaseOfStack is initialized at doRemapLZ.s + UINT32 uiheapBufferAddr = (UINT32)_loader_heap_base; +// UINT32 uiheapBufferAddr = BaseOfStack + 0x40000; // reserve 16KB for tmp buffer usage + UINT32 uiTmpBufferAddr = uiheapBufferAddr + FAT_HEAP_BUFFER_SIZE; + UINT32 uiUpdateBootloaderBufAddr = uiTmpBufferAddr + 0x4000; + UINT32 uiUpdateMainBinBufAddr = SDRAM_Start_FW; + + // UART initial sequence + //uart_openSystemUART(); + // rtc reset shutdown timer + // rtc_resetShutDownTimer(); + + + + +#if 0 + // adjust PAD driving (if required) + bl_adjustDriving(); + /* + - @b RTC_PWR_SW_STS: Power on source is PWR_SW + - @b RTC_PWR_VBAT_STS: Power on source is PWR_VBAT + - @b RTC_PWR_VBUS_STS: Power on source is PWR_VBUS + */ + uiPowerOnSrc = rtc_getPWRONSource(); + + if (uiPowerOnSrc & RTC_PWR_SW_STS) { + uart_putSystemUARTStr("\r\nSW PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBAT_STS) { + uart_putSystemUARTStr("\r\nVBAT PON\r\n"); + } else if (uiPowerOnSrc & RTC_PWR_VBUS_STS) { + uart_putSystemUARTStr("\r\nVBUS PON\r\n"); + } else if (rtc_getIsAlarmPowerOn()) { + uart_putSystemUARTStr("\r\nPwrAlarm PON\r\n"); + } else { + uart_putSystemUARTStr("\r\nPOR PON\r\n"); + } +#endif + // Display Loader Version + debug_msg((char *)LOADER_START_STR); + UTL_setDrvTmpBufferAddress(uiTmpBufferAddr); + + +#if 0 // for now, reduce code size + if (rtc_chkS3boot()) { + UINT32 resume_addr; + + uart_putSystemUARTStr("main selfing..\r\n"); + resume_addr = bl_resume_cpu1((unsigned char *)_BOARD_IPC_ADDR_); + if (resume_addr == 0) { + // in codition for MODELEXT_BUILT_IN_ON + resume_addr = RESUME_ADDR; + } + return resume_addr; + } else { + + uart_putSystemUARTStr("main not selfing..\r\n"); + } +#endif + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + prj_main(); + +#if !(USB_WRITELOADER) + set_usb_suspend(); +#endif + + if(utl_get_bootsrc() == BOOT_SOURCE_UART) + { +#if UART_UPDATE + debug_msg("Boot from UART ...\r\n"); + bl_uart();//never returned. +#else + bl_displayErrMsg("UART_UPDATE must enable on loader\r\n"); +#endif + } + + if(USB_WRITELOADER || utl_get_bootsrc() == BOOT_SOURCE_USB) + { +#if USB_WRITELOADER + debug_msg("Boot from USB ...\r\n"); + bl_usb(); //never returned. +#else + bl_displayErrMsg("USB_WRITELOADER must enable on loader\r\n"); +#endif + } + +#if !(USB_WRITELOADER || UART_UPDATE) + if (bl_load_rtos_from_uart(uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH, &adjusted_addr, &adjusted_size) == 0) { + //specail case, load small rtos from uart + uiUpdateMainBinBufAddr = adjusted_addr; + uiUpdateFileLen = adjusted_size; + uiLoaderFunc |= FUNC_RUN_CARD; + } else if ((int_strg_obj->flash_getBlockSize() == EMMC_BLOCK_SIZE) && gRecoveryTriggerCallBack && gRecoveryTriggerCallBack()) { + debug_msg("Recovery triggered not support currently.\r\n"); +#if 0 + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } else { + flash_mount_fs(0, BaseOfStack + 0x4000, FAT_HEAP_BUFFER_SIZE); + if (flash_mount_partition(g_uiPartitionID) == E_OK) { + if (flash_open_file(RECOVERY_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = flash_read_file((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + g_is_recovery_triggered = TRUE; + } else { + debug_msg("Recovery should be all in one bin!\r\n"); + } + } else { + debug_msg("no recovery bin!\r\n"); + } + } else { + debug_msg("Partition error!\r\n"); + } + } +#endif + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack == NULL) || gCardDetectCallBack())) { + if (card_open() == TRUE && fat_initFAT(uiheapBufferAddr, FAT_HEAP_BUFFER_SIZE) == TRUE) { +#if UPDATE_SIM_CODE + BOOL bWDTInit = UTL_canUpdateSecKey(); + if (bWDTInit && fat_open_rootfile(RUN_WRKEY_NAME) == TRUE) { + debug_msg("sim.bin exist\r\n"); // the others A or T are skipped. + // Read byte count specified in file directory entry + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_WRBIN; + } else { // exclude others update if FUNC_RUN_WRBIN is existing. +#endif + // Update loader or not, loader is fixed to 16 KB + if (fat_open_rootfile(UPDATE_LOADER_NAME) == TRUE) { + // Read byte count specified in file directory entry + fat_read_rootfile((UINT8 *)uiUpdateBootloaderBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_UPDATE_LOADER; + uiLoaderSize = *((UINT32 *)(uiUpdateBootloaderBufAddr + 0x24)); + } + // "Update FW" or "Run FW" function + // Update FW has higher priority + if (fat_open_rootfile(UPDATE_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + uiLoaderFunc |= FUNC_UPDATE_FW; + } else { + // only rtos + debug_msg("not all-in-one, force behavior as T bin.\r\n"); + adjusted_addr = 0; + adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) == 0) { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } else { + bl_displayErrMsg("invalid firmware"); + } +#if UPDATE_EMU_CODE + uiLoaderFunc |= FUNC_UPDATE_FW; +#else + uiLoaderFunc |= FUNC_RUN_CARD; +#endif + + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + } + // Run FW has lower priority + else if (fat_open_rootfile(RUN_FW_NAME) == TRUE) { + NVTPACK_MEM mem_in ; + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, SIZE_PRELOAD); + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + // Read all + uiUpdateFileLen = fat_read_rootfile((UINT8 *)uiUpdateMainBinBufAddr, FAT_READ_TOTAL_FILE_LENGTH); + } else { + // Read rtos + unsigned int adjusted_addr = 0; + unsigned int adjusted_size = 0; + if (bl_load_rtos_from_non_nvtpack(uiUpdateMainBinBufAddr, uiUpdateFileLen, &adjusted_addr, &adjusted_size) != 0) { + bl_displayErrMsg("invalid firmware"); + } else { + uiFwBaseAddr = adjusted_addr; //fix compressed fit bl_checkDramScanFW() after copy its to temp area, see commit log + uiUpdateFileLen = adjusted_size; + } + uiLoaderFunc |= FUNC_RUN_CARD; + } + fat_close_rootfile(); + debug_msg("\r\n"); // for line end RRRRRRR.... + uiLoaderFunc |= FUNC_RUN_CARD; + } +#if UPDATE_SIM_CODE + } +#endif + card_close(); + } else { + debug_msg("card open fail\r\n"); +// while (1); + } + } else if (((gSpecialKeyCallBack == NULL) || gSpecialKeyCallBack()) && + ((gCardDetectCallBack != NULL) || (gCardDetectCallBack() == FALSE))) { + debug_msg("No card inserted\r\n"); + } +#endif + + if (uiLoaderFunc & FUNC_UPDATE_LOADER) { + bl_process_update_loader(uiUpdateBootloaderBufAddr, uiLoaderSize); + } + + // Run FW + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + if (uiLoaderFunc & (FUNC_RUN_CARD | FUNC_UPDATE_FW)) { + debug_msg("RC\r\n"); + NVTPACK_MEM mem_in ; + int chk_valid_all_in_one; +#if (DRAM_RANGE_SCAN_EN == ENABLE) + // First word is code entry point address, once if entry address is 0xC000XXXX + // represent code is running on sram. + debug_msg("Check SRAM fw\r\n"); + if (bl_checkDramScanFW(uiUpdateMainBinBufAddr) == TRUE) { + + debug_msg("This fw is on SRAM\r\n"); + // Enable sram usage + SETREG32(0xF0900128, 0x00000002); + SETREG32(0xF0800128, 0x00000006); + SETREG32(0xF0020060, 0x00030002); + + debug_msg(Dec2HexStr(*((UINT32 *)SRAM_Start_FW))); + debug_msg("before jump\r\n"); +// while (b_debug_go == FALSE); + load_dram_scan(uiUpdateMainBinBufAddr, uiUpdateFileLen); + return *((UINT32 *)SRAM_Start_FW); + } +#endif + mem_in.p_data = (void *)uiUpdateMainBinBufAddr; + mem_in.len = uiUpdateFileLen; + chk_valid_all_in_one = bl_chk_valid_all_in_one(&mem_in); + if (chk_valid_all_in_one == 0) { + // all-in-one flow + // File len got from fat_read_rootfile() may exceed actual file size. + // In such condition, we should use info in NVTPACK_FW_HDR2 + if (((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize < uiUpdateFileLen) { + uiUpdateFileLen = ((NVTPACK_FW_HDR2 *)uiUpdateMainBinBufAddr)->TotalSize; + mem_in.len = uiUpdateFileLen; + } +#if (REMOVED_FLASH == ENABLE) + bl_displayErrMsg("cannot process all-in-one fw"); +#else + uiFwBaseAddr = bl_process_all_in_one(uiUpdateMainBinBufAddr, uiUpdateFileLen, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); +#endif + } else { + // non-all-in-one flow + // check valid + if (uiLoaderFunc & FUNC_UPDATE_FW) { +#if UPDATE_EMU_CODE + bl_process_update_emu_firmware(uiUpdateMainBinBufAddr, uiUpdateFileLen); +#else + bl_displayErrMsg("cannot write non-all-in-one fw"); +#endif + } + uiFwBaseAddr = bl_process_rtos_only(uiUpdateMainBinBufAddr, mem_in.len, uiLoaderFunc, &comp_addr, &comp_size); + } + + // here uiFwBaseAddr is ready to use. + if (comp_addr == 0) { + HEADINFO *p_headinfo = (HEADINFO *)(uiFwBaseAddr + BIN_INFO_OFFSET_RTOS); + debug_msg("Nrml\r\n"); + if (chk_valid_all_in_one == 0) { + uiUpdateFileLen = p_headinfo->BinLength; + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + // uiUpdateFileLen is already set when file is loaded + } + } else { + debug_msg("Fcompress\r\n"); + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + debug_msg_var("uiUpdateFileLen", uiUpdateFileLen); + //boot from flash or update fw is no need to check sanity because of ecc, turn on it just for debug + if (uiLoaderFunc & FUNC_RUN_CARD) { + bl_checkFW(uiUpdateMainBinBufAddr, uiUpdateFileLen); + } + if (chk_valid_all_in_one == 0) { + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); + } else { + debug_msg_var("fw load addr", uiUpdateMainBinBufAddr); + bl_update_uItron_headInfo(uiUpdateMainBinBufAddr, p_dram_partition); + } + } else { //boot from flash +#if (REMOVED_FLASH == DISABLE) +#if UPDATE_EMU_CODE +// UINT32 uiNandBlkSize; + // open flash + if (bl_flash_open() != 0) { + bl_displayErrMsg("flash open failed\r\n"); + } + debug_msg("RFlash\r\n"); + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW, g_uiNandBlkSize, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiUpdateFileLen = *(volatile UINT32 *)(SDRAM_Start_FW + 0x168); + + if (int_strg_obj->flash_readSectors(g_uiStartBlkUpdateFW + 1, uiUpdateFileLen - g_uiNandBlkSize, (UINT8 *)(SDRAM_Start_FW + g_uiNandBlkSize), NAND_RW_FIRMWARE) < 0) { + bl_displayErrMsg(RWErrorMsg); + } + + uiFwBaseAddr = bl_process_rtos_only(SDRAM_Start_FW, uiUpdateFileLen, uiLoaderFunc, &comp_addr, &comp_size); + bl_checkFW(SDRAM_Start_FW, uiUpdateFileLen); + uiUpdateMainBinBufAddr = SDRAM_Start_FW; + if (comp_addr == 0) { + debug_msg("Nrml\r\n"); + } else { + debug_msg("Fcompress not support\r\n"); + } + +#else + uiFwBaseAddr = bl_process_flash_boot((UINT8 *)SDRAM_Start_FW, &p_dram_partition, uiLoaderFunc, &comp_addr, &comp_size); + if (comp_addr == 0) { + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } else { + //for speed up, u-boot only copy compressed rtos and loader needs to decode it + uiUpdateFileLen = bl_decompress_rtos(comp_addr, comp_size, uiFwBaseAddr); + uiUpdateMainBinBufAddr = uiFwBaseAddr; + } + // no need to bl_checkFW, because check sanity in flash_read + bl_update_uItron_headInfo(uiFwBaseAddr, p_dram_partition); +#endif +#endif + } + + if (p_dram_partition) { + bl_update_loader_bininfo((unsigned char *)p_dram_partition->fdt_addr, uiLoaderFunc, uiUpdateFileLen); + } + +#if UPDATE_EMU_CODE + debug_msg_var("emu fw len", uiUpdateFileLen); +#endif + g_rtos_load_addr = uiUpdateMainBinBufAddr; + g_rtos_target_addr = uiFwBaseAddr; + g_rtos_size = uiUpdateFileLen; + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + debug_msg_var("rtos start", uiFwBaseAddr); + return uiFwBaseAddr; + +} + +_THUMB2 void loader_setUpdateFwName(char *fileName) +{ + strncpy((char *)UPDATE_FW_NAME, fileName, sizeof(UPDATE_FW_NAME)); +} + +_THUMB2 void loader_setUpdateLdrName(char *fileName) +{ + strncpy((char *)UPDATE_LOADER_NAME, fileName, sizeof(UPDATE_LOADER_NAME)); +} + +_THUMB2 void loader_setRunFwName(char *fileName) +{ + strncpy((char *)RUN_FW_NAME, fileName, sizeof(RUN_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryFwName(char *fileName) +{ + strncpy((char *)RECOVERY_FW_NAME, fileName, sizeof(RECOVERY_FW_NAME)); +} + +_THUMB2 void loader_setRecoveryPartitionID(UINT32 partition_id) +{ + g_uiPartitionID = partition_id; +} + +_THUMB2 void loader_setVersion(UINT32 version) +{ + g_uiVersion = version; +} + +_THUMB2 void loader_installSpecialKeyCB(LDR_SPECIAL_KEY_CB callback) +{ + gSpecialKeyCallBack = callback; +} + +_THUMB2 void loader_installCardDetectCB(LDR_CARD_DETECT_CB callback) +{ + gCardDetectCallBack = callback; +} + +_THUMB2 void loader_installRecoveryTriggerCB(LDR_RECOVERY_TRIGGER_CB callback) +{ + gRecoveryTriggerCallBack = callback; +} + +_THUMB2 void loader_installFastbootKeyCB(LDR_FASTBOOT_KEY_CB callback) +{ + gFastbootKeyCallBack = callback; +} + +_THUMB2 void loader_setStorageIntType(STORAGEINT type, PSTORAGE_OBJ strg_obj) +{ + gStorageIntType = type; + int_strg_obj = strg_obj; +} diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h new file mode 100755 index 000000000..04d8e06f4 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_func.h @@ -0,0 +1,302 @@ +/** + @file bl_func.h + @brief Header file for main function + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#ifndef _BL_MAIN_H +#define _BL_MAIN_H + +#include "main.h" +#include "IOReg.h" +#include "GPIO.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "loader.h" +//------------------------------------------------------------------------------ +// Compiler option +// +// These compiler option are define in MakeConfig.txt +//!!!!!!!!!!!!!!!!!!! DO NOT MODIFY COMPILER OPTION HERE !!!!!!!!!!!!!!!!!!!! +//------------------------------------------------------------------------------ +#ifndef SECURE_DECRYPT_UBOOT +#define SECURE_DECRYPT_UBOOT 0 //Decrypt uboot sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + +#ifndef SECURE_DECRYPT_OPTEE_OS +#define SECURE_DECRYPT_OPTEE_OS 0 //Decrypt optee_os sample code +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt +#ifndef SECURE_SIGNATURE_BY_AES +#define SECURE_SIGNATURE_BY_AES 0 //using aes to decrypt signature +#endif //Option move to ModelConfig_EMU_EVB_XXX.txt + + +#if (SECURE_DECRYPT_UBOOT || SECURE_DECRYPT_OPTEE_OS) +#define SECURE_OFFSET 1024 //Decrypt uboot from which offset +#endif + +// Define LED_FUNCTION == ENABLE will enable LED on/off in boot loader +#define LED_FUNCTION ENABLE//DISABLE + +// FW checking method, support checksum & CRC now +//#define FW_CHECK_NOCHECK 0 +//#define FW_CHECK_CHECKSUM 1 +//#define FW_CHECK_CRC 2 +#ifndef FW_CHECK_METHOD +#define FW_CHECK_METHOD FW_CHECK_CHECKSUM +#endif + +///#define FW_CHECK_INSTRUCTION0 0xE59FF018 + +// Optional pseudo string for checksum & CRC checking +#define FW_CHECK_PSEUDO_STR_EN DISABLE +#if (FW_CHECK_PSEUDO_STR_EN == ENABLE) + // Must sync to MakeConfig.txt + #define FW_CHECK_PSEUDO_STR "DSC_FW" +#endif + +// Determine if need to support compressable main code +#ifndef _MAINCODE_COMPRESS_ +#define _MAINCODE_COMPRESS_ 0 +#endif + +#ifndef STORAGEINT_SPI +#define STORAGEINT_SPI 0 +#endif + +#define FW_EXCEED_16MB_TEST DISABLE + +//------------------------------------------------------------------------------ +// Global definition +//------------------------------------------------------------------------------ +#define LOADER_CODE_SIZE 0x8000 // Reserve 32 KB + +#define RESERVED_DATA_SIZE 0x4000 // Fixed to 16 KB + +//Once if optee exist need modify to 0x02800000 +//#define SDRAM_Start_FW 0x02800000 // DRAM uITRON starting address +#define SDRAM_Start_FW 0x02000000 +//#endif + +#define SRAM_Start_FW 0xF07c0000 // SRAM FW starting address + +#define SRAM_TAG 0xF0000000 // SRAM tag + +#define CORE2_JUMP_ADDR 0x00000000 // Core2 entry code should put on 0, because when core2 reset is released, core2 will jump to 0 and run + +#define CPU_TIMER_SETTING 0x00B71B00 //0x016E3600 + +#define _BOARD_IPC_ADDR_ 0x00002000 // must be the same with BOARD_IPC_ADDR on ModelConfig. + + +#define UPDATE_CFG_BUFADDR 0x05000000 +#define UPDATE_CFG_TAGCODE 0xABCD0043 +#define UPDATE_CFG_LOADER_OFS 0x00 +#define UPDATE_CFG_FW_OFS 0x10 + +#define UPDATE_CFG_ITEM_LD 0xABCD0001 +#define UPDATE_CFG_ITEM_FW 0xABCD0002 + +#define UPDATE_CFG_TAG 0 +#define UPDATE_CFG_ITEM 1 +#define UPDATE_CFG_ADDR 2 +#define UPDATE_CFG_LEN 3 + +#define USB_RESULT_LOADER_INVALID_FW_INVALID (0) +#define USB_RESULT_LOADER_INVALID_FW_OK (1) +#define USB_RESULT_LOADER_INVALIE_FW_FAIL (2) +#define USB_RESULT_LOADER_OK_FW_INVALID (3) +#define USB_RESULT_LOADER_FAIL_FW_INVALID (4) +#define USB_RESULT_LOADER_OK_FW_OK (5) +#define USB_RESULT_LOADER_FAIL_FW_OK (6) +#define USB_RESULT_LOADER_OK_FW_FAIL (7) +#define USB_RESULT_LOADER_FAIL_FW_FAIL (8) +#define USB_RESULT_OTHER (9) + +// Loader checking +#define LOADER_TAG_OFFSET 0x30 +#define LOADER_TAG_VALUE 0xAA55 + +//#NT#2011/06/30#Steven Wang -begin +//#NT#Checksum offset +///#define CHECKSUM_OFFSET 0x1C +#define CHECKSUM_TAG 0xAA55 +//#NT#2011/06/30#Steven Wang -end + +// Config table tag value (for USB flow) +#define CFG_TABLE_TAG (0x4B54564E) // 'N' 'V' 'T' 'K' + +#define COMPRESS_TAG_VALUE (0x314C4342) // use to distinguish full compressed main code + +#define SPI_FLASH_IDENTIFY (0x46495053) //'S''P''I''F' + +#define BOOTVER_SET(OutMaj,OutMin,InnMaj,InnMin) (((OutMaj)<<24)|((OutMin)<<16)|((InnMaj)<<8)|((InnMin))) + +#define BOOTVER_GETOuterMajor(Ver) (((Ver)&0xFF000000)>>24) +#define BOOTVER_GETOuterMinor(Ver) (((Ver)&0x00FF0000)>>16) +#define BOOTVER_GETInnerMajor(Ver) (((Ver)&0x0000FF00)>>8) +#define BOOTVER_GETInnerMinor(Ver) (((Ver)&0x000000FF)) + +// Define loader version (_LDR_VER_) in MakeConfig.txt +#define BOOTLOADER_OUTERMAJOR (((_LDR_VER_)&0xFF000000)>>24) +#define BOOTLOADER_OUTERMINOR (((_LDR_VER_)&0x00FF0000)>>16) +#define BOOTLOADER_INNERMAJOR (((_LDR_VER_)&0x0000FF00)>>8) +#define BOOTLOADER_INNERMINOR (((_LDR_VER_)&0x000000FF)) + +// Binary tag value +#define FW_BINARY_TAG 0xAA55544E // 'N' 'T' 0x55 0xAA + +// CAL FW size exit tag +#define CAL_SIZE_TAG 0x5A534C43 // CLSZ +// FW size exit tag +#define FW_SIZE_TAG 0x5A535746 // FWSZ + +// Reserved area FW size offset +#define RESERVED_AREA_FW_SIZE_OFFSET 0x00 +// Reserved area CAL size offset +#define RESERVED_AREA_CAL_SIZE_OFFSET 0x04 +// Reserved area FW size tag offset +#define RESERVED_AREA_FW_TAG_OFFSET 0x08 +// Reserved area CAL size tag offset +#define RESERVED_AREA_CAL_TAG_OFFSET 0x0C + +// Operation of boot loader +#define FUNC_UPDATE_FW 0x01 // Read FW code from card and update to NAND and run +#define FUNC_UPDATE_LOADER 0x02 // Read boot loader code from card and update to NAND +#define FUNC_RUN_CARD 0x04 // Read FW code from card and run +#define FUNC_RUN_FLASH 0x08 // Read FW code from internal flash and run +#define FUNC_UPDATE_CAL 0X10 // Update CAL data +#define FUNC_RUN_WRBIN 0X20 // RUN wrkey data +#define FUNC_RUN_UBOOT 0X40 // Read Uboot from card and run +#define FUNC_UPDATE_FW_DONE 0x0100 // update f/w to NAND/SPI done + +// API to turn on / off LED +#if (LED_FUNCTION == ENABLE) +// Red LED (DGPIO 6) +// Green LED (DGPIO 9) +#define TurnOff_RedLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000040) +#define TurnOn_RedLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000040) +#define TurnOff_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x4C, 0x00000200) +#define TurnOn_GreenLED() OUTREG32(CPE_GPIO_BASE + 0x38, 0x00000200) +#else +#define TurnOff_RedLED() +#define TurnOn_RedLED() +#define TurnOff_GreenLED() +#define TurnOn_GreenLED() +#endif + +//Configure build as USB write loader @ ModelConfig_EMU_EVB.txt +//UART & USB can enable at the same time. +#if (STORAGE_EXT_TYPE == STORAGE_EXT_USB) || (STORAGE_EXT_TYPE == STORAGE_EXT_UART) +#define USB_WRITELOADER ENABLE +#define UART_UPDATE ENABLE +#else +#define USB_WRITELOADER DISABLE +#define UART_UPDATE DISABLE +#endif +#define UART_UPDATE_ DISABLE +#define UPDATE_EMU_CODE DISABLE +#define REMOVED_FLASH DISABLE +#define NUTTX_SUPPORT DISABLE +#define UPDATE_SIM_CODE DISABLE +#define UITRON_FW DISABLE +#define FDT_SUPPORT ENABLE +#define DUAL_RTOS_SUPPORT DISABLE // only for rtos-uvc project +#define STAND_ALONE_LOADER_560 0 + +#define LOADER_TYPE STAND_ALONE_LOADER_560 + +#define COMBINATION_LOADER_SIZE 0x18000 + +#define EMUKIT 0 +#define DEMOKIT 0x1800000 +#define RESUME_ADDR DEMOKIT + +//#NT#2018/03/07#Ben Wang -begin +//#NT#Support EMMC boot flow +#define EMMC_BLOCK_SIZE 0x200 +#define FDT_OFFSET 0x40000 +//#NT#2018/03/07#Ben Wang -end + +#if (STORAGEINT_SPI == 1) + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkReserved 0 + //#NT#2012/12/17#HH Chuang -begin + //#NT#Sync spi erase unit to best access size of f/w storage object + #define StartNandBlkUpdateFW 16 + //#NT#2012/12/17#HH Chuang -end +#else + #define StartNandBlkUpdateLoader 0 + #define StartNandBlkUpdateFW 2 +#endif + +#if (FW_CHECK_METHOD == FW_CHECK_CRC) +static UINT32 g_uiCRCTable[256]; +#endif + +//Define @prj_main.h +#if 0 +// Card detect GPIO offset +#define DGPIO_CARD_DETECT (P_GPIO_17) + + +#define CHECK_CARD_EXIST (ENABLE) +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +#define bl_checkCardExist() (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE) +#else +#define bl_checkCardExist() TRUE +#endif +#endif +/** + @name Assert macros +*/ +//@{ +#define ASSERT_CONCAT_(a, b) a##b +#define ASSERT_CONCAT(a, b) ASSERT_CONCAT_(a, b) + +#if defined(__COUNTER__) + +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __COUNTER__) = 1/(expr) } + +#else + +// This might cause compile error when writing STATIC_ASSERT at the same line +// in two (or more) files and one file include another one. +#define STATIC_ASSERT(expr) \ +enum { ASSERT_CONCAT(FAILED_STATIC_ASSERT_, __LINE__) = 1/(expr) } + +#endif +//@} + +//#NT#2010/05/21#Steven Wang -begin +//#NT#Check if FW size > EXEC base address +//extern UINT32 _load_BOOT_EXEC_start_base; +//#NT#2010/05/21#Steven Wang -end + +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; + +extern UINT32 LoaderInternalInfo[]; + +extern PSTORAGE_OBJ int_strg_obj; + +//------------------------------------------------------------------------------ +// internal functions +//------------------------------------------------------------------------------ +extern int bl_chk_valid_all_in_one(NVTPACK_MEM *p_mem_all_in_one); +extern int bl_chk_uboot(unsigned int addr, unsigned int size); +extern unsigned int bl_process_all_in_one(UINT32 uiFwBuf, UINT32 uiFwBufSize, DRAM_PARTITION **pOut_dram_partition, UINT32 uiLoaderFunc, UINT32 *p_comp_addr, UINT32 *p_comp_size); +extern int bl_boot_uboot(unsigned char *p_fdt); +extern int bl_chk_fdt(unsigned int addr, unsigned int size); +extern int bl_copy_fdt_to_fdt_addr(unsigned char *p_fdt /*IN*/, unsigned char **pp_fdt /*OUT*/); +extern int bl_flash_open(void); +// Exported functions +//------------------------------------------------------------------------------ +extern UINT32 bl_mainFlow(void); +extern UINT32 BaseOfStack; + +// project(customer) main function +extern void prj_main(void); +extern void bl_read_rtos_addr(UINT32* pLoadAddr, UINT32* pTargetAddr, UINT32* pSize); +#endif diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c new file mode 100755 index 000000000..46cad2921 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.c @@ -0,0 +1,404 @@ +#include "constant.h" +#include "fuart.h" +#include "fat.h" +#include "StorageDef.h" +#include "global.h" +#include "nvtpack.h" +#include "dram_partition_info.h" +#include "bl_func.h" +#include "string.h" +#include "lz.h" +#include "debug.h" +#include "loader.h" +#include "emb_partition_info.h" +#include "modelext_info.h" +#include "bin_info.h" +#include "shm_info.h" +#include "libfdt.h" +#include +//#include "mmc_api.h" +#include "Cache.h" +#include "Memory.h" +#include "timer.h" +#include "lz.h" +#include "bl_u2.h" +#include "nand.h" +#include "nor.h" + +#ifndef ALIGN_FLOOR +#define ALIGN_FLOOR(value, base) ((value) & ~((base)-1)) +#endif +#ifndef ALIGN_CEIL +#define ALIGN_CEIL(value, base) ALIGN_FLOOR((value) + ((base)-1), base) +#endif + +#if (USB_WRITELOADER || UART_UPDATE) + +//u2: means usb and uart +#include "scsi_op.h" + +typedef enum _U2_FW_TYPE { + U2_FW_TYPE_UNKNOWN, + U2_FW_TYPE_NVTPACK, + U2_FW_TYPE_UBOOT, +} U2_FW_TYPE; + +#define MAKEUINT32(a, b, c, d) ((UINT32)((a)&0xFF)) | (((UINT32)((b)&0xFF)) << 8) | (((UINT32)((c)&0xFF)) << 16) | (((UINT32)((d)&0xFF)) << 24) + +static U2_FW_TYPE m_u2_fw_type = U2_FW_TYPE_UNKNOWN; +static unsigned int m_u2_fw_size = 0; +static unsigned char *m_fdt = NULL; +UINT32 m_tmp_addr = SDRAM_Start_FW; +static int m_uboot_status = -2; +static int m_fdt_status = -1; +static SCSIOP_FLASH_OP m_flash_op = {0}; + +__attribute__((target("thumb2"))) static int u2_check_firmware(unsigned int addr) +{ + NVTPACK_FW_HDR2 *p_hdr = (NVTPACK_FW_HDR2 *)addr; + unsigned int size = p_hdr->TotalSize; + NVTPACK_MEM mem_in ; + mem_in.p_data = (void *)addr; + mem_in.len = size; + // all in one bin + if (bl_chk_valid_all_in_one(&mem_in) == 0) { + m_u2_fw_type = U2_FW_TYPE_NVTPACK; + m_u2_fw_size = size; + return 0; + } + // uboot + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + addr = addr_uncomp; + } + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + if (p_headinfo->BinLength < 0x1000000 && bl_chk_uboot(addr, p_headinfo->BinLength) == 0) { + m_u2_fw_type = U2_FW_TYPE_UBOOT; + m_u2_fw_size = p_headinfo->BinLength; + if (m_fdt == NULL) { + //check fdt followed uboot + unsigned char *fdt = (unsigned char *)(addr + m_u2_fw_size); + if (fdt_check_header(fdt) != 0) { + debug_err("no fdt behind uboot\r\n"); + return -1; + } + } + return 0; + } + + return -1; +} + +__attribute__((target("thumb2"))) static int u2_boot_uboot(unsigned int addr, unsigned int size, U2_FW_TYPE fw_type) +{ + if (fw_type == U2_FW_TYPE_NVTPACK) { + UINT32 comp_addr = 0; + UINT32 comp_size = 0; + DRAM_PARTITION *p_dram_partition = NULL; + return bl_process_all_in_one(addr, size, &p_dram_partition, FUNC_UPDATE_FW, &comp_addr, &comp_size); + } else { + // update headinfo as real u-boot address + HEADINFO *p_headinfo = (HEADINFO *)(addr + BIN_INFO_OFFSET_UBOOT); + NVTPACK_BFC_HDR *pBfc = (NVTPACK_BFC_HDR *)addr; // describe compressed u-boot + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + UINT32 addr_uncomp = ALIGN_CEIL(addr + size_comp_le, 4); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)addr_uncomp, 1024); + p_headinfo = (HEADINFO *)(addr_uncomp + BIN_INFO_OFFSET_UBOOT); + } + // check tmp memory (file load) cannot overlap with uboot + if ((addr < p_headinfo->CodeEntry && addr + size > p_headinfo->CodeEntry) || + (addr > p_headinfo->CodeEntry && addr + size < p_headinfo->CodeEntry + size)) { + debug_err_var("addr", addr); + debug_err_var("size", size); + debug_err_var("CodeEntry", p_headinfo->CodeEntry); + debug_err("uboot & tmp_addr are overlapped\r\n"); + return -1; + } + + if (pBfc->uiFourCC == MAKEFOURCC('B', 'C', 'L', '1')) { + UINT32 size_comp_le = __builtin_bswap32(pBfc->uiSizeComp); + LZ_Uncompress((UINT8 *)addr + sizeof(NVTPACK_BFC_HDR), (unsigned char *)p_headinfo->CodeEntry, size_comp_le); + } else { + utl_memcpy((void *)p_headinfo->CodeEntry, (void *)addr, size); + } + + if (m_fdt != NULL) { + bl_boot_uboot(m_fdt); + } else { + //check fdt followed uboot + unsigned char *fdt = (unsigned char *)(addr + size); + if (fdt_check_header(fdt) != 0) { + debug_err("no fdt behind uboot\r\n"); + return -1; + } + utl_memcpy((void *)(p_headinfo->CodeEntry + size), fdt, fdt_totalsize(fdt)); + debug_msg_var("jump", p_headinfo->CodeEntry); + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); + { + typedef void (*BRANCH_CB)(void); + BRANCH_CB p_func = (BRANCH_CB)p_headinfo->CodeEntry; + p_func(); + } + } + } + return 0; +} + +__attribute__((target("thumb2"))) static int u2_on_verify(unsigned int p_cmd, unsigned int *p_data, unsigned int *in_size) +{ + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (p_cbw->dCBWDataTransferLength != sizeof(m_flash_op)) { + debug_err_var("m_flash_op size not matched", *in_size); + return -1; + } + *p_data = (UINT32)&m_flash_op; + *in_size = p_cbw->dCBWDataTransferLength; + break; + case SCSIOP_IN_MEM_READ: + *p_data = MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5]); + *in_size = p_cbw->dCBWDataTransferLength; + //debug_msg_var("p_data:", MAKEUINT32(p_cbw->CBWCB[2], p_cbw->CBWCB[3], p_cbw->CBWCB[4], p_cbw->CBWCB[5])); + break; + case SCSIOP_IN_GET_TMP_ADDR: + *p_data = (unsigned int)&m_tmp_addr; + *in_size = sizeof(m_tmp_addr); + break; + case SCSIOP_IN_FDT: + *p_data = (unsigned int)&m_fdt_status; + *in_size = sizeof(m_fdt_status); + if (bl_chk_fdt((unsigned int)SDRAM_Start_FW, fdt_totalsize(SDRAM_Start_FW)) == 0) { + m_fdt_status = bl_copy_fdt_to_fdt_addr((unsigned char *)SDRAM_Start_FW, &m_fdt); + } else { + m_fdt_status = -1; + } + break; + case SCSIOP_IN_UBOOT: + *p_data = (unsigned int)&m_uboot_status; + *in_size = sizeof(m_uboot_status); + if (u2_check_firmware(SDRAM_Start_FW) == 0) { + m_uboot_status = 0; + } else { + m_uboot_status = -1; + } + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb2"))) static int u2_flash_open(unsigned int flash_type) +{ + static int is_opened[4] = {0}; + + if (flash_type >= 4) { + debug_err_var("flash_type", flash_type); + return -1; + } + + // open default and its related to + if (is_opened[0] == 0) { + if (bl_flash_open() != 0) { + return -1; + } + is_opened[0] = 1; +#if !defined(_STORAGEINT_EMMC_) + if (int_strg_obj == nand_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + } + if (int_strg_obj == nor_get_storage_object()) { + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + } +#endif + } + + if (is_opened[flash_type]) { + return 0; + } + +#if !defined(_STORAGEINT_EMMC_) + switch(flash_type) { + case FLASH_ACCESS_TYPE_NAND: +#if 0 + // User define SPI-NAND id table sample code + nand_get_storage_object()->flash_setConfig(FLASH_CFG_ID_SPI_IDENTIFY_CB, (UINT32)nand_identify); +#endif + nand_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NAND] = 1; + break; + case FLASH_ACCESS_TYPE_NOR: +#if 0 + // User define SPI-NOR id table sample code + nor_get_storage_object()->flash_installIdentifyCB(nor_identify); +#endif + nor_get_storage_object()->flash_open(); + is_opened[FLASH_ACCESS_TYPE_NOR] = 1; + break; + default: + debug_err_var("unsupported flash_type", flash_type); + return -1; + } + return 0; +#else + debug_err("flash_type must be auto on emmc"); + return -1; +#endif +} + +__attribute__((target("thumb2"))) static int u2_on_vendor(unsigned int p_cmd) +{ + int er; + PSTORAGE_OBJ p_strg = NULL; + NVT_SCSI_CBW *p_cbw = (NVT_SCSI_CBW *)p_cmd; + int cmd_id = p_cbw->CBWCB[1]; + + switch (cmd_id) { + case SCSIOP_OUT_MEM_WRITE: + break; + case SCSIOP_OUT_FLASH_ACCESS: + if (u2_flash_open(m_flash_op.type) != 0) { + return -1; + } + switch(m_flash_op.type) { + case FLASH_ACCESS_TYPE_AUTO: + p_strg = int_strg_obj; + break; +#if !defined(_STORAGEINT_EMMC_) + case FLASH_ACCESS_TYPE_NAND: + p_strg = nand_get_storage_object(); + break; + case FLASH_ACCESS_TYPE_NOR: + p_strg = nor_get_storage_object(); + break; +#endif + default: + debug_err_var("unsupport flash_type", m_flash_op.type); + return -1; + } + + if (m_flash_op.is_write) { + //write + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int write_size = ALIGN_CEIL(m_flash_op.size, block_size); + if (startblk == 0) { + // write block 0 means update loader area + if ((er = p_strg->flash_writePartition(startblk, write_size, (unsigned int)(m_flash_op.partition_size), (UINT8 *)SDRAM_Start_FW, NAND_RW_LOADER)) != 0) { + debug_err_var("wr failed", er); + return -1; + } + } else { + if ((er = p_strg->flash_writePartition(startblk, write_size, (unsigned int)(m_flash_op.partition_size), (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("wr failed", er); + return -1; + } + } + //Once write loader something wrong happen.. + //Can enable code bellow make sure data were program into SPI-NOR/NAND +#if 0 + else { //Read back and make checksum + unsigned int reload_addr; + UINT32 status = 0; + reload_addr = SDRAM_Start_FW + write_size; + + int_strg_obj->flash_getConfig(FLASH_CFG_ID_SPI_GET_STATUS_1,(UINT32)&status); + debug_msg_var( +"status1", status); + + if (int_strg_obj->flash_readSectors(startblk, write_size, (UINT8 *)reload_addr, NAND_RW_LOADER) < 0) { + debug_err("rd fail\r\n"); + } else { + debug_err("rd success\r\n"); + } + // Verify + if (memcmp((void *)SDRAM_Start_FW, (void *)reload_addr, write_size) != 0) { + debug_err("verify fail\r\n"); + } else { + debug_msg_var("read back 0x0",*(UINT32 *)(reload_addr+0x0)); + debug_msg_var("read back 0x4",*(UINT32 *)(reload_addr+0x4)); + debug_msg_var("read back 0x8",*(UINT32 *)(reload_addr+0x8)); + debug_msg_var("read back 0xc",*(UINT32 *)(reload_addr+0xc)); + } + + } +#endif + } else { + //read + unsigned int block_size = p_strg->flash_getBlockSize(); + unsigned int startblk = (unsigned int)(m_flash_op.offset / block_size); + unsigned int read_size = ALIGN_CEIL(m_flash_op.size, block_size); + if (startblk == 0) { + // read block 0 means update loader area + if ((er = p_strg->flash_readSectors(startblk, read_size, (UINT8 *)SDRAM_Start_FW, NAND_RW_LOADER)) != 0) { + debug_err_var("rd failed", er); + return -1; + } + } else { + if ((er = p_strg->flash_readSectors(startblk, read_size, (UINT8 *)SDRAM_Start_FW, NAND_RW_FIRMWARE)) != 0) { + debug_err_var("rd failed", er); + return -1; + } + } + } + break; + case SCSIOP_IN_MEM_READ: + case SCSIOP_IN_GET_TMP_ADDR: + break; + case SCSIOP_IN_FDT: + break; + case SCSIOP_IN_UBOOT: + break; + default: + debug_err_var("unknown_cmd_id", cmd_id); + break; + } + return 0; +} + +__attribute__((target("thumb2"))) int bl_usb(void) +{ + + typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); + extern void fLib_USB_Update_FW(void); + extern MSDC_Verify_CB guiU2MsdcCheck_cb; + extern MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + guiU2MsdcCheck_cb = u2_on_verify; + guiU2MsdcVendorDone_cb = u2_on_vendor; + fLib_USB_Update_FW(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +__attribute__((target("thumb2"))) int bl_uart(void) +{ + + typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); + typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); + extern void uart_upgrade_procedure(void); + extern UART_Verify_CB guiUARTCheck_cb; + extern UART_Vendor_CB guiUARTVendor_cb; + guiUARTCheck_cb = u2_on_verify; + guiUARTVendor_cb = u2_on_vendor; + uart_upgrade_procedure(); + u2_boot_uboot(SDRAM_Start_FW, m_u2_fw_size, m_u2_fw_type); + return 0; +} + +#endif //USB_WRITELOADER diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h new file mode 100755 index 000000000..28ae6ee7c --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/bl_u2.h @@ -0,0 +1,7 @@ +#ifndef _BL_USB_H +#define _BL_USB_H + +extern int bl_usb(void); +extern int bl_uart(void); + +#endif \ No newline at end of file diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c b/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c new file mode 100755 index 000000000..f715100ca --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/main.c @@ -0,0 +1,168 @@ +/* + Main control function + + This file is implement by user mode + + @file main.c + + Copyright Novatek Microelectronics Corp. 2014. All rights reserved. +*/ +#include "main.h" +#include "bl_func.h" +#include "Cache.h" +#include "global.h" +#include "fuart.h" +#include "debug.h" + +extern char _loader_exec_compres_start[]; +extern char _loader_exec_compress_load_cpu_addr[]; +extern char _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[]; +extern char _load_BOOT_EXEC_start_base[]; +extern char _loader_data_start_base[]; +#define _THUMB2 __attribute__((target("thumb2"))) +//--------------------------------------------------------------------------- +// Static function +//--------------------------------------------------------------------------- +/* + BL_RunPartOne + + Expend loader if use compress + + @return void +*/ +_THUMB2 static void BL_RunPartOne(void) +{ +#if (_LOADER_COMPRESSED_ == ENABLE) +#if (_PROCESS_2ND_CHECKSUM_ == 1) + NVTPACK_MEM mem = {0}; + UINT16 sum; + UINT16 src_sum; +#endif + UINT8 *in_addr = (UINT8 *)(_loader_exec_compress_load_cpu_addr); + UINT8 *out_addr = (UINT8 *)(_loader_exec_compres_start); + UINT32 uiCompressedOutSize; + + // Get decompress size within specific header + uiCompressedOutSize = (((UINT32)*(in_addr + 12)) << 24) + + (((UINT32)*(in_addr + 13)) << 16) + + (((UINT32)*(in_addr + 14)) << 8) + + ((UINT32)*(in_addr + 15)); + + // Decompress loader image +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'L'; +#endif + LZ_Un_compress((unsigned char *)(in_addr + LDC_HEADER_SIZE), (unsigned char *)(out_addr), uiCompressedOutSize); +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'Z'; +#endif + // Need to clean data cache + CPUInvalidateICacheAll(); +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'I'; +#endif + CPUCleanInvalidateDCacheAll(); +#if (_PROCESS_2ND_CHECKSUM_ == 1) + *(UINT32 *)0xF0290000 = 'D'; +#endif + +#if (_PROCESS_2ND_CHECKSUM_ == 1) + // debug_msg_var("addr", (UINT32)(_load_BOOT_EXEC_start_base)); + mem.p_data = (void *)out_addr; + mem.len = *(UINT16 *)(_load_BOOT_EXEC_start_base + 0x14 + 0x2); + src_sum = *(UINT16 *)(_load_BOOT_EXEC_start_base + 0x14); + sum = nvtpack_calc_nvt_sum(&mem); + if(src_sum == sum) { + debug_msg("\r\nCHKSUM UNZOK!"); + } else { + debug_msg_var("\r\nCHKSUM UNZNG!", sum); + debug_msg_var("calc_sum=",sum); + debug_msg_var(" bin_sum=",src_sum); + } +#else + debug_msg("\r\nUNZOK!"); +#endif +#else +#endif +} + +/* +void BL_PostHandle(void) +{ + UINT32 uiParamCnt; + UINT32 *pParamOffset; + UINT32 *pDramParam; + + pParamOffset = (UINT32*)(&_load_LOADER_CONFIGRAM_FREQ_PARAM_start_base[5*4]); + pDramParam = (UINT32*)(*pParamOffset); + for (uiParamCnt=0; uiParamCnt < 7*2; uiParamCnt++) + { + OUTREG32(DDR_PARAM_LEVEL_0_ADDR + uiParamCnt*4, pDramParam[uiParamCnt]); + } + + // Disable IDE2 clock + CLRREG32(0xC0020070, 1<<17); + + //invalid Instruciton and data cache + CPUCleanInvalidateDCacheAll(); + CPUInvalidateICacheAll(); +} +*/ +_THUMB2 UINT32 main(void) +{ + UINT32 uiReturn; + UINT32 load_addr, target_addr, uitron_size; + UINT32 i; + UINT32 *pSrc, *pDst; + // Run part one loader + // If using compressed loader, just decompress the loader image at first! + BL_RunPartOne(); + utl_dram_protect_enable((UINT32)_loader_exec_compres_start, (UINT32)(_loader_data_start_base - _loader_exec_compres_start)); + uiReturn = bl_mainFlow(); + utl_dram_protect_check(); + utl_dram_protect_disable(); + + bl_read_rtos_addr(&load_addr, &target_addr, &uitron_size); + if (load_addr != target_addr) { + uart_putSystemUARTStr("uitron target_addr= "); + PrintDec2Hex(target_addr); + uart_putSystemUARTStr("\r\n"); + uart_putSystemUARTStr("uitron load_addr= "); + PrintDec2Hex(load_addr); + uart_putSystemUARTStr("\r\n"); + uart_putSystemUARTStr("Copy from load to target by loader, this may has longer boot time\r\n"); + CPUflushReadCache(0, 128*1024); + CPUInvalidateICacheAll(); + +#if 1 + // disable MMU + { \ + __asm__ __volatile__( \ + "mrc p15, 0, r0, c1, c0, 0\n\t" \ + "bic r0, r0, #0x5\n\t" \ + "bic r0, r0, #0x1000\n\t" \ + "mcr p15, 0, r0, c1, c0, 0\n\t" \ + : \ + : \ + : "r0" \ + ); \ + } + asm volatile("dsb"); + asm volatile("isb"); + uart_putSystemUARTStr("disable MMU done\r\n"); +#endif + + pSrc = (UINT32*)load_addr; + pDst = (UINT32*)target_addr; + for (i=0; ipagesize = nvt_nand_ids[ui_nand_ids].pagesize; + pIdentify->erasesize= nvt_nand_ids[ui_nand_ids].erasesize; + pIdentify->qe_opt = nvt_nand_ids[ui_nand_ids].qe_opt; + pIdentify->plane_opt= nvt_nand_ids[ui_nand_ids].plane_opt; + nand_ids_found = TRUE; + break; + } + } + return nand_ids_found; +} diff --git a/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c b/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c new file mode 100755 index 000000000..669f40347 --- /dev/null +++ b/loader/LibExt/LIBExt_src/Ctrl_Flow/spi_nor_ids.c @@ -0,0 +1,38 @@ +/* + * nand_ids.c + * + * nand id table + * + * Copyright (c) 2018 Novatek, ALL Rights Reserve + */ +#include "main.h" +#include "nor.h" +#include "constant.h" +#include "compiler.h" +#include "fuart.h" + +#define _THUMB2 __attribute__((target("thumb2"))) + + +NOR_FLASH_DEV nvt_nor_ids[] = { + // manufactor ID device id capacity id, dual read quad type flash size + SPI_ID_NOR(0xEF, 0x40, 0x18, TRUE, SPI_QUAD_TYPE2, (16<<20)), +}; + +_THUMB2 BOOL nor_identify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + BOOL nor_ids_found = FALSE; + UINT32 ui_nor_ids; + for (ui_nor_ids = 0; ui_nor_ids < (sizeof(nvt_nor_ids) / sizeof(NOR_FLASH_DEV)); ui_nor_ids++) { + if (uiMfgID == nvt_nor_ids[ui_nor_ids].mfr_id && uiTypeID == nvt_nor_ids[ui_nor_ids].dev_id && uiCapacityID == nvt_nor_ids[ui_nor_ids].capacity_id) { + // For SPI Nor flash only + pIdentify->bDualRead = nvt_nor_ids[ui_nor_ids].bDualRead; + pIdentify->uiQuadReadType = nvt_nor_ids[ui_nor_ids].uiQuadReadType; + pIdentify->uiFlashSize = nvt_nor_ids[ui_nor_ids].uiFlashSize; + nor_ids_found = TRUE; + break; + } + } + + return nor_ids_found; +} diff --git a/loader/LibExt/Makefile b/loader/LibExt/Makefile new file mode 100755 index 000000000..c37cab5be --- /dev/null +++ b/loader/LibExt/Makefile @@ -0,0 +1,62 @@ +include ../MakeCommon/MakeOption.txt + +ifeq "$(shell uname)" "Linux" +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name 'Makefile'))) +else +MAKEFILE_SEARCH := $(sort $(dir $(shell find . -name \'Makefile\'))) +endif +mk_all := $(filter-out ./, $(MAKEFILE_SEARCH)) + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all $(mk_all) clean rebuild debug release dep + +all: + @make dep + @make debug + @make release +else +.PHONY: all $(mk_all) clean rebuild debug release + +all: rm_log $(mk_all) +endif + +$(mk_all): + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f log*.txt +endif + +PRJ_NAME_ALL = $(shell find -name 'Makefile' -not -path "./Makefile" -print | xargs grep "PRJ_NAME" | sed 's/[[:digit:][:alpha:][:punct:]]*:PRJ_NAME[ ]*=[ ]*//g') +LIB_R = $(addprefix "../ARC/Lib/Release/", $(addsuffix ".a", $(PRJ_NAME_ALL))) +LIB_D = $(addprefix "../ARC/Lib/Debug/", $(addsuffix "_D.a", $(PRJ_NAME_ALL))) + +clean: + @-echo Clean LibExt ... \ + && find ./ -type d -name '*_Data' | xargs rm -rf --no-preserve-root $(LIB_D) $(LIB_R) log*.txt lint*.txt + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: rm_log $(mk_all) +else +rebuild: rm_log $(mk_all) +endif + +debug: rm_log $(mk_all) + +release: rm_log $(mk_all) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(mk_all) + +lintclean: + @-echo Clean LibExt lint data ... \ + && find ./ -type d -name 'CheckData' | xargs rm -rf --no-preserve-root lint*.txt \ No newline at end of file diff --git a/loader/MakeCommon/InputSource.txt b/loader/MakeCommon/InputSource.txt new file mode 100755 index 000000000..631265678 --- /dev/null +++ b/loader/MakeCommon/InputSource.txt @@ -0,0 +1,177 @@ +#---------------------------------------------------------------------- +# get the source full path, convert upper case extension to lower case +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +SRC := $(addprefix $(shell pwd)/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell pwd)/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell pwd)/, $(CPP_SRC:.CPP=.cpp)) +else +SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(SRC:.C=.c)) +ASM := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(ASM:.s=.S)) +CPP_SRC := $(addprefix $(shell cygpath --mixed $(shell pwd))/, $(CPP_SRC:.CPP=.cpp)) +endif + +#---------------------------------------------------------------------- +# set the basic include directories +#---------------------------------------------------------------------- +# Get working directory +MYPWD := $(shell pwd) +ALG_PATH := $(findstring /Alg/, $(MYPWD)) +APP_PATH := $(findstring /App/, $(MYPWD)) +APPEXT_PATH := $(findstring /AppExt/, $(MYPWD)) +LIB_PATH := $(findstring /Lib/, $(MYPWD)) +LIBEXT_PATH := $(findstring /LibExt/, $(MYPWD)) +DRV_PATH := $(findstring /Drv/, $(MYPWD)) +DRVEXT_PATH := $(findstring /DrvExt/, $(MYPWD)) +COM_PATH := $(findstring /Common/, $(MYPWD)) +UTIL_PATH := $(findstring /Common/Common_src/Utility, $(MYPWD)) +PRJ_PATH := $(shell find ./ -maxdepth 1 -name MakeConfig.txt) + +BASE_INC_DIR := $(filter %../../Include, $(INC_DIR)) +APPEXT_INC_DIR := -I$(BASE_INC_DIR)/AppExt +APP_INC_DIR := -I$(BASE_INC_DIR)/App +LIBEXT_INC_DIR := -I$(BASE_INC_DIR)/LibExt +LIB_INC_DIR := -I$(BASE_INC_DIR)/Lib +DRVEXT_INC_DIR := -I$(BASE_INC_DIR)/DrvExt +DRV_INC_DIR := -I$(BASE_INC_DIR)/Drv +LIBC_INC_DIR := -I$(BASE_INC_DIR)/Common/LibC + +#BASE_INC_ALG_DIR := $(BASE_INC_DIR)/../Alg/Include +#BASE_INC_PROTECT_DIR := $(subst Include,IncludeProtected,$(BASE_INC_DIR)) + +#change replace /Include/ to /IncludeProtected/ +define protected +$(subst ../../Include/,../../IncludeProtected/,$1) +endef + + +ifeq "$(USE_ECOS_KERNEL)" "ON" +#eCos include path like ThirdParty/eCos/Include ThirdParty/live555/Include +ECOS_INC_DIR := $(addprefix -I,$(addsuffix /include, $(shell find $(BASE_INC_DIR)/../ThirdParty/ -maxdepth 1 -mindepth 1 -type d))) +endif + +ifeq "$(shell uname)" "Linux" +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name '*.h')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name '*.h')))) +else +INC_DIR := $(addprefix -I, $(sort $(dir $(shell find $(INC_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_PROTECT_DIR) -name \'\*\.h\')))) +INC_DIR += $(addprefix -I, $(sort $(dir $(shell find $(BASE_INC_ALG_DIR) -name \'\*\.h\')))) +endif + +# For uITRON (MIPS) platform, we use proprietary standard C library. +# We must filter out proprietary header file if we are in others platform (ARM or eCos...) +# Filter out standard C library header file +# ifeq "$(ARCH)" "ARM" +# INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) +# endif + +ifeq "$(USE_ECOS_KERNEL)" "ON" + INC_DIR := $(filter-out $(LIBC_INC_DIR)/%, $(INC_DIR)) + INC_DIR += $(ECOS_INC_DIR) +endif + +ifeq "$(INCLUDE_RULE)" "ON" + +#---------------------------------------------------------------------- +# Filter out upper layer's include path +#---------------------------------------------------------------------- + + +# /Common can't access /App or /AppExt or /Lib or /LibExt or /Drv or /DrvExt +# except: /Common/Common_src/Utility can access /Drv +ifneq "$(COM_PATH)" "" +ifneq "$(UTIL_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%),$(INC_DIR)) +else +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)% $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%) $(call protected,$(DRVEXT_INC_DIR)%) $(call protected,$(DRV_INC_DIR)%),$(INC_DIR)) +endif +endif + +# /Drv can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected, $(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%),$(INC_DIR)) +endif + +# /DrvExt can't access /App or /AppExt or /Lib or /LibExt +ifneq "$(DRVEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)% $(LIBEXT_INC_DIR)% $(LIB_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%) $(call protected,$(LIBEXT_INC_DIR)%) $(call protected,$(LIB_INC_DIR)%), $(INC_DIR)) +endif + +# /Lib can't access /App or /AppExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +# /LibExt can't access /App or /AppExt +ifneq "$(LIBEXT_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)% $(APP_INC_DIR)%, $(INC_DIR)) +INC_DIR := $(filter-out $(call protected,$(APPEXT_INC_DIR)%) $(call protected,$(APP_INC_DIR)%), $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out under layer's include path +#---------------------------------------------------------------------- + +# /App can't access /Drv +#ifneq "$(APP_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /App can't access /DrvExt or /LibExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /AppExt can't access /Drv +#ifneq "$(APPEXT_PATH)" "" +#INC_DIR := $(filter-out $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +# /Lib can't access /DrvExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Prj can't access /Drv or /DrvExt +#ifneq "$(PRJ_PATH)" "" +#INC_DIR := $(filter-out $(DRVEXT_INC_DIR)% $(DRV_INC_DIR)%, $(INC_DIR)) +#endif + +ifneq "$(UI_STYLE)" "" +ifeq ($(filter $(UI_STYLE), $(UI_STYLE_ALL)),) +$(error add your style into $$UI_STYLE_ALL in MakeConfig.txt) +else +PRJ_FILT_OUT := $(filter-out $(UI_STYLE), $(UI_STYLE_ALL)) +endif +PRJ_FILT_OUT_DIR := $(addsuffix %,$(addprefix -I./SrcCode/UIWnd/, $(subst UI_STYLE_,,$(PRJ_FILT_OUT)))) +#INC_DIR := $(shell echo $(INC_DIR)|tr a-z A-Z) +INC_DIR := $(filter-out $(PRJ_FILT_OUT_DIR) , $(INC_DIR)) +endif + +#---------------------------------------------------------------------- +# Filter out external layer's include path +#---------------------------------------------------------------------- + +# /Drv can't access /DrvExt +ifneq "$(DRV_PATH)" "" +INC_DIR := $(filter-out $(DRVEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /Lib can't access /LibExt +ifneq "$(LIB_PATH)" "" +INC_DIR := $(filter-out $(LIBEXT_INC_DIR)%, $(INC_DIR)) +endif + +# /App can't access /AppExt +ifneq "$(APP_PATH)" "" +INC_DIR := $(filter-out $(APPEXT_INC_DIR)%, $(INC_DIR)) +endif + +endif \ No newline at end of file diff --git a/loader/MakeCommon/MakeCommon.txt b/loader/MakeCommon/MakeCommon.txt new file mode 100755 index 000000000..6b9119ac4 --- /dev/null +++ b/loader/MakeCommon/MakeCommon.txt @@ -0,0 +1,663 @@ +#---------------------------------------------------------------------- +# Get the source full path, include directories +#---------------------------------------------------------------------- +# query SRC, ASM, INC_DIR +include $(MAKE_COMMON_DIR)/InputSource.txt + +#---------------------------------------------------------------------- +# set the basic ASM flags +# PLATFORM_AFLAGS := -march=armv7-a -mcpu=cortex-a9 -mabi=aapcs -msoft-float +# -mfloat-abi=softfp <==> -mfloat-abi=hard +#---------------------------------------------------------------------- +ifeq "$(FPU)" "hard" +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) +else +PLATFORM_AFLAGS := -mcpu=$(CPU) -mfloat-abi=$(FPU) +endif + + + +#---------------------------------------------------------------------- +# set the basic C flags +# Reference +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/ +# http://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Option-Summary.html#Option-Summary +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +# Overall Options +#---------------------------------------------------------------------- +# -c : Compile the source files, but do not link +# -pipe : Use pipes rather than temporary files for communication between the various stages of compilation +PLATFORM_CFLAGS := -c -pipe + +#---------------------------------------------------------------------- +# Machine Dependent Options +#---------------------------------------------------------------------- +# -march=24kec : Generate code that will run on MIPS 24KEc +# -mtune=24kec : Optimize for MIPS 24KEc +# -mdsp : Use revision 1 of the MIPS DSP ASE +# -EL : Generate little-endian code +# -msoft-float : Do not use floating-point coprocessor instructions +# -marm : Tell compiler do not build c code as thumb2 instruction +#---------------------------------------------------------------------- +ifeq "$(USE_NEON)" "on" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=softfp -mfpu=neon-fp-armv8 -ftree-vectorize +else +ifeq "$(FPU)" "hard" +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) -mfpu=neon -ftree-vectorize +else +PLATFORM_CFLAGS += -mcpu=$(CPU) -marm -mno-thumb-interwork -mfloat-abi=$(FPU) +endif +endif +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -mhard-float -mfpu=neon-vfpv4 -mno-thumb-interwork -mno-sched-prolog +# PLATFORM_CFLAGS += -mtune=$(CPU) -march=armv7-a -marm -msoft-float -mno-thumb-interwork -mno-sched-prolog + +#---------------------------------------------------------------------- +# Warning Options +#---------------------------------------------------------------------- +# -Wall : This enables all the warnings about constructions that some users consider questionable, +# and that are easy to avoid (or modify to prevent the warning), even in conjunction with macros. +# NOTE: -Wall turns on the following warning flags: +# -Waddress +# -Warray-bounds (only with -O2) +# -Wc++11-compat +# -Wchar-subscripts +# -Wenum-compare (in C/ObjC; this is on by default in C++) +# -Wimplicit-int (C and Objective-C only) +# -Wimplicit-function-declaration (C and Objective-C only) +# -Wcomment +# -Wformat +# -Wmain (only for C/ObjC and unless -ffreestanding) +# -Wmaybe-uninitialized +# -Wmissing-braces (only for C/ObjC) +# -Wnonnull +# -Wparentheses +# -Wpointer-sign +# -Wreorder +# -Wreturn-type +# -Wsequence-point +# -Wsign-compare (only in C++) +# -Wstrict-aliasing +# -Wstrict-overflow=1 +# -Wswitch +# -Wtrigraphs +# -Wuninitialized +# -Wunknown-pragmas +# -Wunused-function +# -Wunused-label +# -Wunused-value +# -Wunused-variable +# -Wvolatile-register-var +# -Wundef : Warn if an undefined identifier is evaluated in an `#if' directive +# -Wsign-compare : Warn when a comparison between signed and unsigned values could produce an incorrect result when the signed value is converted to unsigned +# -Wno-missing-braces : Trun off "Warn if an aggregate or union initializer is not fully bracketed". For XXX = {0}; statement. +# -Wstrict-prototypes : Warn if a function is declared or defined without specifying the argument types +# -Wimplicit-function-declaration : Warn when a function is used before being declared +# -Wmissing-prototypes : Warn about global funcs without prototypes +# -Wmissing-declarations: Warn about global funcs without previous declarations +# -Werror : Warnning as error +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -Wall -Wundef -Wsign-compare -Wno-missing-braces -Wstrict-prototypes -Wno-unused-const-variable -Wno-misleading-indentation +ifeq "$(OUTPUT_FILE)" "BIN" +else +ifeq "$(INCLUDE_RULE)" "ON" +# PLATFORM_CFLAGS += -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=missing-declarations + PLATFORM_CFLAGS += -Wimplicit-function-declaration -Wmissing-prototypes -Wmissing-declarations +endif +endif + +ifeq "$(shell uname)" "Linux" +PLATFORM_CFLAGS += -Werror +endif + +#---------------------------------------------------------------------- +# C Language Options +#---------------------------------------------------------------------- +# -fno-builtin : Don't recognize built-in functions that do not begin with `__builtin_' as prefix +# -ffreestanding: Assert that compilation takes place in a freestanding environment +#---------------------------------------------------------------------- +# Code Generation Options +#---------------------------------------------------------------------- +# -fno-common : The compiler should place uninitialized global variables in the data section of the object file, rather than generating them as common blocks +# -fshort-wchar : Override the underlying type for `wchar_t' to be `short unsigned int' instead of the default for the target. +#---------------------------------------------------------------------- +# Optimization Options +#---------------------------------------------------------------------- +# -fno-strict-aliasing : Do not warn about code that breaks strict aliasing rules +# -fno-optimize-sibling-calls : Don't optimize sibling and tail recursive calls +# -fno-omit-frame-pointer : Keep the frame pointer in a register for functions that don't need one +#---------------------------------------------------------------------- +PLATFORM_CFLAGS += -fno-builtin -ffreestanding -fno-common -fshort-wchar -fno-strict-aliasing -fno-optimize-sibling-calls -fno-omit-frame-pointer + +# C Language Options for eCos system +ifeq "$(USE_ECOS_KERNEL)" "ON" + PLATFORM_CFLAGS += -D__ECOS +else + PLATFORM_CFLAGS += -nostdinc -D__UITRON +# For make dep + GCCFLAGS +=-D__UITRON +endif + +# Remove -Otime (There is no such option in GCC, GCC default is optimize for time) +# Replace -OSpace (-Os in GCC) +CFLAGS_D := $(filter-out -Otime, $(CFLAGS_D)) +CFLAGS_D := $(CFLAGS_D:-Ospace=-Os) +CFLAGS_R := $(filter-out -Otime, $(CFLAGS_R)) +CFLAGS_R := $(CFLAGS_R:-Ospace=-Os) + +# Slove sub-folder cannot include parent folder header file +INC_DIR += -I$(CURDIR) + +# For Debug target +CFLAGS_D += $(INC_DIR) -g -ggdb -O0 $(PLATFORM_CFLAGS) +ASMFLAGS_D += -g $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# For Release target (use -Os instead of -O2, because loader is size dominant) +CFLAGS_R += $(INC_DIR) -Os $(PLATFORM_CFLAGS) +ASMFLAGS_R += $(INC_DIR) $(PLATFORM_AFLAGS) -D__ASSEMBLY__ + +# Generate debug symbol in release target +ifeq "$(RELEASE_SYMBOL)" "ON" + CFLAGS_R += -g -ggdb + ASMFLAGS_R += -L -g +endif + +# Generate debug callback of entry and exit to functions +ifeq "$(INSTRUMENT_FUNCTION)" "ON" + CFLAGS_R += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_D += -finstrument-functions -finstrument-functions-exclude-file-list=Common_src/LibC,Common_src/Kernel,Common_src/Debug,Common_src/OS,Include/Common/LibC,Include/Common/Kernel,Include/Common/Debug,Include/Common/OS,Drv_src/Driver,Include/Drv/Driver + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=1 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=1 +else + CFLAGS_R += -D_INSTRUMENT_FUNCTION_=0 + CFLAGS_D += -D_INSTRUMENT_FUNCTION_=0 +endif + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Only apply to release target +# Note: -fdata-sections will generate larger code size +#---------------------------------------------------------------------- +ifeq "$(SECTION_BY_FUNC)" "ON" +# CFLAGS_R += -ffunction-sections -fdata-sections + CFLAGS_R += -ffunction-sections +endif + +#---------------------------------------------------------------------- +# Definition for source code check build debug or release +#---------------------------------------------------------------------- +CFLAGS_R += -DNDEBUG +CFLAGS_D += -D_DEBUG + +#---------------------------------------------------------------------- +# FPGA notification for drivers +#---------------------------------------------------------------------- +ifeq "$(EMULATION)" "ON" + ifeq "$(FPGA_EMULATION)" "ON" + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=1 -D_FPGA_PLL_OSC_=$(FPGA_PLL_OSC) + else + CFLAGS_R += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=1 -D_FPGA_EMULATION_=0 + endif +else + CFLAGS_R += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + CFLAGS_D += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 + GCCFLAGS += -D_EMULATION_=0 -D_FPGA_EMULATION_=0 +endif + +#---------------------------------------------------------------------- +# PM demo based on customized building way +#---------------------------------------------------------------------- +ifeq "$(PM_DEMO)" "ON" + CFLAGS_R += -D_PM_DEMO_=1 + CFLAGS_D += -D_PM_DEMO_=1 +else + CFLAGS_R += -D_PM_DEMO_=0 + CFLAGS_D += -D_PM_DEMO_=0 +endif + +#---------------------------------------------------------------------- +# GIC usage ON/OFF +#---------------------------------------------------------------------- +ifeq "$(ARM_GIC_400)" "ON" + CFLAGS_R += -D_ARM_GIC_USAGE_=1 + CFLAGS_D += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=1 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=1 +else + CFLAGS_R += -D_ARM_GIC_USAGE_=0 + CFLAGS_D += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_R += -D_ARM_GIC_USAGE_=0 + ASMFLAGS_D += -D_ARM_GIC_USAGE_=0 +endif + +#---------------------------------------------------------------------- +# Architecture definition +#---------------------------------------------------------------------- +CFLAGS_R += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +CFLAGS_D += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 +GCCFLAGS += -D_ARCH_ARM_=0 -D_ARCH_MIPS_=1 + +ifeq "$(ARCH)" "ARM" + CFLAGS_R += -D_ARCH_=_ARCH_ARM_ + CFLAGS_D += -D_ARCH_=_ARCH_ARM_ + GCCFLAGS += -D_ARCH_=_ARCH_ARM_ +else ifeq "$(ARCH)" "MIPS" + CFLAGS_R += -D_ARCH_=_ARCH_MIPS_ + CFLAGS_D += -D_ARCH_=_ARCH_MIPS_ + GCCFLAGS += -D_ARCH_=_ARCH_MIPS_ +endif + +ifeq "$(FPU)" "hard" +ASMFLAGS_D += -D_NEON_ON_=1 +ASMFLAGS_R += -D_NEON_ON_=1 +else +ASMFLAGS_D += -D_NEON_ON_=0 +ASMFLAGS_R += -D_NEON_ON_=0 +endif + +#---------------------------------------------------------------------- +# ROM Public API usage +#---------------------------------------------------------------------- +ifeq "$(ROM_PUBLIC_API)" "ON" + CFLAGS_R += -D_ROM_PUBLIC_API_=1 + CFLAGS_D += -D_ROM_PUBLIC_API_=1 + ASMFLAGS_R+= -D_ROM_PUBLIC_API_=1 + ASMFLAGS_D+= -D_ROM_PUBLIC_API_=1 +else + CFLAGS_R += -D_ROM_PUBLIC_API_=0 + CFLAGS_D += -D_ROM_PUBLIC_API_=0 + ASMFLAGS_R+= -D_ROM_PUBLIC_API_=0 + ASMFLAGS_D+= -D_ROM_PUBLIC_API_=0 +endif + + +#---------------------------------------------------------------------- +# 2nd checksum usage +#---------------------------------------------------------------------- +ifeq "$(PROCESS_2ND_CHECKSUM)" "ON" + CFLAGS_R += -D_PROCESS_2ND_CHECKSUM_=1 + CFLAGS_D += -D_PROCESS_2ND_CHECKSUM_=1 + ASMFLAGS_R+= -D_PROCESS_2ND_CHECKSUM_=1 + ASMFLAGS_D+= -D_PROCESS_2ND_CHECKSUM_=1 +else + CFLAGS_R += -D_PROCESS_2ND_CHECKSUM_=0 + CFLAGS_D += -D_PROCESS_2ND_CHECKSUM_=0 + ASMFLAGS_R+= -D_PROCESS_2ND_CHECKSUM_=0 + ASMFLAGS_D+= -D_PROCESS_2ND_CHECKSUM_=0 +endif + +#---------------------------------------------------------------------- +# Definition from environment +#---------------------------------------------------------------------- +ifeq "$(NMAKE_DEF)" "" +CFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +CFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +CFLAGS_R += $(NMAKE_DEF) +CFLAGS_D += $(NMAKE_DEF) +endif +ifeq "$(NMAKE_DEF_ASM)" "" +ASMFLAGS_R += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +ASMFLAGS_D += -D_EMULATION_ON_CPU2_=0 -D_EMULATION_MULTI_CPU_=0 +else +ASMFLAGS_R += $(NMAKE_DEF_ASM) +ASMFLAGS_D += $(NMAKE_DEF_ASM) +endif +#---------------------------------------------------------------------- +# Set image base directory according to kernel type +# eCos : /ARC +# uITRON : /ARC_eCos +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" + ifeq "$(OUTPUT_FILE)" "LIB" + # This is for library, project's image base directory is $(PRJ_NAME)_Data + # IMG_BASE_DIR looks like ../../ARC/Common (There is backslash succeeding to /ARC) + IMG_BASE_DIR := $(subst /ARC/,/ARC_eCos/,$(IMG_BASE_DIR)) + endif + ifeq "$(OUTPUT_FILE)" "BIN" + # This is for project, library doesn't have this variable + # ARC_BASE_DIR looks like ../../ARC (There is No backslash succeeding to /ARC) + ARC_BASE_DIR := $(subst /ARC,/ARC_eCos,$(ARC_BASE_DIR)) + endif + KERNEL_STR := eCos +else + KERNEL_STR := uITRON +endif + +#---------------------------------------------------------------------- +# Set branched project name +#---------------------------------------------------------------------- +ifneq "$(_BRANCH_PROJECT_)" "" + CFLAGS_R += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) + CFLAGS_D += -D_PROJECT_CODE_=$(_BRANCH_PROJECT_) +endif + +#---------------------------------------------------------------------- +# Set the directory for debug/release objects and images here +#---------------------------------------------------------------------- +OBJ_DEBUG = $(PRJ_NAME)_Data/Debug/ObjectCode +OBJ_RELEASE = $(PRJ_NAME)_Data/Release/ObjectCode +IMG_DEBUG = $(IMG_BASE_DIR)/Debug +IMG_RELEASE = $(IMG_BASE_DIR)/Release + + +#---------------------------------------------------------------------- +# Filter the GCC Command Options for debug/release mode +#---------------------------------------------------------------------- +FILTER_GCC_D = $(foreach v, $(CFLAGS_D), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_D = $(filter-out $(INC_DIR), $(FILTER_GCC_D)) +FILTER_GCC_R = $(foreach v, $(CFLAGS_R), $(if $(findstring -D, $(v)), , $(v))) +GCC_OPT_R = $(filter-out $(INC_DIR), $(FILTER_GCC_R)) + + +#---------------------------------------------------------------------- +# Set the make outputs +#---------------------------------------------------------------------- +SRC_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_D := $(addprefix $(OBJ_DEBUG)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_D := $(ASM_OBJ_D) $(SRC_OBJ_D) $(CPP_OBJ_D) +DEPFILE_D := $(subst .o,.d,$(ALL_OBJ_D)) + +SRC_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(ASM:.S=.o))) +CPP_OBJ_R := $(addprefix $(OBJ_RELEASE)/, $(notdir $(CPP_SRC:.cpp=.o))) +ALL_OBJ_R := $(ASM_OBJ_R) $(SRC_OBJ_R) $(CPP_OBJ_R) +DEPFILE_R := $(subst .o,.d,$(ALL_OBJ_R)) + +ifeq "$(ISOLATE_DEP)" "ON" + ALL_DEP := $(DEPFILE_D) $(DEPFILE_R) +endif + +LINT_ROOTDIR = $(PRJ_NAME)_Lint +LINT_DIR = $(PRJ_NAME)_Lint/LintData +LINT_FILE := $(addprefix $(LINT_DIR)/, $(notdir $(SRC:.c=.lob))) + +#---------------------------------------------------------------------- +# For dependency +#---------------------------------------------------------------------- +GCCFLAGS += $(INC_DIR) -c -w + +#---------------------------------------------------------------------- +# For coding rule +#---------------------------------------------------------------------- +PCLINTFLAGS = $(PCLINT_PARAMETER) $(C_DEFINE_EXT) $(INC_DIR) -i$(MAKE_COMMON_DIR)/LintRule std.lnt options.lnt $$(lintopt_file) + +#---------------------------------------------------------------------- +# define host environment is linux if we build on linux server +#---------------------------------------------------------------------- +ifeq ($(OS),Linux) +CFLAGS_R += -D_HOST_ENV_LINUX_ +CFLAGS_D += -D_HOST_ENV_LINUX_ +GCCFLAGS += -D_HOST_ENV_LINUX_ +endif + +#---------------------------------------------------------------------- +# CPP FLAGS derived from CFLAGS_R / CFLAGS_D +#---------------------------------------------------------------------- +CPPFLAGS_R = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_R)) +CPPFLAGS_D = $(filter-out -Wstrict-prototypes -Wimplicit-function-declaration -Wmissing-prototypes, $(CFLAGS_D)) + +#---------------------------------------------------------------------- +# Set the make targets +#---------------------------------------------------------------------- +build_all: rm_log build_D build_R + +make_debug_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_D))) debug target ... \ + && mkdir -p $(IMG_DEBUG) $(OBJ_DEBUG) + +make_release_begin: + @-echo \ + && echo Checking $(KERNEL_STR) - $(basename $(notdir $(IMAGE_R))) release target ... \ + && mkdir -p $(IMG_RELEASE) $(OBJ_RELEASE) + +make_dep_begin: + @-echo Checking $(basename $(notdir $(IMAGE_R))) dependency ... \ + && mkdir -p $(OBJ_DEBUG) $(OBJ_RELEASE) + +make_lint_begin: + @-echo Checking \"$(basename $(notdir $(IMAGE_R)))\" with coding rules ... \ + && mkdir -p $(LINT_DIR) + +make_option_begin: + @-echo [GCC Command Options - Release] + @-echo $(GCC_OPT_R) + @-echo + @-echo [GCC Command Options - Debug ] + @-echo $(GCC_OPT_D) + +#---------------------------------------------------------------------- +# Compile rule functions +#---------------------------------------------------------------------- +BUILD_DATE = 20`date +'%y%m%d'` +ifeq "$(ISOLATE_DEP)" "ON" + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @echo Compiling $(notdir $2)\ + && $(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CC) $(PLATFORM_AFLAGS) -c $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @echo Compiling $(notdir $2) \ + && $(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +else + + # $(call compile_rule,object,source,cflags) + define compile_rule + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_rule_asm,object,source,asmflags) + define compile_rule_asm + $1: $2 + @-$(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CC) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + + # $(call compile_cpp,object,source,cflags) + define compile_rule_cpp + $1: $2 + @-$(CXX) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && echo Compiling $(notdir $2) + @$(CXX) -D__section_name__=$(PRJ_NAME) -D__module_name__=$(PRJ_NAME)_LIBRARY_VERSION_INFO -D__SHORT_FILE__=$(basename $(notdir $2)) -D_BUILD_DATE_=$(BUILD_DATE) $3 -o $1 $2 $$(LOG_OPTION) + + endef + +endif + +# $(call get_obj,obj_dir,source) +get_obj = $(addprefix $1/, $(subst .c,.o,$(notdir $2))) + +# $(call get_obj_asm,obj_dir,source) +get_obj_asm = $(addprefix $1/, $(subst .S,.o,$(notdir $2))) + +# $(call get_obj,obj_dir,source) +get_obj_cpp = $(addprefix $1/, $(subst .cpp,.o,$(notdir $2))) + +# $(call compile_all,obj_dir,cflags) +define compile_all +$(foreach i, $(SRC), \ + $(call compile_rule,$(call get_obj,$1,$i),$i,$2)) +endef + +# $(call compile_all_asm,obj_dir,asmflags) +define compile_all_asm +$(foreach i, $(ASM), \ + $(call compile_rule_asm,$(call get_obj_asm,$1,$i),$i,$2)) +endef + +# $(call compile_all_cpp,obj_dir,cflags) +define compile_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call compile_rule_cpp,$(call get_obj_cpp,$1,$i),$i,$2)) +endef + +#----------------------------------------------------------------- +# Dependency rule functions +#----------------------------------------------------------------- +# $(call depend_rule,depend,source) +define depend_rule +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +define depend_rule_asm +$1: $2 + @echo Depending $(notdir $2) \ + && $(GCC) -MM -MF $(basename $1).d -MP -MT $1 $(GCCFLAGS) $2 \ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) \ + && rm -f $(basename $1).o + +endef + +define depend_rule_cpp +$1: $2 + @echo Depending $(notdir $2) \ + && $(CXX) -MM -MF $1 -MP -MT $(basename $1).o $(GCCFLAGS) $2\ + && sed -e 's/_Data\/Debug\//_Data\/Release\//1' $1 > $(subst _Data/Debug/,_Data/Release/,$1) + +endef + +# $(call get_dep,dep_dir,source) +get_dep = $(addprefix $1/, $(subst .c,.d,$(notdir $2))) + +# $(call get_dep_asm,dep_dir,source) +get_dep_asm = $(addprefix $1/, $(subst .S,.d,$(notdir $2))) + +# $(call get_dep_cpp,dep_dir,source) +get_dep_cpp = $(addprefix $1/, $(subst .cpp,.d,$(notdir $2))) + +define depend_all +$(foreach i, $(SRC), \ + $(call depend_rule,$(call get_dep,$1,$i),$i)) +endef + +# $(call dep_all_asm,dep_dir) +define depend_all_asm +$(foreach i, $(ASM), \ + $(call depend_rule_asm,$(call get_dep_asm,$1,$i),$i)) +endef + +define depend_all_cpp +$(foreach i, $(CPP_SRC), \ + $(call depend_rule_cpp,$(call get_dep_cpp,$1,$i),$i)) +endef + +#---------------------------------------------------------------------- +# LINT rule functions +#---------------------------------------------------------------------- +# $(call get_lint,lint_dir,source) +get_lint = $(addprefix $1/, $(subst .c,.lob,$(notdir $2))) + +# $(call lint_rule,output,source) +define lint_rule +$1: $2 + @-echo Review $(notdir $2) \ + && $(LT) $(PCLINTFLAGS) -u -zero -oo[$1] $2 >> $$(lint_file) + +endef + +# && $(LT) $(PCLINTFLAGS) $2 >> $$(lint_file) + +define lint_all +$1: +$(foreach i, $(SRC), \ + $(call lint_rule,$(call get_lint,$1,$i),$i)) + @-echo Review \(Internal Relation\) \ + && $(LT) $(PCLINTFLAGS) $(LINT_DIR)/"*.lob" >> $$(lint_file) + -rm -rf --no-preserve-root $(LINT_ROOTDIR) + +endef + +#---------------------------------------------------------------------- +# Goals +#---------------------------------------------------------------------- +ifeq "$(ISOLATE_DEP)" "ON" + + ifeq "$(MAKECMDGOALS)" "dep" + $(eval $(call depend_all,$(OBJ_RELEASE))) + $(eval $(call depend_all_asm,$(OBJ_RELEASE))) + $(eval $(call depend_all_cpp,$(OBJ_RELEASE))) + $(eval $(call depend_all,$(OBJ_DEBUG))) + $(eval $(call depend_all_asm,$(OBJ_DEBUG))) + $(eval $(call depend_all_cpp,$(OBJ_DEBUG))) + endif + + ifeq "$(MAKECMDGOALS)" "" + .DEFAULT_GOAL := all + endif + +else + + ifeq "$(MAKECMDGOALS)" "" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + + ifeq "$(MAKECMDGOALS)" "rebuild" + -include $(DEPFILE_D) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) + endif + +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) + -include $(DEPFILE_D) + $(eval $(call compile_all,$(OBJ_DEBUG),$(CFLAGS_D))) + $(eval $(call compile_all_asm,$(OBJ_DEBUG),$(ASMFLAGS_D))) + $(eval $(call compile_all_cpp,$(OBJ_DEBUG),$(CPPFLAGS_D))) +endif + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) + -include $(DEPFILE_R) + $(eval $(call compile_all,$(OBJ_RELEASE),$(CFLAGS_R))) + $(eval $(call compile_all_asm,$(OBJ_RELEASE),$(ASMFLAGS_R))) + $(eval $(call compile_all_cpp,$(OBJ_RELEASE),$(CPPFLAGS_R))) +endif + +ifeq "$(MAKECMDGOALS)" "lint" + $(eval $(call lint_all,$(LINT_DIR))) +endif diff --git a/loader/MakeCommon/MakeOption.txt b/loader/MakeCommon/MakeOption.txt new file mode 100755 index 000000000..db6885f74 --- /dev/null +++ b/loader/MakeCommon/MakeOption.txt @@ -0,0 +1,298 @@ +ifeq "$(OPTION_LOADED)" "" + +#---------------------------------------------------------------------- +# Set option file loaded +#---------------------------------------------------------------------- +export OPTION_LOADED := TRUE + +#---------------------------------------------------------------------- +# Set the target CPU architecture +# +# ARM : ARM CPU +# MIPS : MIPS CPU (24KEc) +#---------------------------------------------------------------------- +export ARCH := ARM +#export ARCH := MIPS + +#---------------------------------------------------------------------- +# Set the toolchain +# +# ARM : ARM ADS, RealView +# GNU : GNU C, ASM and linker +#---------------------------------------------------------------------- +#export TOOLCHAIN := ARM +export TOOLCHAIN := GNU + +#---------------------------------------------------------------------- +# Set the floating point +# +# SW/HW : soft or hard float point unit +#---------------------------------------------------------------------- +#export FPU := hard +export FPU := soft + +#---------------------------------------------------------------------- +# Set the CPU type +# +# cortex-a9 or a53 +#---------------------------------------------------------------------- +export CPU := cortex-a9 +#export CPU := cortex-a53 + + +#---------------------------------------------------------------------- +# Set branched project code +# +# The project code must be 4 characters, please refer to +# http://mynvt.novatek.com.tw/deptsites/IM/Shared%20Documents/VersionControl.doc +# for more detailed information. +# Leaves this variable empty if not branched yet. +#---------------------------------------------------------------------- +export _BRANCH_PROJECT_ := + +#---------------------------------------------------------------------- +# PClint parameters +#---------------------------------------------------------------------- +export PCLINT_PARAMETER := -b -v + +#---------------------------------------------------------------------- +# Set log file option +# +# ON : Save warning/error message to log files (Win32 Default) +# OFF : Just output warning/error message to stdout (Linux Default) +#---------------------------------------------------------------------- +ifeq "$(shell uname)" "Linux" +export LOG_ERR := OFF +else +export LOG_ERR := ON +endif + +#---------------------------------------------------------------------- +# Set clean log file option +# +# ON : Clean log files before make +# OFF : Don't clean log files before make +# (You should execute "make clean" to clean the log files) +#---------------------------------------------------------------------- +export CLEAN_LOG := ON +#export CLEAN_LOG := OFF + +#---------------------------------------------------------------------- +# Keep going when encounter error or not +# +# ON : Make will keep going when encounter error +# OFF : Make will stop when encounter error +#---------------------------------------------------------------------- +#export KEEP_GOING := ON +export KEEP_GOING := OFF + +#---------------------------------------------------------------------- +# Isolate creating dependency files process +# +# ON : You have to run "make dep" to create dependency files +# OFF : dependency file will be created when making the file +#---------------------------------------------------------------------- +export ISOLATE_DEP := ON +#export ISOLATE_DEP := OFF + +#---------------------------------------------------------------------- +# Generate debug symbol in release target +# Release target won't generate debug symbol by default, if you want to +# generate debug symbol in release target, please turn on this option +# +# ON : Generate debug symbol in release target +# OFF : Don't generate debug symbol in release target (default value) +#---------------------------------------------------------------------- +#export RELEASE_SYMBOL := ON +export RELEASE_SYMBOL := OFF + +#---------------------------------------------------------------------- +# Generate debug callback of entry and exit to functions +# Only support on MIPS (This is GCC Extension) +# Reference: http://blog.linux.org.tw/~jserv/archives/001870.html +# +# ON : Generate debug callback +# OFF : Don't generate debug callback (default value) +#---------------------------------------------------------------------- +#export INSTRUMENT_FUNCTION := ON +export INSTRUMENT_FUNCTION := OFF + +#---------------------------------------------------------------------- +# Generate one ELF section for each function +# Compiler will generate one ELF section for one .c file by default. +# If the .c file contains lots of function that are unused, turn on +# this function can reduce code size. +# (Linker will remove unused section by default) +# Valid only in release target +# +# ON : One ELF section for each function +# OFF : One ELF section for each .c file (default value of ADS/GNU C compiler) +#---------------------------------------------------------------------- +export SECTION_BY_FUNC := ON +#export SECTION_BY_FUNC := OFF + +#---------------------------------------------------------------------- +# Copy bin file to storage after bin file is created +# You have to set an environment variable named "NVT_STG_PATH" (without +# quote) to work with this function. +# Example: set "NVT_STG_PATH" to "H:/" (without quote). +# +# ON : Copy bin file to storage after bin file is created +# OFF : Don't copy bin file to storage after bin file is created +#---------------------------------------------------------------------- +export COPY_BIN_2_STG := ON +#export COPY_BIN_2_STG := OFF + +#---------------------------------------------------------------------- +# Select emulation or design-in (Release code) environment +# +# ON : Emulation environment +# OFF : Design-in environment +#---------------------------------------------------------------------- +#export EMULATION := ON +export EMULATION := OFF + +#---------------------------------------------------------------------- +# Select FPGA or Realchip platform for emulation. +# Valid only when EMULATION is ON +# +# ON : FPGA platform +# OFF : Realchip platform +#---------------------------------------------------------------------- +#export FPGA_EMULATION := ON +export FPGA_EMULATION := OFF + +#---------------------------------------------------------------------- +# Set PLL OSC frequency for FPGA EMULATION +# Valid only when FPGA_EMULATION is ON +# +# For example, you should set it to 27000000 if your FPGA is connected +# with a 27 MHz OSC. +#---------------------------------------------------------------------- +export FPGA_PLL_OSC := 24000000 + +#---------------------------------------------------------------------- +# Set INCLUDE RULE +# +# ON : Enable include rule checking of platform +# OFF : Disable include rule checking of platform +#---------------------------------------------------------------------- +export INCLUDE_RULE := ON +#export INCLUDE_RULE := OFF + +#---------------------------------------------------------------------- +# Use eCos kernel or uITRON kernel +# +# ON : Use eCos kernel and light weight uITRON kernel compatible wrapper +# OFF : Use light weight uITRON kernel +#---------------------------------------------------------------------- +#export USE_ECOS_KERNEL := ON +export USE_ECOS_KERNEL := OFF + +#---------------------------------------------------------------------- +# PM demo based on customized building way +# +# ON : compile rule depends on _PM_DEMO_ that is informal way. +# OFF : formal way to build code +#---------------------------------------------------------------------- +#export PM_DEMO := ON +export PM_DEMO := OFF + +#---------------------------------------------------------------------- +# Set the dump encrypt binary tool +# +# ARCH := ARM 'Use ARMv4 as target +# ARCH := MIPS 'Use MIPS24Ke as target +#---------------------------------------------------------------------- +export ENCRYPT_DUMP := ON +#export ENCRYPT_DUMP := OFF + +#---------------------------------------------------------------------- +# Use ARM GIC as interrupt controller +# +# ON : Use GIC +# OFF : Use Lagacy interrupt as interrupt controller +#---------------------------------------------------------------------- +export ARM_GIC_400 := ON +#export ARM_GIC_400 := OFF + +#---------------------------------------------------------------------- +# Use ROM public API +# +# ON : Use ROM LZMA etc public API +# OFF : Not use ROM LZMA etc public API +#---------------------------------------------------------------------- +#export ROM_PUBLIC_API := OFF +export ROM_PUBLIC_API := ON + +#---------------------------------------------------------------------- +# Enable 2nd checksum check +# +# ON : After lz uncompress, processing checksum first before jump to +# OFF : Not use checksum. +#---------------------------------------------------------------------- +#export PROCESS_2ND_CHECKSUM := ON +export PROCESS_2ND_CHECKSUM := OFF + +#---------------------------------------------------------------------- +# Set the parameters of GNU toolchain +#---------------------------------------------------------------------- +ifeq "$(TOOLCHAIN)" "GNU" +ifeq "$(shell uname)" "Linux" + #CROSS_COMPILE := /opt/arm/gcc-linaro-arm-none-eabi-4.9-2014.09_linux/bin/arm-none-eabi- + CROSS_COMPILE := /opt/gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi/bin/arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = +else + CROSS_COMPILE := arm-eabi- + TOOLS_DIR = ../../Tools/Bin + TOOLS_SUFFIX = .exe +endif + export CC = $(CROSS_COMPILE)gcc + export AS = $(CROSS_COMPILE)as + export LD = $(CROSS_COMPILE)ld + export AR = $(CROSS_COMPILE)ar + export OBJDUMP = $(CROSS_COMPILE)objdump + export FE = $(CROSS_COMPILE)objcopy + export NM = $(CROSS_COMPILE)nm + export LT = "C:/lint/lint-nt.exe" + export GCC = $(CROSS_COMPILE)gcc + export CXX = $(CROSS_COMPILE)g++ + export EBIN = $(TOOLS_DIR)/encrypt_bin$(TOOLS_SUFFIX) + export BFC = $(TOOLS_DIR)/bfc$(TOOLS_SUFFIX) + export LDNVT = $(TOOLS_DIR)/nvt-ld-op$(TOOLS_SUFFIX) + export EBIN = $(TOOLS_DIR)/encrypt_boot_dump$(TOOLS_SUFFIX) + export CFGRAM = $(TOOLS_DIR)/Configram560$(TOOLS_SUFFIX) + export ARMINC_DIR := +endif + + +#---------------------------------------------------------------------- +# Set make flags +# +# Note: Don't modify this if you didn't add new option +#---------------------------------------------------------------------- +# Slient mode +MAKEFLAGS := s + +# Keep going or not +ifeq "$(KEEP_GOING)" "ON" + MAKEFLAGS := $(MAKEFLAGS)k +endif + +#---------------------------------------------------------------------- +# OS Type and Number of CPUs +#---------------------------------------------------------------------- +NPROCS=1 +export OS:=$(shell uname -s) + +ifeq ($(OS),Linux) + NPROCS:=$(shell grep -c ^processor /proc/cpuinfo) +endif +ifeq ($(findstring CYGWIN_NT,$(OS)),CYGWIN_NT) + NPROCS:=$(NUMBER_OF_PROCESSORS) +endif + +export JOB_FLAGS:= -j$(NPROCS) + +endif diff --git a/loader/MakeCommon/Makefile b/loader/MakeCommon/Makefile new file mode 100755 index 000000000..83ea369cf --- /dev/null +++ b/loader/MakeCommon/Makefile @@ -0,0 +1,126 @@ +include MakeOption.txt + +module_Common := $(dir $(wildcard ../Common/Makefile)) +module_Drv := $(dir $(wildcard ../Drv/Makefile)) +module_DrvExt := $(dir $(wildcard ../DrvExt/Makefile)) +module_Lib := $(dir $(wildcard ../Lib/Makefile)) +module_LibExt := $(dir $(wildcard ../LibExt/Makefile)) +module_App := $(dir $(wildcard ../App/Makefile)) +module_AppExt := $(dir $(wildcard ../AppExt/Makefile)) +module_Alg := $(dir $(wildcard ../Alg/Makefile)) + +-include ../Project/ProjectConfig.txt + +ifneq "$(ACTIVE_PROJECT)" "" +module_Prj := ../Project/$(ACTIVE_PROJECT)/ +else +# Find the first folder in ../Project/ that contains "Makefile" +ifeq "$(shell uname)" "Linux" +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name 'Makefile')))) +else +module_Prj := $(dir $(firstword $(sort $(shell find ../Project -name \'Makefile\')))) +endif +endif +test_if_unix_file_fmt = $(shell cd $(1); ret=`if [ "$(OS)" == "Linux" ]; then tools/recursive_dir -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; else tools/recursive_dir.exe -t . --exclude-ext .o .a .bin .axf .7z --exclude-dir .svn .git; fi`; echo "$$ret";) + +module_all := \ + $(module_Common) \ + $(module_Drv) \ + $(module_DrvExt) \ + $(module_Lib) \ + $(module_LibExt) \ + $(module_App) \ + $(module_AppExt) \ + $(module_Alg) + +ifeq "$(LOG_ERR)" "ON" +define copy_log + @-cp \ + $(module_Common)log*.txt \ + $(module_Drv)log*.txt \ + $(module_DrvExt)log*.txt \ + $(module_Lib)log*.txt \ + $(module_LibExt)log*.txt \ + $(module_App)log*.txt \ + $(module_AppExt)log*.txt \ + $(module_Alg)log*.txt \ + $(module_Prj)log*.txt \ + . +endef +else +define copy_log +endef +endif + +ifeq "$(ISOLATE_DEP)" "ON" +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release dep + +all: rm_log + @make dep + @make debug + @make release + $(call copy_log) +else +.PHONY: all rm_log $(module_all) $(module_Prj) clean rebuild debug release + +all: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +$(module_all): +ifeq ($(OS),Linux) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) +else + @$(MAKE) --directory=$@ $(MAKECMDGOALS) $(JOB_FLAGS) +endif + +$(module_Prj):$(module_all) + @$(MAKE) --directory=$@ $(MAKECMDGOALS) + +rm_log: + @-rm -f log*.txt + +clean: rm_log $(module_all) $(module_Prj) + +ifeq "$(ISOLATE_DEP)" "ON" +rebuild: + @make clean + @make dep + @make debug + @make release + $(call copy_log) + +dep: $(module_all) $(module_Prj) +else +rebuild: rm_log $(module_all) $(module_Prj) + $(call copy_log) +endif + +debug: rm_log $(module_Prj) + $(call copy_log) + +release: rm_log $(module_Prj) + $(call copy_log) + +rm_chk_log: + @-rm -f chk*.txt + +chk: rm_chk_log $(module_all) $(module_Prj) + +chkclean: $(module_all) $(module_Prj) + +rm_lint_log: + @-rm -f lint*.txt + +lint: rm_lint_log $(module_all) $(module_Prj) + +lintclean: $(module_all) $(module_Prj) + +chk_unix: + @result="$(call test_if_unix_file_fmt, ../)"; if [ ! -z "$$result" ]; then \ + echo -e "\e[1;31mUNIX file format check failed:\e[0m" >&2; \ + for n in $$result; do \ + echo -e "\t$$n" >&2; \ + done; \ + exit 1; \ + fi \ No newline at end of file diff --git a/loader/MakeCommon/OutputImg.txt b/loader/MakeCommon/OutputImg.txt new file mode 100755 index 000000000..b5bd4bbf8 --- /dev/null +++ b/loader/MakeCommon/OutputImg.txt @@ -0,0 +1,556 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = BIN + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +include $(MAKE_COMMON_DIR)/MakeOption.txt +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# CHIPCFG parameters +#---------------------------------------------------------------------- +ifeq "$(CHIPCFG)" "" + CHIPCFG := CHIPCFG +endif + +#---------------------------------------------------------------------- +# get force link ThirdParty symbols for both debug and release +#---------------------------------------------------------------------- +ifeq "$(USE_ECOS_KERNEL)" "ON" +rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d)) +LIB_ECOS_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl +LIB_ECOS_SELECT_RTK_WIFI_DIR = $(ROOT_DIR)/ThirdParty/devs_eCos-rtl$(WIFIMDL)es +LIB_ECOS_BASE_DIR = $(ROOT_DIR)/ThirdParty +LIB_ECOS_TMP = $(call rwildcard,$(LIB_ECOS_BASE_DIR)/,*.a) +LIB_ECOS_WO_RTK_WIFI_LIB = $(filter-out $(LIB_ECOS_RTK_WIFI_DIR)%, $(LIB_ECOS_TMP)) +LIB_ECOS_RTK_WIFI_LIB = $(call rwildcard,$(LIB_ECOS_SELECT_RTK_WIFI_DIR)/,*.a) +LIB_ECOS = $(LIB_ECOS_WO_RTK_WIFI_LIB) $(LIB_ECOS_RTK_WIFI_LIB) +#There are two eCos .o not in archive +ALL_OBJ_R += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +ALL_OBJ_D += $(wildcard $(LIB_ECOS_BASE_DIR)/eCos/lib/*.o) +endif + +#---------------------------------------------------------------------- +# get force link IPL symbols for both debug and release +#---------------------------------------------------------------------- +SYMBOL_IPL := IPL_SetDZoomFCB IPL_SetSleepFCB IPL_SetWakeupFCB IPL_GetCapRawFCB IPL_SetPauseDMAFCB IPL_SetResumeDMAFCB IPL_SetImgInOutFCB IPL_SetVAFCB IPL_GetIMEHalIdxFCB IPL_GetIPLInfoFCB IPL_TrigFCB IPL_SetTrigInfoFCB IPL_Stream2PauseFCB IPL_Pause2StreamFCB DCE_D2D_CB IPE_D2D_CB IFE_D2D_CB IFE2_D2D_CB IME_D2D_CB DRE_D2D_CB RHEIME_D2D_IFECB RHEIME_D2D_DCECB RHEIME_D2D_IPECB RHEIME_D2D_IMECB RHEIME_D2D_RHECB IPL_GetCtrlFlowFCB IQUC_InitCtrlItem + +#---------------------------------------------------------------------- +# include the libraries +#---------------------------------------------------------------------- +# +# get Debug LIBs +# +LIB_ALG_DIR_D = $(ARC_BASE_DIR)/../Alg/ARC/Debug +LIB_APP_DIR_D = $(ARC_BASE_DIR)/App/Debug +LIB_COM_DIR_D = $(ARC_BASE_DIR)/Common/Debug +LIB_DRV_DIR_D = $(ARC_BASE_DIR)/Drv/Debug +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug + +# get Alg libraries +LIB_ALG_D := $(wildcard $(LIB_ALG_DIR_D)/*.a) + +# get App/AppExt libraries +LIB_APP_D := $(wildcard $(LIB_APP_DIR_D)/*.a) + +# get Common libraries +LIB_COM_D := $(wildcard $(LIB_COM_DIR_D)/*.a) + +# get Drv/DrvExt libraries +LIB_DRV_ALL_D := $(wildcard $(LIB_DRV_DIR_D)/*.a) + +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_DIR_D = $(ARC_BASE_DIR)/Lib/Debug +LIB_STRGEXT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_*.a) +LIB_STRGEXT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGEXT_$(STORAGEEXT)_D.a) +LIB_STRGINT_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_*.a) +LIB_STRGINT_D := $(wildcard $(LIB_LIB_DIR_D)/STRGINT_$(STORAGEINT)_D.a) +LIB_REMAP_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_*.a) +LIB_REMAP_D := $(wildcard $(LIB_LIB_DIR_D)/Remap_$(RESETFLAG)_D.a) +LIB_RESET_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_*.a) +LIB_RESET_D := $(wildcard $(LIB_LIB_DIR_D)/Reset_$(RESETCHIP)_D.a) +LIB_COMMON_ALL_D := $(wildcard $(LIB_LIB_DIR_D)/Common_*.a) +LIB_COMMON_D := $(wildcard $(LIB_LIB_DIR_D)/Common_$(COMMON_LIB)_D.a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_D := $(filter-out $(LIB_PARSER_ALL_D) $(LIB_SLIDE_ALL_D), $(wildcard $(LIB_LIB_DIR_D)/*.a)) + +LIB_LIB_D := $(filter-out $(LIB_STRGEXT_ALL_D) $(LIB_STRGINT_ALL_D) $(LIB_REMAP_ALL_D) $(LIB_RESET_ALL_D) $(LIB_COMMON_ALL_D), $(LIB_LIB_ALL_D)) + +# +# get Release LIBs +# +LIB_LIB_DIR_R = $(ARC_BASE_DIR)/Lib/Release +LIB_STRGEXT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_*.a) +LIB_STRGEXT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGEXT_$(STORAGEEXT).a) +LIB_STRGINT_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_*.a) +LIB_STRGINT_R := $(wildcard $(LIB_LIB_DIR_R)/STRGINT_$(STORAGEINT).a) +LIB_REMAP_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_*.a) +LIB_REMAP_R := $(wildcard $(LIB_LIB_DIR_R)/Remap_$(RESETFLAG).a) +LIB_RESET_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_*.a) +LIB_RESET_R := $(wildcard $(LIB_LIB_DIR_R)/Reset_$(RESETCHIP).a) +LIB_COMMON_ALL_R := $(wildcard $(LIB_LIB_DIR_R)/Common_*.a) +LIB_COMMON_R := $(wildcard $(LIB_LIB_DIR_R)/Common_$(COMMON_LIB).a) +# get LIBs in App (except capture library), AppExt +# and LIB module (except driver and slide-effect libraries) +LIB_LIB_ALL_R := $(filter-out $(LIB_PARSER_ALL_R) $(LIB_SLIDE_ALL_R), $(wildcard $(LIB_LIB_DIR_R)/*.a)) + +#LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_STRGINT_ALL_R) $(LIB_REMAP_ALL_R), $(LIB_LIB_ALL_R)) +LIB_LIB_R := $(filter-out $(LIB_STRGEXT_ALL_R) $(LIB_REMAP_ALL_R) $(LIB_RESET_ALL_R) $(LIB_COMMON_ALL_R), $(LIB_LIB_ALL_R)) + + +# get total libraries for Debug & Release mode; note we cannot get string of LIB_R from LIB_D, or vice versa, +# because we may build Debug and Release output separately, the library of one mode maybe not exist, and cause +# the link problem. So, while adding/deleting libraries, please be patient to do it for Debug and Release mode both. + +LIB_R := \ + $(LIB_LIB_R) \ + $(LIB_STRGEXT_R) \ + $(LIB_REMAP_R) \ + $(LIB_RESET_R) \ + $(LIB_COMMON_R) + +LIB_D := \ + $(LIB_LIB_D) \ + $(LIB_STRGEXT_D) \ + $(LIB_REMAP_D) \ + $(LIB_RESET_D) \ + $(LIB_COMMON_D) + +# If some libraries only available in Release mode, add these libraries in Debug mode too. +LIB_D += $(filter-out $(subst Debug/,Release/,$(LIB_D:_D.a=.a)),$(LIB_R)) + +# Append eCos library to both Debug and Release mode +# (We don't have debug mode's eCos library) +LIB_R += $(LIB_ECOS) +LIB_D += $(LIB_ECOS) + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +# for debug target +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.axf +BIN_D = $(IMG_DEBUG)/$(LDR_NAME).bin +MAP_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.txt +MAP2_D = $(IMG_DEBUG)/$(PRJ_NAME)_ldmap_D.txt +SYM_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.sym +DASM_D = $(IMG_DEBUG)/$(PRJ_NAME)_dasm_D.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_D = $(IMG_DEBUG)/$(BIN_NAME).ext.bin +endif + + +# for release target +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).axf +BIN_R = $(IMG_RELEASE)/$(LDR_NAME).bin +MAP_R = $(IMG_RELEASE)/$(PRJ_NAME).txt +MAP2_R = $(IMG_RELEASE)/$(PRJ_NAME)_ldmap.txt +SYM_R = $(IMG_RELEASE)/$(PRJ_NAME).sym +DASM_R = $(IMG_RELEASE)/$(PRJ_NAME)_dasm.txt +ifeq "$(MODELEXT_BUILT_IN)" "MODELEXT_BUILT_IN_OFF" +MODELEXT_R = $(IMG_RELEASE)/$(BIN_NAME).ext.bin +endif + +#---------------------------------------------------------------------- +# if enable LDS_MAP +#---------------------------------------------------------------------- +ifeq "$(LDS_MAP)" "ON" +LDMAP_D = -Map $(MAP2_D) +LDMAP_R = -Map $(MAP2_R) +endif + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +log_file = log_Prj.txt + +# 0: Standard input (stdin), 1: Standard output (stdout), 2: Standard error (stderr) +# 2>>$(log_file) means redirect standard error to $(log_file) +# 2>>/dev/null means redirect standard error to NULL (Don't display error message) +ifeq "$(LOG_ERR)" "ON" +LOG_OPTION = 2>>$(log_file) +endif + +#---------------------------------------------------------------------- +# set robustness checking log file +#---------------------------------------------------------------------- +lint_file = lint_Prj.txt +lintopt_file = options_Prj.lnt +lintsum_file = lintsum_Prj.txt + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin prepare_log $(IMAGE_D) $(BIN_D) +build_R: make_release_begin prepare_log $(IMAGE_R) $(BIN_R) +build_pipe_D: $(IMAGE_D) $(BIN_D) +build_pipe_R: $(IMAGE_R) $(BIN_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(SRC) $(ASM) $(CPP_SRC) $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +prepare_log: + @$(LOG_OPTION) + +ifeq "$(ARCH)" "ARM" +#arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -print-file-name=libm.a +ifeq "$(FPU)" "hard" +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfpu=neon -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfpu=neon -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +else +libgcc_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mabi=aapcs -mfloat-abi=$(FPU) -print-libgcc-file-name) +libgcc_dir_el = $(shell dirname "$(libgcc_path)") +libstdc_path = $(shell $(CC) -msoft-float -print-file-name=libstdc++.a) +libstdc_dir_el = $(shell dirname "$(libstdc_path)") +libm_path = $(shell $(CC) -march=armv7-a -mcpu=$(CPU) -mfloat-abi=$(FPU) -print-file-name=libm.a) +libm_dir = $(shell dirname "$(libm_path)") +endif +endif + +define append_modelext + echo Append $1 into $4. \ + && $(AR) x $3 $1.o \ + && $(FE) --only-section=modelext_header.$1 -O binary -S -R .comment -R .note $1.o $2/$1.header \ + && cat $2/$1.header >> $4 \ + && $(FE) --only-section=modelext_data.$1 -O binary -S -R .comment -R .note $1.o $2/$1.data \ + && cat $2/$1.data >> $4 +endef + + +#Replace string existing in lds file +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_256" + BOARD_UITRON_ADDR = 0x8000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_512" + BOARD_UITRON_ADDR = 0x10000000 +endif +ifeq "$(PLATFORM_MEM_SIZE)" "SDRAM_SIZE_1024" + BOARD_UITRON_ADDR = 0x20000000 +endif +endif + +LD_REMAP_LIB = Remap_$(RESETFLAG) +LD_DOREMAP = doremap$(RESETFLAG) +LD_RESET_LIB = Reset_$(RESETCHIP) +LD_COMMON_LIB = Common_$(COMMON_LIB) +ifeq "$(BL_COMPRESS)" "ENABLE" +LD_CONFIGRAM = configramLZ +else +LD_CONFIGRAM = configramNM +endif +LD_REPLACE_VAR = sed \ + -e 's/$$LD_REMAP_LIB/$(LD_REMAP_LIB)/g' \ + -e 's/$$LD_DOREMAP/$(LD_DOREMAP)/g' \ + -e 's/$$LD_CONFIGRAM/$(LD_CONFIGRAM)/g' \ + -e 's/$$LD_BASE_ADDR/$(LD_BASE_ADDR)/g' \ + -e 's/$$LD_RESET_LIB/$(LD_RESET_LIB)/g' \ + -e 's/$$LD_COMMON_LIB/$(LD_COMMON_LIB)/g' \ + $(SCATTER) + +#The folder, the working space to fill the full path into lds file +LD_DIR_WORKING_D= $(IMG_BASE_DIR)/Debug/ObjectLds +#Generate the working folder and temp lds file called replace.lds +LD_REPLACE_LDS_D= $(shell mkdir -p $(LD_DIR_WORKING_D)) $(shell $(OBJDUMP) -h $(LIB_D) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_D)/replace.lds) +#The real lds file replaced of using by linker +LD_PATH_LDS_D = $(LD_DIR_WORKING_D)/$(basename $(SCATTER))_D.lds +#Here have some steps as following to get a some files explained below, +#Step 1: Generate temp lds file +#Step 2: export the contents of $(LIB_D) into libs.txt +#Step 3: export the contents of $(ALL_OBJ_D) into objs.txt +#Step 4: Give mips-nvt.exe libs.txt, objs.txt and replace.lds to get ld_ext.d, ld_lib.txt, ld_lib_ban.txt and real lds file for linker. +# Where, +# ld_ext.d is a decency file depends on .o used in lds file +# ld_lib_ban is a list of .a files to ban, because linker should use the .a file after extracting .o. +# real lds file is replaced by full path. +LD_DFILE_D = $(LD_REPLACE_LDS_D) $(shell echo $(LIB_D) > $(LD_DIR_WORKING_D)/libs.txt ) $(shell echo $(ALL_OBJ_D) > $(LD_DIR_WORKING_D)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_D) --lds-dir=$(LD_DIR_WORKING_D) --lds-src=$(LD_DIR_WORKING_D)/replace.lds --libs-src=$(LD_DIR_WORKING_D)/libs.txt --objs-src=$(LD_DIR_WORKING_D)/objs.txt --objs-dir=$(OBJ_DEBUG)) $(LD_DIR_WORKING_D)/ld_ext.d +#Getting the contents of ld_lib.txt +LD_LIB_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib.txt 2>>/dev/null) +#Getting the contents of ld_lib_ban.txt +LD_LIB_BAN_D = $(shell cat $(LD_DIR_WORKING_D)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),debug build_pipe_D)) +include $(LD_DFILE_D) +endif + +$(LD_LIB_D): $(MODELEXT_D) + +#$(MODELEXT_D): $(LIB_MODELEXT_D) +# @echo Creating modelext $@ ... \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_DEBUG),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_DEBUG),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_D): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_D) $(LIB_D) $(LD_LIB_D) $(MODELEXT_D) + $(shell mv *.o $(IMG_BASE_DIR)/Debug/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_D)'> ld_d.tmp + @echo '--start-group $(LD_LIB_D) $(filter-out $(LD_LIB_BAN_D),$(LIB_D)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_D) -L "$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -L"$(libm_dir)" -lstdc++ -lgcc "$(libm_path)" $(LDMAP_D)' >> ld_d.tmp +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_D)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ..." \ + && echo Creating image $@ ... \ + && $(LD) @ld_d.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_D) \ + && $(NM) -n $@ > tmp_sym_d \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_d > $(SYM_D) \ + && rm -f tmp_sym_d \ + && rm -f ld_d.tmp \ + && rm -f tmp_awk1 +endif + + +$(BIN_D): $(IMAGE_D) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_DEBUG)/SPECIAL_RO $(BIN_D) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_D): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_D) > $(DASM_D) +endif + +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_D) tmp 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_D) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ 680 + $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ 680 $(SECURE_BOOT) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH)$(notdir $(BIN_D)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_D)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_D) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +#Please refer LD_DIR_WORKING_D for getting explanation. Ohters are in the same way. +LD_DIR_WORKING_R= $(IMG_BASE_DIR)/Release/ObjectLds +LD_REPLACE_LDS_R= $(shell mkdir -p $(LD_DIR_WORKING_R)) $(shell $(OBJDUMP) -h $(LIB_R) | grep ".version.info" > tmp_awk1) $(shell $(LD_REPLACE_VAR) > $(LD_DIR_WORKING_R)/replace.lds) +LD_PATH_LDS_R = $(LD_DIR_WORKING_R)/$(basename $(SCATTER))_R.lds +LD_DFILE_R = $(LD_REPLACE_LDS_R) $(shell echo $(LIB_R) > $(LD_DIR_WORKING_R)/libs.txt ) $(shell echo $(ALL_OBJ_R) > $(LD_DIR_WORKING_R)/objs.txt ) $(shell $(LDNVT) --lds-dst=$(LD_PATH_LDS_R) --lds-dir=$(LD_DIR_WORKING_R) --lds-src=$(LD_DIR_WORKING_R)/replace.lds --libs-src=$(LD_DIR_WORKING_R)/libs.txt --objs-src=$(LD_DIR_WORKING_R)/objs.txt --objs-dir=$(OBJ_RELEASE)) $(LD_DIR_WORKING_R)/ld_ext.d +LD_LIB_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib.txt 2>>/dev/null) +LD_LIB_BAN_R = $(shell cat $(LD_DIR_WORKING_R)/ld_lib_ban.txt 2>>/dev/null) +tmp_awk2 = $(shell awk -F" " '{print $$2}' tmp_awk1 | awk -F"." '{print $$5}') +tmp_awk3 = $(addsuffix _LIBRARY_VERSION_INFO, $(tmp_awk2)) + +ifeq ($(MAKECMDGOALS), $(filter $(MAKECMDGOALS),release build_pipe_R)) +include $(LD_DFILE_R) +endif + +$(LD_LIB_R): $(MODELEXT_R) + +#$(MODELEXT_R): $(LIB_MODELEXT_R) +# @echo Creating modelext $@ \ +# && rm -f $@ \ +# && $(call append_modelext,modelext_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,bin_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,pinmux_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,intdir_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,emb_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,gpio_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,dram_partition_info,$(OBJ_RELEASE),$<,$@) \ +# && $(call append_modelext,model_cfg,$(OBJ_RELEASE),$<,$@) \ +# && $(EBIN) $(EBIN_METHOD) $@ 0x18 $(EBIN_MNAME) +# @BIN_SIZE=`ls -l $@ | cut -d ' ' -f 5`; \ +# RESIDUAL=$$(($${BIN_SIZE} % 4)); \ +# if [ "$${RESIDUAL}" -ne "0" ]; then \ +# echo "sizeof($@) is not 4-byte aligned"; \ +# exit 1; \ +# fi + +$(IMAGE_R): $(SRC) $(ASM) $(CPP_SRC) $(ALL_OBJ_R) $(LIB_R) $(LD_LIB_R) $(MODELEXT_R) + $(shell mv *.o $(IMG_BASE_DIR)/Release/ObjectCode 2>>/dev/null) + @echo '-o $@ $(ALL_OBJ_R) '> ld_r.tmp + @echo '--start-group $(LD_LIB_R) $(filter-out $(LD_LIB_BAN_R),$(LIB_R)) --end-group -Bstatic -EL --no-wchar-size-warning --gc-sections -T $(LD_PATH_LDS_R) -L"$(libgcc_dir_el)" -L"$(libstdc_dir_el)" -lstdc++ -lgcc "$(libm_path)" $(LDMAP_R)' >> ld_r.tmp + +ifeq "$(SCATTER)" "EmuKit_cpu2.lds" + @echo "Linking CA53_core2...$(LD_PATH_LDS_R)" \ + && echo Creating image $@ ... \ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +else + @echo "Linking ... " \ + && echo Creating image $@ ...\ + && $(LD) @ld_r.tmp $(LOG_OPTION) \ + && $(OBJDUMP) -x -h -t -marm $@ > $(MAP_R) \ + && $(NM) -n $@ > tmp_sym_r \ + && grep -v '\( [aNUw] \)\|\(__crc_\)\|\( \$[adt]\)' tmp_sym_r > $(SYM_R) \ + && rm -f tmp_sym_r \ + && rm -f ld_r.tmp \ + && rm -f tmp_awk1 +endif + +$(BIN_R): $(IMAGE_R) +ifeq "$(MULTI_REGIONS)" "ON" + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ \ + && mv $(IMG_RELEASE)/SPECIAL_RO $(BIN_R) +else + @echo Creating executable $@ ... \ + && $(FE) --gap-fill=0xff -O binary $< $@ +endif + +ifeq "$(LDS_MAP)" "ON" + @echo Generate LDS map file $(MAP2_R): ok +endif +ifeq "$(AXF_DIS)" "ON" + @echo Translate AXF $< to disassembly... \ + && $(OBJDUMP) -D $(IMAGE_R) > $(DASM_R) +endif +ifeq "$(PROCESS_2ND_CHECKSUM)" "ON" + @echo Process compressing file $(@) checksum ...\ + && $(EBIN) $@ $@ $(CHIPID) 10 +endif +ifeq "$(BL_COMPRESS)" "ENABLE" + @echo Compressing file $(@)\ + && $(BFC) c lz $(BIN_R) tmp 1 $(UNCOMPRESSEDPART_SIZE_OFFSET) \ + && cp -f tmp $(BIN_R) \ + && rm -f tmp \ + && echo Encrypt binary file $@ for $(CHIP)... $(CHIP_VER) $(DMA_CLOCK) $(SDRAM_SIZE) $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE)\ + && $(EBIN) $@ $@ $(CHIPID) +ifeq "$(NC520_525_COMBO)" "ON" + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -ini_NC520_525_combo=../../Tools/ConfigRam/$(DDR_INI_STR_NC520_525_COMBO) -dram_ssc=$(DRAM_SSC_PARAM) -52x_combo_528=$(52x_528_COMBO) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +else +ifeq "$(CHIPID)" "560" + $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) -dram_wt=$(DDR_TREFI_PARAM) -dram_2nd_tlb=$(2ND_INI) -dram_2nd_tlb_gpio_no=$(GPIO_NUM) -2nd_ini=../../Tools/ConfigRam/$(DDR_INI_STR2) -odt_select=$(ODT_SELECT) + $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) $(ENCRYPT_DATA) $(SECUREBOOT_MSG) $(AES_KEY_FILE_DIR) $(RSA_PUB_KEY_FILE_DIR) $(RSA_PRV_KEY_FILE_DIR) +endif +endif +# $(CFGRAM) $@ -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI_STR) -chip=660 -package=$(CHIP) -ldver=$(LOADER_VERSION) -gui=$(CONFIG_RAM_GUI_EN) -storage=$(STORAGEINT) +# $(CFGRAM) $@ ../../Tools/ConfigRam/$(CHIP)_$(CHIP_VER)_$(DMA_CLOCK)_$(SDRAM_SIZE)$(DDR_FILE_STR).ini 650 $(LOADER_VERSION) $(CONFIG_RAM_GUI_EN) $(PHY_ANALOG_HV) $(DUTY_CALIBRATION) $(DUTY_CALIBRATION_LOG) $(DUTY_CALIBRATION_TYPE) $(LV1_CLK) +else +# No compress + @echo Encrypt binary file $@ for $(CHIP)...\ + && $(EBIN) $@ $@ $(CHIPID) $(SECURE_BOOT) \ + && $(CFGRAM) $@ -freq=$(DRAM1_CLK) -ini=../../Tools/ConfigRam/$(DDR_INI_STR) -ini2=../../Tools/ConfigRam/$(DDR_INI2_STR) -chip=$(CHIPID) -package=$(CHIP) -ldver=$(LOADER_VERSION) -storage=$(STORAGEINT) -inv_rst=$(DRAM1_RST_PARAM) -dram_number=$(DRAM_NUMBER_DET_PARAM) -dram_ssc=$(DRAM_SSC_PARAM) +endif + +ifeq "$(COPY_BIN_2_STG)" "ON" +ifneq "$(NVT_STG_PATH)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH)$(notdir $(BIN_R)) +endif +ifneq "$(NVT_STG_PATH_MIPS2)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_MIPS2) ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_MIPS2)_FWMIPS2.bin +endif + +ifneq "$(NVT_STG_PATH_CA532)" "" + @-echo Copy \""$(BIN_R)\"" to $(NVT_STG_PATH_CA532)_FWCA532.bin ... \ + && cp -f -v $(BIN_R) $(NVT_STG_PATH_CA532)_FWCA532.bin +endif +endif + +.PHONY: +rm_log: +ifeq "$(CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(IMG_BASE_DIR) $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +#remove unused remap.a for sdk +remap: + rm -v $(filter-out $(LIB_REMAP_D), $(LIB_REMAP_ALL_D)) $(filter-out $(LIB_REMAP_R), $(LIB_REMAP_ALL_R)) + +codesize: $(IMAGE_R) + @$(OBJDUMP) -t $< > $<.sym && \ + $(LDNVT) -j $<.sym && \ + mv RO_RW.txt ZI.txt $(IMG_RELEASE) diff --git a/loader/MakeCommon/OutputLib.txt b/loader/MakeCommon/OutputLib.txt new file mode 100755 index 000000000..cf436efaa --- /dev/null +++ b/loader/MakeCommon/OutputLib.txt @@ -0,0 +1,155 @@ +#---------------------------------------------------------------------- +# Local variable to determine create library or binary file +#---------------------------------------------------------------------- +OUTPUT_FILE = LIB + +#---------------------------------------------------------------------- +# include make common and make option files +#---------------------------------------------------------------------- +ifeq "$(OPTION_LOADED)" "" + include $(MAKE_COMMON_DIR)/MakeOption.txt + LOCAL_CLEAN_LOG = $(CLEAN_LOG) +else + LOCAL_CLEAN_LOG = OFF +endif + +include $(MAKE_COMMON_DIR)/MakeCommon.txt + +#---------------------------------------------------------------------- +# set the make outputs +#---------------------------------------------------------------------- +IMAGE_D = $(IMG_DEBUG)/$(PRJ_NAME)_D.a +IMAGE_R = $(IMG_RELEASE)/$(PRJ_NAME).a + +#---------------------------------------------------------------------- +# set the warning/error log file option +#---------------------------------------------------------------------- +# $(APP_PATH), $(APPEXT_PATH), $(LIB_PATH), $(LIBEXT_PATH) will be assigned value in MakeCommon.txt +ifneq "$(ALG_PATH)" "" + log_file := $(subst MakeCommon,Alg/log_Alg.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Alg/lint_Alg.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Alg.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_Alg.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APP_PATH)" "" + log_file := $(subst MakeCommon,App/log_App.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,App/lint_App.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_App.lnt + lintsum_file := $(subst MakeCommon,App/lintsum_App.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(APPEXT_PATH)" "" + log_file := $(subst MakeCommon,AppExt/log_AppExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,AppExt/lint_AppExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_AppExt.lnt + lintsum_file := $(subst MakeCommon,AppExt/lintsum_AppExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIB_PATH)" "" + log_file := $(subst MakeCommon,Lib/log_Lib.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Lib/lint_Lib.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Lib.lnt + lintsum_file := $(subst MakeCommon,Lib/lintsum_Lib.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(LIBEXT_PATH)" "" + log_file := $(subst MakeCommon,LibExt/log_LibExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,LibExt/lint_LibExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_LibExt.lnt + lintsum_file := $(subst MakeCommon,LibExt/lintsum_LibExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRV_PATH)" "" + log_file := $(subst MakeCommon,Drv/log_Drv.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Drv/lint_Drv.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Drv.lnt + lintsum_file := $(subst MakeCommon,Drv/lintsum_Drv.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(DRVEXT_PATH)" "" + log_file := $(subst MakeCommon,DrvExt/log_DrvExt.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,DrvExt/lint_DrvExt.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_DrvExt.lnt + lintsum_file := $(subst MakeCommon,DrvExt/lintsum_DrvExt.txt,$(MAKE_COMMON_DIR)) +else ifneq "$(COM_PATH)" "" + log_file := $(subst MakeCommon,Common/log_Common.txt,$(MAKE_COMMON_DIR)) + lint_file := $(subst MakeCommon,Common/lint_Common.txt,$(MAKE_COMMON_DIR)) + lintopt_file := options_Common.lnt + lintsum_file := $(subst MakeCommon,Common/lintsum_Common.txt,$(MAKE_COMMON_DIR)) +else + log_file := /dev/null + lint_file := /dev/null + lintopt_file := /dev/null + lintsum_file := /dev/null +endif + +ifeq "$(LOG_ERR)" "ON" + LOG_OPTION = 2>>$(log_file) + LOG_DATE = date >>$(log_file) + LOG_SPACE = echo >>$(log_file) +endif + +#---------------------------------------------------------------------- +# set the make targets +#---------------------------------------------------------------------- +build_D: make_debug_begin $(IMAGE_D) +build_R: make_release_begin $(IMAGE_R) +build_pipe_D: $(IMAGE_D) +build_pipe_R: $(IMAGE_R) + +ifeq "$(ISOLATE_DEP)" "ON" +build_DEP: make_dep_begin $(ALL_DEP) +endif + +build_LINT: make_lint_begin $(LINT_FILE) + +$(IMAGE_D): $(ALL_OBJ_D) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_D) \ + && $(AR) -cru $@ $^ + +$(IMAGE_R): $(ALL_OBJ_R) + @echo Creating library $(notdir $@) ... \ + && rm -f $(IMAGE_R) \ + && $(AR) -cru $@ $^ + +.PHONY: +rm_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(log_file) +endif + +clean: + @-echo Clean $(basename $(notdir $(IMAGE_R))) ... \ + && rm -rf --no-preserve-root $(PRJ_NAME)_Data $(log_file) $(lint_file) + +ifeq "$(ISOLATE_DEP)" "ON" +all: rm_log + @make dep + @make debug + @make release + +rebuild: + @make clean + @make dep + @make debug + @make release + +dep: build_DEP +else +rebuild: clean build_D build_R +endif + +debug: rm_log make_debug_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_D +else + $(MAKE) build_pipe_D $(JOB_FLAGS) +endif + +release: rm_log make_release_begin +ifeq ($(OS),Linux) + $(MAKE) build_pipe_R +else + $(MAKE) build_pipe_R $(JOB_FLAGS) +endif + +rm_lint_log: +ifeq "$(LOCAL_CLEAN_LOG)" "ON" + @-rm -f $(lint_file) +endif + +lint: rm_lint_log build_LINT + +lintclean: + @-echo Clean Lint $(basename $(notdir $(IMAGE_R))) checking data ... \ + && rm -rf --no-preserve-root $(LINT_DIR) $(lint_file) diff --git a/loader/MakeCommon/dump_tmp b/loader/MakeCommon/dump_tmp new file mode 100755 index 000000000..e69de29bb diff --git a/loader/MakeCommon/make_combo_loader.sh b/loader/MakeCommon/make_combo_loader.sh new file mode 100755 index 000000000..639bba753 --- /dev/null +++ b/loader/MakeCommon/make_combo_loader.sh @@ -0,0 +1,184 @@ +#!/bin/bash +MODEL_BUILD_LIST=("lunch rtos cfg_TEST_REALCHIP gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi" + "lunch rtos cfg_TEST_RTOS_RUN_CORE2 gcc-linaro-6.4.1-2018.05-x86_64_arm-eabi") + +function make_NT98560_loader_only(){ + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_560/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + #cp ../Project/Model/Loader560_Data/Release/LD98560A.bin ../output +} + +function make_NT98560_loader_use_ROM_API(){ + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_560/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" "ROM_PUBLIC_API := ON" + make release "MODEL=EMU_EVB" "ROM_PUBLIC_API := ON" -j66 + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + #cp ../Project/Model/Loader560_Data/Release/LD98560A.bin ../output +} + +function make_NT98560_loader_not_use_ROM_API(){ + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_560/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" "ROM_PUBLIC_API := OFF" + make release "MODEL=EMU_EVB" "ROM_PUBLIC_API := OFF" -j66 + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + #cp ../Project/Model/Loader560_Data/Release/LD98560A.bin ../output +} + + +function make_NT98528_loader_only(){ + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make clean "MODEL=EMU_EVB_528" + make release "MODEL=EMU_EVB_528" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + #cp ../Project/Model/Loader528_Data/Release/LD98528A.bin ../output +} + +function make_NT9852x_combo_loader(){ + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE COMBINATION_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean "MODEL=EMU_EVB" + make release "MODEL=EMU_EVB" "BIN_NAME=LDCOMBOA" "52x_528_COMBO=ON" + find ../Project/Model/ -name LD*.bin -exec cp {} ../output/LD9852XA.bin \; + #cp ../Project/Model/Loader525_Data/Release/LDCOMBOA.bin ../output/LD98525A.bin + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE COMBINATION_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean + make release "MODEL=EMU_EVB_528" "BIN_NAME=LDCOMBOA" + find ../Project/Model/ -name LD*.bin -exec cp {} ../output/LD98528A.bin \; + #cp ../Project/Model/Loader528_Data/Release/LDCOMBOA.bin ../output/LD98528A.bin + cat ../output/LD9852XA.bin ../output/LD98528A.bin > ../output/LDCOMBOA.bin + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h +} + +function make_NT98560_eth_write_loader(){ + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_560/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^STORAGEEXT =[ \t].*/STORAGEEXT = Eth/g' ../Project/Model/ModelConfig_EMU_EVB.txt + rm -rf ../Project/Model/Loader56* + make clean "MODEL=EMU_EVB" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name loader.bin -exec cp {} ../output \; + #cp ../Project/Model/Loader525_Data/Release/LD98525A.bin ../output +} + +function make_NT98528_eth_write_loader(){ + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE COMBINATION_528/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make clean + make release "MODEL=EMU_EVB_528" "BIN_NAME=LDCOMBOA" + find ../Project/Model/ -name loader.bin -exec cp {} ../output/loader.bin \; + #cp ../Project/Model/Loader528_Data/Release/LDCOMBOA.bin ../output/LD98528A.bin + #cat ../output/LD9852XA.bin ../output/LD98528A.bin > ../output/LDCOMBOA.bin + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_52x/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h +} + +function make_NT98560_sqa_fastboot_test_nand(){ + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h + cp ../Project/Model/Src/prj_main.h ../Project/Model/Src/prj_main_tmp.h + cp ../Project/Model/Src/prj_main.c ../Project/Model/Src/prj_main_tmp.c + sed -i 's/^#define LOADER_TYPE[ \t].*/#define LOADER_TYPE STAND_ALONE_LOADER_560/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + sed -i 's/^#define DEBUG_MSG[ \t].*/#define DEBUG_MSG (DISABLE)/g' ../Project/Model/Src/prj_main.h + sed -i 's/^[ \t]\/\/strg_obj->flash_setFrequency(96);*/strg_obj->flash_setFrequency(96);/g' ../Project/Model/Src/prj_main.c + make clean "MODEL=EMU_EVB" + make release "MODEL=EMU_EVB" + if [ -d "../output" ]; then + rm -rf ../output + mkdir -p ../output + else + mkdir -p ../output + fi + find ../Project/Model/ -name LD*.bin -exec cp {} ../output \; + cp ../LibExt/LIBExt_src/Ctrl_Flow/bl_func_tmp.h ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + cp ../Project/Model/Src/prj_main_tmp.h ../Project/Model/Src/prj_main.h + cp ../Project/Model/Src/prj_main_tmp.c ../Project/Model/Src/prj_main.c + #cp ../Project/Model/Loader560_Data/Release/LD98560A.bin ../output +} + + +echo -e "Please select NMAKE environment:" +echo -e "1. make NT9856x standalone loader(MODEL = EMU_EVB)" +echo -e "2. make NT9856x (tee) loader(MODEL = EMU_EVB)" +echo -e "3. make NT9856x loader(MODEL = EMU_EVB) use ROM Public API" +echo -e "4. make NT9856x loader(MODEL = EMU_EVB) Not use ROM Public API" +#echo -e "3. make NT9852x & NT98528 combination loader" +echo -e "5. make NT98560 Eth write loader(MODEL = EMU_EVB)" +#echo -e "5. make NT98528 Eth write loader(MODEL = EMU_EVB_528)" +echo -e "-------------------------------------------------------" +echo -e "6. make NT98560 power down loader(MODEL = EMU_EVB)" +echo -e "s. make NT98560 for SQA fastboot test(internal usage)" + + +read NMAKE_ENV +case ${NMAKE_ENV} in + "1") + make_NT98560_loader_only; + ;; + "2") + sed -i 's/^#define SDRAM_Start_FW[ \t].*/#define SDRAM_Start_FW 0x02800000/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + make_NT98560_loader_only; + sed -i 's/^#define SDRAM_Start_FW[ \t].*/#define SDRAM_Start_FW 0x02000000/g' ../LibExt/LIBExt_src/Ctrl_Flow/bl_func.h + ;; + "3") + make_NT98560_loader_use_ROM_API; + ;; + "4") + make_NT98560_loader_not_use_ROM_API; + ;; + "5") + make_NT98560_eth_write_loader; + ;; + "6") + make_NT98560_loader_only; + ./../Tools/Bin/bin2byte_linux ../output/LD98560A.bin v_resume_ldr 4 > ../output/pdn.txt + ;; + "s") + make_NT98560_sqa_fastboot_test_nand; + ;; + *) + echo -e "exit" + ;; +esac + + + diff --git a/loader/Project/Model/Debug_R.bat b/loader/Project/Model/Debug_R.bat new file mode 100755 index 000000000..e28e91ca2 --- /dev/null +++ b/loader/Project/Model/Debug_R.bat @@ -0,0 +1,5 @@ +@echo off +set CurrentDIR=%CD% +pushd C:\Program Files\teraterm +ttpmacro.exe /V %CurrentDIR%\LoadCode.ttl %CurrentDIR:\=/% Release Halt +popd diff --git a/loader/Project/Model/IceMode.ttl b/loader/Project/Model/IceMode.ttl new file mode 100755 index 000000000..9e886c452 --- /dev/null +++ b/loader/Project/Model/IceMode.ttl @@ -0,0 +1,6 @@ +connect 'localhost:4444 /DS /T=1' + +sendln 'halt' +wait '>' + +disconnect 0 \ No newline at end of file diff --git a/loader/Project/Model/IceMode_R.bat b/loader/Project/Model/IceMode_R.bat new file mode 100755 index 000000000..37b36abfd --- /dev/null +++ b/loader/Project/Model/IceMode_R.bat @@ -0,0 +1,11 @@ +@echo off +set CurrentDIR=%CD% +pushd C:\Program Files\teraterm +ttpmacro.exe /V %CurrentDIR%\IceMode.ttl +popd +set OLD_PATH=%PATH% +PATH=C:\NMake;%PATH% +start sde-insight --command=init_IceMode.gdb %CurrentDIR%/Loader660_Data/Release/Loader660.axf +PATH=%OLD_PATH% +set CurrentDIR= +set OLD_PATH= \ No newline at end of file diff --git a/loader/Project/Model/LDS_LZ.lds b/loader/Project/Model/LDS_LZ.lds new file mode 100755 index 000000000..ca37940a2 --- /dev/null +++ b/loader/Project/Model/LDS_LZ.lds @@ -0,0 +1,172 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP($LD_RESET_LIB/reset.o(.data*)); + $LD_RESET_LIB/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP($LD_RESET_LIB/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + KEEP($LD_RESET_LIB/config_dram1_tbl.o(.rodata*)); + config_dram1_tbl_2_start_base = .; + KEEP($LD_RESET_LIB/config_dram1_2_tbl.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x500: + AT (0x500) + { + _load_core2_entry_program_start_base = .; + KEEP($LD_RESET_LIB/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x600: + AT (0x600) + { + _load_LOADER_REMAP_start_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP($LD_RESET_LIB/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP($LD_RESET_LIB/configDDR.o(.text*)); + KEEP($LD_RESET_LIB/configDDR.o(.rodata*)); + KEEP(Driver/fuart.o(.text* .data* .rodata*)); + KEEP(Debug/debug.o (.text* .data* .bss*)); + KEEP($LD_COMMON_LIB/global.o (.text* .data* .bss* .rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC ADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP) : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text $LD_BASE_ADDR: + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + } + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(8); /* This is MUST. Ensure ro size is 2 word aligned. */ + } + .dram_text : + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_dram_text_start_base = .; + * (.dram_text) + } + _loader_dram_text_cpu_addr = LOADADDR(.dram_text) + ADDR(.BOOT_EXEC); + _loader_dram_text_size = SIZEOF(.dram_text); + .data : + AT (LOADADDR(.dram_text) + SIZEOF(.dram_text)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + . = ALIGN(0x400); + _ttb_lv2 = .; + . = . + 0x400; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/loader/Project/Model/LDS_NM.lds b/loader/Project/Model/LDS_NM.lds new file mode 100755 index 000000000..586d5e999 --- /dev/null +++ b/loader/Project/Model/LDS_NM.lds @@ -0,0 +1,161 @@ +/* Linker script for malta + * + * Version: Sourcery G++ Lite 4.3-221 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + * */ + +/* Rule: + * 1. to use .o in project layer just type the .o name with file extension. (UiFlow.o) + * 2. to use .o in library layer have to add prefix module name. (DscSystem/SysTask.o) + * */ + +OUTPUT_ARCH(arm) +ENTRY(__start) +SEARCH_DIR(.) + +SECTIONS +{ + .BOOT_EXEC 0xF07C0000|0x00000000: + AT (0) + { + _load_BOOT_EXEC_start_base = .; + KEEP(Reset/reset.o(.data*)); + Reset/reset.o(.text*); + _load_BOOT_EXEC_end_base = .; + } + .LOADER_CONFIGRAM (0xF07C0000|0x00000000) + 0x30: + AT (0x30) + { + _load_LOADER_CONFIGRAM_start_base = .; + KEEP($LD_REMAP_LIB/$LD_CONFIGRAM.o(.data*)); + _load_LOADER_CONFIGRAM_end_base = .; + _load_LOADER_CONFIGRAM_FREQ_PARAM_start_base = .; + KEEP(Reset/configramFreqParam.o(.data*)); + _load_LOADER_CONFIGRAM_FREQ_PARAM_end_base = .; + KEEP(Reset/config_dram1_tbl.o(.rodata*)); + } + .LOADER_CONFIGRAM2 (0xF07C0000|0x00000000) + 0x200: + AT (0x200) + { + KEEP(Reset/config_dram2_tbl.o(.rodata*)); + } + .LOADER_CORE2_ENTRY_PROGRAM (0xF07C0000|0x00000000) + 0x300: + AT (0x300) + { + _load_core2_entry_program_start_base = .; + KEEP(Reset/core2_entry.o(.text)); + _load_core2_entry_program_end_base = .; + } + .internal_stg_type (0xF07C0000|0x00000000) + 0x420: { LONG (0x46495053) } + .internal_stg_version : + AT (LOADADDR(.internal_stg_type) + SIZEOF(.internal_stg_type)) + { + _load_nand_table_start_base = .; + _load_nand_table_end_base = .; + } + .LOADER_REMAP (0xF07C0000|0x00000000) + 0x430: + AT (0x430) + { + _load_vector_int_table_start_base = .; + KEEP(Reset/isr.o(.text)); + _load_vector_int_table_end_base = .; + $LD_REMAP_LIB/$LD_DOREMAP.o(.text*); + _load_LOADER_REMAP_end_base = .; + _load_vector_exp_table_start_base = .; + KEEP(Reset/exp.o(.text*)); + _load_vector_exp_table_end_base = .; + KEEP(Reset/configDDR.o(.text*)); + KEEP(Reset/configDDR.o(.rodata*)); + . = ALIGN(4); /* This is MUST. Ensure section size is word aligned. */ + } + + . = ALIGN(4); + .LOADER_EXEC : + AT (LOADADDR(.LOADER_REMAP) + SIZEOF(.LOADER_REMAP)) + { + _loader_exec_start_base = .; + KEEP(Ctrl_Flow/main.o(.part1*)); + KEEP(Driver/rtc.o(.part1*)); + * (.part1) + _loader_exec_end_base = .; + } + _loader_exec_cpu_addr = LOADADDR(.LOADER_EXEC) + ADDR(.BOOT_EXEC); + _loader_exec_size = SIZEOF(.LOADER_EXEC); + + . = ALIGN(4); + .text : + AT (LOADADDR(.LOADER_EXEC) + SIZEOF(.LOADER_EXEC)) + { + _loader_exec_compres_start = .; + _internal_strg_param_start = .; + *(.text*) + _loader_exec_compres_end = .; + } + _loader_exec_compress_load_base = LOADADDR(.text); + _loader_exec_compress_load_cpu_addr = LOADADDR(.text) + ADDR(.BOOT_EXEC); + . = ALIGN(4); + .rodata : + { + *(.rodata*) + . = ALIGN(4); /* This is MUST. Ensure ro size is word aligned. */ + } + .data 0xFF00000: + AT (LOADADDR(.rodata) + SIZEOF(.rodata)) + { + _loader_data_start_base = .; + _load_general_var_base = .; + _image_general_var_base = .; + *(.data*) + _image_general_var_limit = .; + } + _loader_data_cpu_addr = LOADADDR(.data) + ADDR(.BOOT_EXEC); + _loader_data_size = SIZEOF(.data); + .dummy : { LONG (0x00000000) } + . = ALIGN(4); + .got : { *(.got) } + . = ALIGN(4); + .bss : { /* locate bss at DRAM end */ + _image_general_zi_zi_base = .; + *(.bss) + . = ALIGN(0x4000); + _ttb = .; + . = . + 0x4000; + } + .common : + { + __common_base = ABSOLUTE(.); + /* collect "small" un-initialized global data (mark "C" in sym file) */ + *(.scommon*) + /* collect "large" un-initialized global data (mark "B" in sym file) */ + *(COMMON) + __common_limit = ABSOLUTE(.); + } + . = ALIGN(64); + _image_general_zi_zi_limit = ABSOLUTE(.); + _load_load_reset_base = .; + _image_load_reset_base = .; + _image_load_reset_length = .; + _image_load_reset_zi_base = .; + _image_load_reset_zi_limit = .; + . = ALIGN(64); + .loader_heap : + { + _loader_heap_base = .; + . += 0xA0000 + 0x20000 + 0x80000; + } + . = ALIGN(64); + _stack_start = .; + +} diff --git a/loader/Project/Model/LoadCode.ttl b/loader/Project/Model/LoadCode.ttl new file mode 100755 index 000000000..7bfc6bbe8 --- /dev/null +++ b/loader/Project/Model/LoadCode.ttl @@ -0,0 +1,29 @@ +connect 'localhost:4444 /DS /T=1' + +sendln 'halt' +wait '>' + +sendln 'binit' +wait '>' + +send 'load_image ' +send param2 +send '/Loader680_Data/' +send param3 +sendln '/LD96680A.bin 0xF07F0000' +wait '>' +wait '>' +sendln 'reg pc 0xF07F0028' + + +strcompare param4 'Resume' +if result=0 then + sendln 'reg pc 0xF07F0028' + wait '>' + sendln 'resume' + wait '>' +endif + +sendln 'exit' + +disconnect 0 \ No newline at end of file diff --git a/loader/Project/Model/MakeConfig.txt b/loader/Project/Model/MakeConfig.txt new file mode 100755 index 000000000..78fe38ce1 --- /dev/null +++ b/loader/Project/Model/MakeConfig.txt @@ -0,0 +1,859 @@ +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +#------------------------------------------------------------------------------ +# Loader version : unsigned long loader version definition +#------------------------------------------------------------------------------ +LOADER_VERSION = 0x01000001 +BL_LOADER_VER_PARAM = \ + -D_LDR_VER_="$(LOADER_VERSION)" + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Hardware device selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Select main chip ID +#------------------------------------------------------------------------------ +#CHIP = 520 + +#------------------------------------------------------------------------------ +# Select chip version +#------------------------------------------------------------------------------ +#CHIP_VER = A +#CHIP_VER = B + +#------------------------------------------------------------------------------ +# Select LV1 clock rate +# LV1: 491MHz / 593MHz +#------------------------------------------------------------------------------ +#LV1_CLK = 491 +#LV1_CLK = 593 + +#------------------------------------------------------------------------------ +# Select DMA clock rate +#------------------------------------------------------------------------------ +#DMA_CLOCK = LV0 +#DMA_CLOCK = LV1 + +#ifeq "$(DMA_CLOCK)" "LV1" +#ifeq "$(LV1_CLK)" "491" +#DMA_CLOCK = LV1_4 +#else +#DMA_CLOCK = LV1_5 +#endif +#endif + +ifeq "$(CHIP)" "566" + +ifeq "$(DRAM1_CLK)" "933" +DRAM1_CLK = 933 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 507 +else ifeq "$(DRAM1_CLK)" "760" +DRAM1_CLK = 760 +else +DRAM1_CLK = 507 +endif + +SDRAM_SIZE = 1024 + +else ifeq "$(CHIP)" "562" + +ifeq "$(DRAM1_CLK)" "666" +DRAM1_CLK = 666 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 522 +else ifeq "$(DRAM1_CLK)" "522" +DRAM1_CLK = 522 +else +DRAM1_CLK = 522 +endif + +SDRAM_SIZE = 512 + +else ifeq "$(CHIP)" "563" + +ifeq "$(DRAM1_CLK)" "666" +DRAM1_CLK = 666 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 522 +else ifeq "$(DRAM1_CLK)" "522" +DRAM1_CLK = 522 +else +DRAM1_CLK = 522 +endif +SDRAM_SIZE = 512 + +else ifeq "$(CHIP)" "565" + +ifeq "$(DRAM1_CLK)" "933" +DRAM1_CLK = 933 +else ifeq "$(DRAM1_CLK)" "507" +DRAM1_CLK = 507 +else ifeq "$(DRAM1_CLK)" "760" +DRAM1_CLK = 760 +else +DRAM1_CLK = 507 +endif + +SDRAM_SIZE = 1024 + +else +endif + +#------------------------------------------------------------------------------ +# Select DRAM Size (unit: Giga bit) +#------------------------------------------------------------------------------ +#SDRAM_SIZE = 1024 +#SDRAM_SIZE = 2048 +#SDRAM_SIZE = 4096 + +#------------------------------------------------------------------------------ +# Select DRAM Type (DDR3L curruently NOT available) +#------------------------------------------------------------------------------ +#DRAM_TYPE = DDR3 +#DRAM_TYPE = DDR3L + +#------------------------------------------------------------------------------ +# Select Phy analog block LV / HV +# (Don't modify this item) +#------------------------------------------------------------------------------ +PHY_ANALOG_HV = HV + +#------------------------------------------------------------------------------ +# CPU Core version configuration +# (Don't modify this item) +#------------------------------------------------------------------------------ +#CA53_ARCH32 +#CA9 +CPU_CORE = CA9 + +#------------------------------------------------------------------------------ +# Select internal storage device +#------------------------------------------------------------------------------ +#STORAGEINT = NandEccRS +#STORAGEINT = NandSpi +#STORAGEINT = SpiFlash + +#------------------------------------------------------------------------------ +# Select external storage device +#------------------------------------------------------------------------------ +#STORAGEEXT = Sdio1 +#STORAGEEXT = Sdio2 +#STORAGEEXT = Usb + +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +# +# Software function selection +# +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +#------------------------------------------------------------------------------ +# Dram range scan loader support enable +# (Don't modify this item) +#------------------------------------------------------------------------------ +DRAM_RANGE_SCAN_SUPPORT_EN = ENABLE +#DRAM_RANGE_SCAN_SUPPORT_EN = DISABLE + +#------------------------------------------------------------------------------ +# Select GUI interface display or not +#------------------------------------------------------------------------------ +# [CONFIG_RAM_GUI_EN] +# ENABLE +# DISABLE +CONFIG_RAM_GUI_EN = DISABLE + +#------------------------------------------------------------------------------ +# Set binary file build name +#------------------------------------------------------------------------------ +CHIP_SHORT = $(shell echo $(CHIP)|awk '{print substr($$0,length($$0)-2,3)}') +ifeq "$(CHIP)" "575" +BIN_NAME = LD96575A +else ifeq "$(CHIP)" "570" +BIN_NAME = LD96570A +else ifeq "$(CHIP)" "580" +BIN_NAME = LD96580A +endif +ifeq "$(CHIP)" "523_A" +BIN_NAME = LD523_AA +endif +ifeq "$(STORAGEEXT)" "Eth" +LDR_NAME = loader +else +LDR_NAME = $(BIN_NAME) +endif +BL_UPDATE_CALNAME = FW96$(CHIP_SHORT)C.BIN +BL_CALIBRATION_FWNAME = CALFW680.BIN +TMP_NAME = LD96$(CHIP)1 + +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_1st)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else +ifeq "$(LOADER_SUPPORT_NAND_1st)" "" + _LOADER_NAND_SUPPORT_NAND_1st_ = default_1 +else + _LOADER_NAND_SUPPORT_NAND_1st_ = $(LOADER_SUPPORT_NAND_1st) +endif +endif +#------------------------------------------------------------------------------ +# 1st NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_2nd_=default_2 +else +ifeq "$(LOADER_SUPPORT_NAND_2nd)" "" + _LOADER_NAND_SUPPORT_NAND_2nd_ = default_2 +else + _LOADER_NAND_SUPPORT_NAND_2nd_ = $(LOADER_SUPPORT_NAND_2nd) +endif +endif +#------------------------------------------------------------------------------ +# 2nd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "DEFAULT_NAND_TYPE" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else +ifeq "$(LOADER_SUPPORT_NAND_3rd)" "" + _LOADER_NAND_SUPPORT_NAND_3rd_ = default_3 +else + _LOADER_NAND_SUPPORT_NAND_3rd_ = $(LOADER_SUPPORT_NAND_3rd) +endif +endif + +#------------------------------------------------------------------------------ +# 3rd NAND configuration support list +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Set bootloader specific strings +#------------------------------------------------------------------------------ +STR_MODEL = $(MODEL_DESC) +STR_DATE = $(shell date +%m/%d/%Y) +STR_TIME = $(shell date +%H:%M:%S) + +BL_START = "Loader NT98$(CHIP) Start ..." +BL_UPDATE_LOADERNAME = $(BIN_NAME).BIN +ifeq "$(CHIP)" "575" +BL_UPDATE_FWNAME := FW96575A.BIN +BL_UPDATE_CALNAME := FW96575C.BIN +BL_RUN_FWNAME := FW96575T.BIN +BL_CALIBRATION_FWNAME := CALFW575.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "570" +BL_UPDATE_FWNAME := FW96570A.BIN +BL_UPDATE_CALNAME := FW96570C.BIN +BL_RUN_FWNAME := FW96570T.BIN +BL_CALIBRATION_FWNAME := CALFW570.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +else ifeq "$(CHIP)" "580" +BL_UPDATE_FWNAME := FW96580A.BIN +BL_UPDATE_CALNAME := FW96580C.BIN +BL_RUN_FWNAME := FW96580T.BIN +BL_CALIBRATION_FWNAME := CALFW580.BIN +BL_START = "Loader NT96$(CHIP) Start ..." +endif +ifeq "$(CHIP)" "523_A" +BL_UPDATE_FWNAME := FW523_AA.BIN +BL_UPDATE_CALNAME := FW523_AC.BIN +BL_RUN_FWNAME := FW523_AT.BIN +BL_CALIBRATION_FWNAME := CALFW523.BIN +BL_START = "Loader NT98$(CHIP) Start ..." +endif + +BL_WRKEY_FWNAME := WRKEY.BIN +BL_UBOOT_FWNAME := UBOOTBIN.BIN + +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" +MODEL_DESC2 = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE)Mb" +BL_VERSION2 = "$(MODEL_DESC2) $(STR_DATE) $(STR_TIME)" +endif + +ifeq "$(NC520_525_COMBO)" "ON" +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE)Mb_combo_NC520_DRAM1_$(NC520_COMBO_DRAM1_CLK)_$(NC520_COMBO_SDRAM_SIZE)Mb_DRAM2_NULL" +else +MODEL_DESC = "$(CHIP)$(CHIP_VER)_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE)Mb" +endif +BL_VERSION = "$(MODEL_DESC) $(STR_DATE) $(STR_TIME)" + +#------------------------------------------------------------------------------ +# Select bootloader compression +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [BL_COMPRESS] +# ENABLE +# DISABLE +BL_COMPRESS = ENABLE + +#Do not modify this parameter 0x08 if loader compress enabled +# [UNCOMPRESSEDPART_SIZE_OFFSET] +# 0x60 +# 0x08 +UNCOMPRESSEDPART_SIZE_OFFSET = 0x08 + +#------------------------------------------------------------------------------ +# Select compressable f/w (main code) +#------------------------------------------------------------------------------ +# [MAINCODE_COMPRESS] +# ENABLE +# DISABLE +MAINCODE_COMPRESS = DISABLE + +#------------------------------------------------------------------------------ +# Select firmware image checksum validation +#------------------------------------------------------------------------------ +# [CHKFWIMAGE] +# NOCHECK +# CHECKSUM +# CRC +CHKFWIMAGE = CHECKSUM + +#------------------------------------------------------------------------------ +# Select loader flow +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [LOADER_FLOW ] +# NORMAL_LDR_FLOW +# MODULE_TST_FLOW +LOADER_FLOW = NORMAL_LDR_FLOW + +ifeq "$(LOADER_FLOW)" "NORMAL_LDR_FLOW" +BL_LOADER_FLOW = 0 +else +BL_LOADER_FLOW = 1 +endif + +BL_LOADER_FLOW_PARAM = \ +-D_BL_MAIN_SPECIAL_FLOW_=$(BL_LOADER_FLOW) + +#------------------------------------------------------------------------------ +# Select Duty calibration ENABLE / DISABLE +#------------------------------------------------------------------------------ +DUTY_CALIBRATION = DISABLE + +#------------------------------------------------------------------------------ +# Select Duty calibration type +# (Don't modify this item) +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_TYPE ] +# AUTO +# MANUAL +DUTY_CALIBRATION_TYPE = AUTO + +ifeq "$(DUTY_CALIBRATION_TYPE)" "AUTO" +BL_DUTY_CALIBRATION_TYPE = 0 +else +BL_DUTY_CALIBRATION_TYPE = 1 +endif + +BL_DUTY_CALIBRATION_TYPE_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_TYPE_=$(BL_DUTY_CALIBRATION_TYPE) + +#------------------------------------------------------------------------------ +# Select Duty calibration LOG ENABLE / DISABLE +#------------------------------------------------------------------------------ +# [DUTY_CALIBRATION_LOG] +# ENABLE +# DISABLE +DUTY_CALIBRATION_LOG = DISABLE + +ifeq "$(LOADER_FLOW)" "MODULE_TST_FLOW" +DUTY_CALIBRATION = DISABLE +endif + +ifeq "$(DUTY_CALIBRATION)" "DISABLE" +DUTY_CALIBRATION_LOG = DISABLE +else +ifeq "$(DUTY_CALIBRATION_TYPE)" "MANUAL" +DUTY_CALIBRATION_LOG = DISABLE +endif +endif + +ifeq "$(DUTY_CALIBRATION)" "ENABLE" +BL_DUTY_CALIBRATION = 1 +else +BL_DUTY_CALIBRATION = 0 +endif + +ifeq "$(DUTY_CALIBRATION_LOG)" "ENABLE" +BL_DUTY_CALIBRATION_LOG = 1 +else +BL_DUTY_CALIBRATION_LOG = 0 +endif + +BL_DUTY_CALIBRATION_PARAM = \ +-D_LOADER_DUTY_CALIBRATION_LOG_=$(BL_DUTY_CALIBRATION_LOG)\ +-D_LOADER_DUTY_CALIBRATION_=$(BL_DUTY_CALIBRATION) + + +#------------------------------------------------------------------------------ +# Bootloader update image file name parameters +#------------------------------------------------------------------------------ +BL_UPDATE_NAME_PARAM = \ + -D_UPDATE_FW_NAME_=\"$(BL_UPDATE_FWNAME)\" \ + -D_UPDATE_LOADER_NAME_=\"$(BL_UPDATE_LOADERNAME)\" \ + -D_RUN_FW_NAME_=\"$(BL_RUN_FWNAME)\" \ + -D_UPDATE_CALFW_NAME_=\"$(BL_UPDATE_CALNAME)\"\ + -D_RUN_CAL_FW_NAME_=\"$(BL_CALIBRATION_FWNAME)\" \ + -D_WR_KEY_FW_NAME_=\"$(BL_WRKEY_FWNAME)\" \ + -D_RUN_UBOOT_NAME_=\"$(BL_UBOOT_FWNAME)\" + + +#------------------------------------------------------------------------------ +# Bootloader specific strings parameters +#------------------------------------------------------------------------------ +BL_STRINGS_PARAM = \ +-D_LOADER_VERSION_STR_=\"\\\r\\\n$(BL_VERSION)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_VERSION_STR2_=\"\\\r\\\n$(BL_VERSION2)\\\r\\\n\\\r\\\n\" \ +-D_LOADER_START_STR_=\"\\\r\\\n$(BL_START)\\\r\\\n\" + +#------------------------------------------------------------------------------ +# Bootloader compression parameters +#------------------------------------------------------------------------------ +ifeq "$(BL_COMPRESS)" "ENABLE" + BL_COMPRESS_CFG = 1 + ifeq "$(CHIP)" "560" + RESETFLAG = LZ560 + else ifeq "$(CHIP)" "562" + RESETFLAG = LZ562 + else ifeq "$(CHIP)" "563" + RESETFLAG = LZ563 + else ifeq "$(CHIP)" "565" + RESETFLAG = LZ565 + else ifeq "$(CHIP)" "566" + RESETFLAG = LZ566 + else + RESETFLAG = LZ + endif + + ifeq "$(CHIP)" "560" + RESETCHIP = 560 + SCATTER_EXT= + else ifeq "$(CHIP)" "562" + RESETCHIP = 560 + SCATTER_EXT= + else ifeq "$(CHIP)" "563" + RESETCHIP = 560 + SCATTER_EXT= + else ifeq "$(CHIP)" "565" + RESETCHIP = 560 + SCATTER_EXT= + else ifeq "$(CHIP)" "566" + RESETCHIP = 560 + SCATTER_EXT= + else + RESETCHIP = 56x + SCATTER_EXT= + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif + +else + BL_COMPRESS_CFG = 0 + ifeq "$(CHIP)" "560" + RESETFLAG = NM560 + else + RESETFLAG = NM + endif + + ifeq "$(CHIP)" "560" + RESETCHIP = 560 + else + RESETCHIP = 56x + endif + + ifeq "$(EXFAT_FILESYSTEM_SUPPORT)" "EXFAT" + COMMON_LIB = exFAT + else + COMMON_LIB = normal + endif +endif + +ifeq "$(MAINCODE_COMPRESS)" "ENABLE" + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=1 +else + FWCOMPRESS_PARAM = -D_MAINCODE_COMPRESS_=0 +endif + +BL_COMPRESS_PARAM = \ +-D_LOADER_COMPRESSED_=$(BL_COMPRESS_CFG) + +BL_COMPRESS_PARAM_ASM = +#\ +#-PD "_LOADER_COMPRESSED_ SETA $(BL_COMPRESS_CFG)" + +#------------------------------------------------------------------------------ +# Firmware image checksum validation parameters +#------------------------------------------------------------------------------ +ifeq "$(CHKFWIMAGE)" "NOCHECK" + CHKFWIMAGE_CFG = FW_CHECK_NOCHECK +endif + +ifeq "$(CHKFWIMAGE)" "CHECKSUM" + CHKFWIMAGE_CFG = FW_CHECK_CHECKSUM +endif + +ifeq "$(CHKFWIMAGE)" "CRC" + CHKFWIMAGE_CFG = FW_CHECK_CRC +endif + +CHKFWIMAGE_PARAM = \ + -DFW_CHECK_NOCHECK=0 \ + -DFW_CHECK_CHECKSUM=1 \ + -DFW_CHECK_CRC=2 \ + -DFW_CHECK_METHOD=$(CHKFWIMAGE_CFG) + +#------------------------------------------------------------------------------ +# External Storage define +#------------------------------------------------------------------------------ + +ifeq "$(STORAGEINT)" "EMMC_NAND_COMBO" +ifeq "$(STORAGEEXT)" "NONE" +else +$(error STORAGEEXT MUST = [NONE] if STORAGEINT= [EMMC_NAND_COMBO]=>Please check [ModelConfig_EMU_EVB.txt] configuration) +endif +endif + + +ifeq "$(STORAGEEXT)" "Sdio1" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO1 +else ifeq "$(STORAGEEXT)" "Sdio2" + STORAGE_EXT_TYPE = STORAGE_EXT_SDIO2 +else ifeq "$(STORAGEEXT)" "Usb" + STORAGE_EXT_TYPE = STORAGE_EXT_USB +else ifeq "$(STORAGEEXT)" "Eth" + STORAGE_EXT_TYPE = STORAGE_EXT_ETH +else ifeq "$(STORAGEEXT)" "Uart" + STORAGE_EXT_TYPE = STORAGE_EXT_UART +else ifeq "$(STORAGEEXT)" "NONE" + STORAGE_EXT_TYPE = STORAGE_EXT_NONE +else + STORAGE_EXT_TYPE = STORAGE_EXT_UNKOWN +endif + +EXTSTRG_PARAM = \ + -DSTORAGE_EXT_UNKOWN=0 \ + -DSTORAGE_EXT_SDIO1=1 \ + -DSTORAGE_EXT_SDIO2=2 \ + -DSTORAGE_EXT_UART=3 \ + -DSTORAGE_EXT_USB=4 \ + -DSTORAGE_EXT_ETH=5 \ + -DSTORAGE_EXT_NONE=6\ + -DSTORAGE_EXT_TYPE=$(STORAGE_EXT_TYPE) + +#------------------------------------------------------------------------------ +# SPI define +#------------------------------------------------------------------------------ +ifeq "$(STORAGEINT)" "SpiFlash" + STORAGE_INT_TYPE = -DSTORAGEINT_SPI=1 +else + STORAGE_INT_TYPE = +endif + +ifeq "$(SPI_SETTING)" "SPI_4BITS" + SPI_PINMUX = SPI_PINMUX_4BITS +endif + +ifeq "$(SPI_SETTING)" "SPI_NORMAL" + SPI_PINMUX = SPI_PINMUX_NORMAL +endif + +SPIPINMUX_PARAM = \ + -DSPI_PINMUX_NORMAL=0 \ + -DSPI_PINMUX_4BITS=1 \ + -DSPI_PINMUX_SETTING=$(SPI_PINMUX) + +#------------------------------------------------------------------------------ +# EMMC define +#------------------------------------------------------------------------------ +ifeq "$(EMMC_SETTING)" "EMMC_8BITS" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +ifeq "$(EMMC_SETTING)" "EMMC_NORMAL" + EMMC_PINMUX = EMMC_PINMUX_NORMAL +endif + +ifeq "$(EMMC_SETTING)" "" + EMMC_PINMUX = EMMC_PINMUX_8BITS +endif + +EMMCPINMUX_PARAM = \ + -DEMMC_PINMUX_NORMAL=0 \ + -DEMMC_PINMUX_8BITS=1 \ + -DEMMC_PINMUX_SETTING=$(EMMC_PINMUX) + +#------------------------------------------------------------------------------ +# Dram range scan support enable parameters +#------------------------------------------------------------------------------ +ifeq "$(DRAM_RANGE_SCAN_SUPPORT_EN)" "ENABLE" + DRAM_SCAN_EN = 1 +else + DRAM_SCAN_EN = 0 +endif + +DRAMSCAN_PARAM = -DDRAM_RANGE_SCAN_EN=$(DRAM_SCAN_EN) + +#------------------------------------------------------------------------------ +# Chip ID related parameters +#------------------------------------------------------------------------------ +ifeq "$(CHIP)" "560" +CHIPID = 560 +else +CHIPID = 560 +endif +#------------------------------------------------------------------------------ +# Secure boot parameters +#------------------------------------------------------------------------------ +ifeq "$(SECUREBOOT)" "Secure" +SECUREBOOT_MSG = 0 +ifeq "$(SIGNATUREMETHOD)" "AES128" +#Secure enable + AES signature +SECURE_BOOT = 1 +else +#Secure enable + RSA signature +SECURE_BOOT = 2 +endif +ifeq "$(ENCRYPTDATA)" "AES128" +ENCRYPT_DATA = 1 +else +ENCRYPT_DATA = 0 +endif +else +SECURE_BOOT = 0 +endif + + + +#------------------------------------------------------------------------------ +# DRAM ini file name generation +#------------------------------------------------------------------------------ +#ifeq "$(DRAM_TYPE)" "DDR3L" +# ifeq "$(DMA_CLOCK)" "LV0" +# $(error DDR3L only support DMA_CLOCK = LV1) +# endif +# ifeq "$(LV1_CLK)" "373" +# $(error DDR3L only support LV1_CLK = 400) +# endif +# DDR_FILE_STR = _DDR3L +#else +# DDR_FILE_STR = +#endif + +ifeq "$(DMA_CLOCK)" "LV0" + +DDR_INI_STR = $(CHIP)/51055A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DDR_INI2_STR = $(CHIP)/51055A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini +#DDR_INI_STR = 680_$(CHIP_VER)_LV0_$(SDRAM_SIZE).ini +ifeq "$(LV1_CLK)" "491" +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_4_$(SDRAM_SIZE).ini +else +#DDR_INI2_STR = 680_$(CHIP_VER)_LV1_5_$(SDRAM_SIZE).ini +endif + +else + +ifneq "$(DRAM_2ND_TBL_DETECT)" "Normal" + +DDR_INI_STR = $(CHIP)/51089A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DDR_INI2_STR = $(CHIP)/51089A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + +DDR_INI_STR2 = $(CHIP)/51089A_DRAM1_$(DRAM1_2ND_CLK)_$(SDRAM_2ND_SIZE).ini +#DDR_INI2_STR2 = $(CHIP)/51089A_DRAM2_$(DRAM2_2ND_CLK)_$(SDRAM2_2ND_SIZE).ini + +2ND_INI = $(DRAM_2ND_TBL_DETECT) +GPIO_NUM = $(DRAM_2ND_TBL_DETECT_GPIO_NO) + +else + +DDR_INI_STR = $(CHIP)/51089A_DRAM1_$(DRAM1_CLK)_$(SDRAM_SIZE).ini +#DR_INI2_STR = $(CHIP)/51089A_DRAM2_$(DRAM2_CLK)_$(SDRAM2_SIZE).ini + + +2ND_INI = "" +GPIO_NUM = 0 + +endif +endif + +ifeq "$(DRAM1_POWEROFF_S3)" "Enabled" +DRAM1_RST_PARAM = 1 +else +DRAM1_RST_PARAM = 0 +endif + + +ifeq "$(DRAM_SSC_ENABLE)" "Normal" +DRAM_SSC_PARAM = 0 +else ifeq "$(DRAM_SSC_ENABLE)" "1" +DRAM_SSC_PARAM = 1 +else ifeq "$(DRAM_SSC_ENABLE)" "2" +DRAM_SSC_PARAM = 2 +else ifeq "$(DRAM_SSC_ENABLE)" "3" +DRAM_SSC_PARAM = 3 +else ifeq "$(DRAM_SSC_ENABLE)" "4" +DRAM_SSC_PARAM = 4 +else ifeq "$(DRAM_SSC_ENABLE)" "5" +DRAM_SSC_PARAM = 5 +else +DRAM_SSC_PARAM = 0 +endif + +ifeq "$(DRAM_ODT)" "Normal" +ODT_SELECT = "" +else ifeq "$(DRAM_ODT)" "Enable" +ODT_SELECT = "ENABLE" +else ifeq "$(DRAM_ODT)" "Disable" +ODT_SELECT = "DISABLE" +else +ODT_SELECT = "" +endif + +#------------------------------------------------------------------------------- +# set the scatter file name here +#------------------------------------------------------------------------------- +ifeq "$(BL_COMPRESS)" "ENABLE" +SCATTER = LDS_LZ$(SCATTER_EXT).lds +else +SCATTER = LDS_NM.lds +endif + +#------------------------------------------------------------------------------- +# set loader execution DRAM address +#------------------------------------------------------------------------------- +# 255MB +ifeq "$(SDRAM_SIZE)" "512" +LD_BASE_ADDR = 0x3C00000 +else ifeq "$(SDRAM_SIZE)" "1024" +LD_BASE_ADDR = 0x7C00000 +else ifeq "$(SDRAM_SIZE)" "2048" +LD_BASE_ADDR = 0xFC00000 +else +LD_BASE_ADDR = 0xFC00000 +endif +BL_LDADDR_PARAM = \ +-DLD_BASE_ADDR=$(LD_BASE_ADDR) + +#------------------------------------------------------------------------------- +# set loader internal storage type +#------------------------------------------------------------------------------- +BL_STORAGEINT_PARAM = \ +-D_STORAGEINT_$(STORAGEINT)_ + +#------------------------------------------------------------------------------- +# Model parameters +#------------------------------------------------------------------------------- +ifeq "$(MODEL)" "EMU_EVB" + MODEL_TYPE = _MODEL_EMU_EVB_ +endif + +ifeq "$(MODEL)" "DEMO1_EVB" + MODEL_TYPE = _MODEL_DEMO1_EVB_ +endif + +ifeq "$(MODEL)" "ARTOSYN_EVB" + MODEL_TYPE = _MODEL_ARTOSYN_EVB_ +endif +MODEL_PARAM = \ + -D_MODEL_EMU_EVB_=0 \ + -D_MODEL_DEMO1_EVB_=1 \ + -D_MODEL_ARTOSYN_EVB_=2 \ + -D_MODEL_DSC_=$(MODEL_TYPE) + +#------------------------------------------------------------------------------- +# uboot encrypt binary or not parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Normal" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Secure" + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_ENABLE_ +else + UBOOT_DECRYPT_TYPE = _SECURE_DECRYPT_UBOOT_DISABLE_ +endif + +SECURE_DECRYPT_UBOOT_PARAM = \ + -D_SECURE_DECRYPT_UBOOT_DISABLE_=0 \ + -D_SECURE_DECRYPT_UBOOT_ENABLE_=1 \ + -DSECURE_DECRYPT_UBOOT=$(UBOOT_DECRYPT_TYPE) + +#------------------------------------------------------------------------------- +# optee parameters +#------------------------------------------------------------------------------- +ifeq "$(SECUREBOOT_DECRYPT_OPTEE)" "Normal" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +else ifeq "$(SECUREBOOT_DECRYPT_UBOOT)" "Secure" + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_ENABLE_ +else + OPTEE_DECRYPT_TYPE = _SECURE_DECRYPT_OPTEE_DISABLE_ +endif + + +SECURE_DECRYPT_OPTEE_PARAM = \ + -D_SECURE_DECRYPT_OPTEE_DISABLE_=0 \ + -D_SECURE_DECRYPT_OPTEE_ENABLE_=1 \ + -DSECURE_DECRYPT_OPTEE_OS=$(OPTEE_DECRYPT_TYPE) + + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(SIGNATUREMETHOD)" "AES128" +# => AES signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_AES128_ +else +# => RSA signature +OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE = _UBOOT_OPTEE_SIGNATURE_USE_RSA_ +endif + +OPTEE_UBOOT_SIGNATURE_PARAM = \ + -D_UBOOT_OPTEE_SIGNATURE_USE_RSA_=0 \ + -D_UBOOT_OPTEE_SIGNATURE_USE_AES128_=1 \ + -DSECURE_SIGNATURE_BY_AES=$(OPTEE_UBOOT_DIGITAL_SIGNATURE_TYPE) + + +#------------------------------------------------------------------------------- +# optee or uboot digital signature parameters +#------------------------------------------------------------------------------- +ifeq "$(CHIP)" "565" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "563" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +else ifeq "$(CHIP)" "562" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else ifeq "$(CHIP)" "566" +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_2_ +else +CARD_DETECT_PIN_TYPE = _CARD_DETECT_TYPE_1_ +endif + +CARDDET_PIN_PARAM = \ + -D_CARD_DETECT_TYPE_0_=0 \ + -D_CARD_DETECT_TYPE_1_=1 \ + -D_CARD_DETECT_TYPE_2_=2 \ + -DCARD_DETECT_PIN=$(CARD_DETECT_PIN_TYPE) + +ifeq "$(DDR_TREFI)" "Extend" +DDR_TREFI_PARAM = 1 +else +DDR_TREFI_PARAM = 0 +endif + diff --git a/loader/Project/Model/Makefile b/loader/Project/Model/Makefile new file mode 100755 index 000000000..904ec8b2b --- /dev/null +++ b/loader/Project/Model/Makefile @@ -0,0 +1,131 @@ +#---------------------------------------------------------------------- +# set the ROOT directory here +#---------------------------------------------------------------------- +ROOT_DIR = ../.. + +#---------------------------------------------------------------------- +# include make config file +#---------------------------------------------------------------------- +include ModelConfig.txt +include ModelConfig_$(MODEL).txt +include MakeConfig.txt + +#---------------------------------------------------------------------- +# set the project name here +#---------------------------------------------------------------------- +PRJ_NAME = Loader$(CHIP) + +#---------------------------------------------------------------------- +# set loader execution DRAM address +#---------------------------------------------------------------------- +ifeq "$(SDRAM_SIZE)" "1024" +# 1Gb*2 => 256MB => 0x1000_0000 +LD_BASE_ADDR = 0xF000000 +else ifeq "$(SDRAM_SIZE)" "2048" +# 2Gb*2 => 512MB => 0x2000_0000 +LD_BASE_ADDR = 0x1F000000 +else +# 4Gb*2 => 1024MB => 0x4000_0000 +LD_BASE_ADDR = 0x3F000000 +endif + +ifeq "$(LOADER_DRAM_ADDR)" "" +LD_BASE_ADDR = 0x1000000 +else +LD_BASE_ADDR = $(LOADER_DRAM_ADDR) +endif + +#---------------------------------------------------------------------- +# set the include directory here +#---------------------------------------------------------------------- +INC_DIR = . \ + ../../Include + +#---------------------------------------------------------------------- +# add/delete the project assembly files here +#---------------------------------------------------------------------- +#ASM = Src/reset.S \ +#Src/remap.S + + + + +#---------------------------------------------------------------------- +# add/delete the project C source files here +#---------------------------------------------------------------------- +SRC = \ + Src/prj_main.c \ + Src/USB/usb_update.c \ + Src/UART/uart_upgrade.c + + + + +#---------------------------------------------------------------------- +# set the image output directory here +#---------------------------------------------------------------------- +IMG_BASE_DIR = $(PRJ_NAME)_Data + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +LIB_BASE_DIR = ../../LIB + +#---------------------------------------------------------------------- +# set the library directory here +#---------------------------------------------------------------------- +ARC_BASE_DIR = $(ROOT_DIR)/ARC + +#---------------------------------------------------------------------- +# add additional C and assembly flags here, for example, -O2 +#---------------------------------------------------------------------- +C_DEFINE_EXT = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(BL_LDADDR_PARAM) \ + $(EXTSTRG_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(SPIPINMUX_PARAM)\ + $(EMMCPINMUX_PARAM)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) \ + $(BL_STORAGEINT_PARAM) \ + $(SECURE_DECRYPT_UBOOT_PARAM) \ + $(SECURE_DECRYPT_OPTEE_PARAM) \ + $(CARDDET_PIN_PARAM) + +CFLAGS_R = $(C_DEFINE_EXT) +CFLAGS_D = $(C_DEFINE_EXT) + +ASMFLAGS_R = \ + $(BL_COMPRESS_PARAM_ASM) + +ASMFLAGS_D = \ + $(BL_COMPRESS_PARAM_ASM) + +GCCFLAGS = \ + $(MODEL_PARAM) \ + $(BL_UPDATE_NAME_PARAM) \ + $(BL_STRINGS_PARAM) \ + $(BL_COMPRESS_PARAM) \ + $(CHKFWIMAGE_PARAM) \ + $(FWCOMPRESS_PARAM) \ + $(BL_LOADER_VER_PARAM) \ + $(STORAGE_INT_TYPE)\ + $(DRAMSCAN_PARAM)\ + $(BL_DUTY_CALIBRATION_PARAM)\ + $(BL_DUTY_CALIBRATION_TYPE_PARAM)\ + $(BL_LOADER_FLOW_PARAM) + +#---------------------------------------------------------------------- +# include common parts of the makefile +#---------------------------------------------------------------------- +MAKE_COMMON_DIR = ../../MakeCommon +include $(MAKE_COMMON_DIR)/OutputImg.txt diff --git a/loader/Project/Model/ModelConfig.txt b/loader/Project/Model/ModelConfig.txt new file mode 100755 index 000000000..1ccf9d20a --- /dev/null +++ b/loader/Project/Model/ModelConfig.txt @@ -0,0 +1,5 @@ +#---------------------------------------------------------------------- +# Set model here +#---------------------------------------------------------------------- +# EMU_EVB => Model config as NT9856x +MODEL = EMU_EVB \ No newline at end of file diff --git a/loader/Project/Model/ModelConfig_EMU_EVB.txt b/loader/Project/Model/ModelConfig_EMU_EVB.txt new file mode 100755 index 000000000..2e1f88474 --- /dev/null +++ b/loader/Project/Model/ModelConfig_EMU_EVB.txt @@ -0,0 +1,200 @@ +BIN_NAME = LD98$(CHIP_SHORT)A +BL_UPDATE_FWNAME = FW98$(CHIP_SHORT)A.BIN +BL_RUN_FWNAME = FW98$(CHIP_SHORT)T.BIN + +# Ext => DRAM is external die => Need user configuration +# KGD => DRAM is internal die => Depend on specific chip (force fixed dram size) +#===========+================+==================+ +# chip_name | DDR1 size | DDR1 clock | +#===========+================+==================+ +# 560 |1024 ~ 8192(Mb) | 507, 760, 933 | +#===========+================+==================+ +# 562 |512(Mb) | 522, 666 | +#===========+================+==================+ +# 563 |512(Mb) | 522, 666 | +#===========+================+==================+ +# 566 |1024(Mb) | 507, 760, 933 | +#===========+================+==================+ +# 565 |1024(Mb) | 507, 760, 933 | +#===========+================+==================+ +# [CHIP] : main chip ID +#560 +#562 +#563 +#566 +#565 +CHIP = 565 + +# [CHIP_VER] : chip version +# A +# B +#CHIP_VER = A + +# [DRAM1_CLK] : DRAM1(16-bit) clock rate +# 507 +# 522 +# 666 +# 760 +# 933 +DRAM1_CLK = 933 + +# [SDRAM_SIZE] : DRAM Size (unit: Giga bit) +# 512(Mb) +# 1024 +# 2048 +# 4096 +SDRAM_SIZE = 512 + +# [DRAM1_POWEROFF_S3] : PCB support powered off S3 +# Normal +# Enabled +#DRAM1_POWEROFF_S3 = Normal + +# [DRAM_TYPE] : DRAM Type +# DDR3 +# DDR3L +DRAM_TYPE = DDR3 + +# [DRAM_2ND_TBL_DETECT] : enable DRAM 2nd table detect by GPIO (default: P_GPIO13) +# Normal (No GPIO detected) +# 0 (C_GPIO) +# 1 (P_GPIO) +# 2 (S_GPIO) +# 3 (L_GPIO) +# 4 (D_GPIO) +# 5 (HSI_GPI0) +# 6 (ADC_GPIO) +# 7 (DSI_GPI0) +# 8 (Reserved) +DRAM_2ND_TBL_DETECT = Normal + +# [DRAM_2ND_TBL_DETECT_GPIO_NO] : enable DRAM 2nd table detect by X_GPIO_n +# where +# C_GPIO --> n=0~22 +# P_GPIO --> n=0~25 +# S_GPIO --> n=0~8 +# L_GPIO --> n=0~9 +# D_GPIO --> n=0~7 +# HSI_GPI0 --> n=0~11 +# ADC_GPIO --> n=0~2 +# DSI_GPIO --> n=0~10 +DRAM_2ND_TBL_DETECT_GPIO_NO = 0 + +# [DRAM1_2ND_CLK] : DRAM1(16-bit) 2nd table clock rate +# 507 +# 760 +# 933 +DRAM1_2ND_CLK = 760 + +# [SDRAM_2ND_SIZE] : 2nd table DRAM Size (unit: Giga bit) +# 1024 +# 2048 +# 4096 +SDRAM_2ND_SIZE = 4096 + +# [DDR_TREFI] : ddr refresh time select by temparature range +# Normal(3.9 us) +# Extend(1.95 us) +DDR_TREFI = Normal + +# [DRAM_PLL_SSC] : enable DRAM PLL spread spectrum +# Normal +# 1 (0.1%) +# 2 (0.2%) +# 3 (0.3%) +# 4 (0.4%) +# 5 (0.5%) +DRAM_SSC_ENABLE = Normal + +# [DRAM_ODT] : enable DRAM ODT or not +# Normal +# Enable +# Disable +DRAM_ODT = Normal + +# [STORAGEINT] : internal storage device +# NandSpi +# SpiFlash +# EMMC +# EMMC_NAND_COMBO >>>[eMMC & NandSpi 2 in 1 & STORAGEEXT must choose NONE]<<< +STORAGEINT = SpiFlash + +# [SPI_SETTING] : SPI pinmux setting (Valid when STORAGEINT is NandSpi or SpiFlash) +# SPI_NORMAL +# SPI_4BITS +SPI_SETTING = SPI_4BITS + +# [STORAGEEXT] : external storage device +# NONE +# Sdio1 +# Usb +# Eth >>>[During this option => STORAGEINT MUST not choose @EMMC_NAND_COMBO]<<< +# Uart +STORAGEEXT = Sdio1 + +#==============================================================================# +# ROM decrypt loader option # +#==============================================================================# +# [SECUREBOOT] : Secure boot enable or not(Generate loader for secure boot) +# Normal +# Secure +SECUREBOOT = Normal + +# [SIGNATUREMETHOD] : Digital signature method (Only valid when SECUREBOOT = Secure ) +# AES128 +# RSA2048 +SIGNATUREMETHOD = AES128 + +# [ENCRYPTIONDATA] : Is data area encrypt ? (Only valid when SECUREBOOT = Secure ) +# Normal +# AES128 +ENCRYPTDATA = Normal + +# [AES key path] : Set absolute path of AES key configuration file +ifeq "$(shell uname)" "Linux" +#AES_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +AES_KEY_FILE_DIR = ../../Tools/Bin/aes.txt +else +AES_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [RSA key path] : Set absolute path of RSA key configuration file +ifeq "$(shell uname)" "Linux" +#RSA_KEY_FILE_DIR = /home/nvt00607/NT96680/01_Loader/na51000_loader_smp_crypto_190320_v2/Tools/Bin/aes.txt +RSA_PUB_KEY_FILE_DIR = ../../Tools/Bin/rsa_pub.txt +RSA_PRV_KEY_FILE_DIR = ../../Tools/Bin/rsa_priv.txt +else +RSA_KEY_FILE_DIR = Y:/NT96680/01_Loader/na51000_loader_smp_crypto_190320/Tools/Bin/aes.txt +endif + +# [LOADER_DRAM_ADDR] : assign DRAM address used by loader (format 0xABCD) +# 0x1000000 +#LOADER_DRAM_ADDR = 0x01F00000 +LOADER_DRAM_ADDR = 0x1000000 + +#==============================================================================# +# loader decrypt uboot option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_UBOOT] : Loader decrypt uboot or not (Depend on uboot build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_UBOOT = Normal + +#==============================================================================# +# loader decrypt optee option # +#==============================================================================# +# [SECUREBOOT_DECRYPT_OPTEE] : Loader decrypt optee or not (Depend on optee build as cypher text or not) +# Normal +# Secure +SECUREBOOT_DECRYPT_OPTEE = Normal + +#==============================================================================# +# exFAT support(Once customer want to use exFAT, need get license from $MS ) # +#==============================================================================# +# [exFAT] : Loader support exFAT or not +# NONE +# EXFAT +EXFAT_FILESYSTEM_SUPPORT = EXFAT + + + diff --git a/loader/Project/Model/Run_R.bat b/loader/Project/Model/Run_R.bat new file mode 100755 index 000000000..a20cdd6a3 --- /dev/null +++ b/loader/Project/Model/Run_R.bat @@ -0,0 +1,6 @@ +@echo off +set CurrentDIR=%CD% +pushd C:\Program Files\teraterm +start ttpmacro.exe /V %CurrentDIR%\LoadCode.ttl %CurrentDIR:\=/% Release Resume +set CurrentDIR= +popd \ No newline at end of file diff --git a/loader/Project/Model/Src/UART/uart_upgrade.c b/loader/Project/Model/Src/UART/uart_upgrade.c new file mode 100755 index 000000000..5dd82bcde --- /dev/null +++ b/loader/Project/Model/Src/UART/uart_upgrade.c @@ -0,0 +1,212 @@ +#include +#include "constant.h" +#include "uart_upgrade.h" +#include "scsi_op.h" +#include "debug.h" +#include "debug.h" +#include "global.h" + + +#define _THUMB2 __attribute__((target("thumb2"))) + +UART_Verify_CB guiUARTCheck_cb; +UART_Vendor_CB guiUARTVendor_cb; +static int uartrom_exit = 0; +static unsigned int chipid = 0; +static CONSOLE_OBJ *m_console = NULL; +static INT32U nvtuart_opened = 1; + +_THUMB2 static INT32U calc_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + return sum & 0xFFFF; +} + +_THUMB2 static INT32U make_sum(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum = 0; + + sum = (dat0 & 0xFFFF) + ((dat0 >> 16)) + (dat1 & 0xFFFF) + ((dat1 >> 16)) + + (dat2 & 0xFFFF) + ((dat2 >> 16)) + (dat3 & 0xFFFF) + ((dat3 >> 16)) + 28; + + sum = (~sum + 1) & 0xFFFF; + + return sum; +} + +_THUMB2 static int recv_data(char *p, unsigned int len) +{ + while (len) { + *p = m_console->getc(); + p++; + len--; + } + return 0; +} + +_THUMB2 static int send_data(char *p, unsigned int len) +{ + while (len) { + m_console->putc(*p); + p++; + len--; + } + return 0; +} + +_THUMB2 static void uart_send_csw(INT32U *cdb, int er) +{ + char *p_cdb = (char *)cdb; + p_cdb[IDX_CDB_UART_STATUS_ER] = er; + + unsigned int sum = make_sum(cdb[0], cdb[1], cdb[2], (cdb[3] & 0xFFFF)); + cdb[3] |= sum << 16; + + send_data((char *)cdb, sizeof(INT32U) * 4); +} + + +_THUMB2 static int uart_cmd(INT32U *cdb) +{ + unsigned int cmd_id = ((cdb[0] >> 8) & 0xFF); + unsigned int insize = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); + unsigned int tmp1, tmp2; + + switch (cmd_id) { + case SCSIOP_OUT_OPEN_DEVICE: + nvtuart_opened = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_WAIT_DONE: + uartrom_exit = 1; + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_IS_NVT: + chipid = uart_read_reg(TOP_CTRL_VERSION_REG); + uart_send_csw(cdb, 0); + send_data((char *)&chipid, sizeof(chipid)); + break; + + case SCSIOP_OUT_ADDR_WRITE: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = ((cdb[1] >> 16) & 0xFFFF) + ((cdb[2] & 0xFFFF) << 16); //data + *(INT32U *)tmp1 = tmp2; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + break; + + case SCSIOP_IN_ADDR_READ: + tmp1 = ((cdb[0] >> 16) & 0xFFFF) + ((cdb[1] & 0xFFFF) << 16); //addr + tmp2 = *(INT32U *)tmp1; + __asm__ __volatile__("dsb\n\t"); + uart_send_csw(cdb, 0); + send_data((char *)&tmp1, sizeof(tmp2)); //repeat addr + send_data((char *)&tmp2, sizeof(tmp2)); //reply data + break; + + default: + if (guiUARTCheck_cb != NULL) { + NVT_SCSI_CBW cbw; + unsigned int OutDataBuf = 0; + utl_memset(&cbw, 0, sizeof(cbw)); + cbw.dCBWDataTransferLength = insize; + utl_memcpy(cbw.CBWCB, cdb, 4 * sizeof(unsigned int)); + int er = guiUARTCheck_cb((unsigned int)&cbw, (unsigned int *)&OutDataBuf, (unsigned int *)&insize); + utl_memcpy(cdb, cbw.CBWCB, 4 * sizeof(unsigned int)); + if (er != 0) { + uart_send_csw(cdb, 1); + return -1; + } else { + uart_send_csw(cdb, 0); + } + if ((cmd_id & 0x80)) { + //dir-in + guiUARTVendor_cb((unsigned int)&cbw); + if (insize) { + send_data((char *)OutDataBuf, insize); + } + } else { + //dir-out + if (insize) { + recv_data((char *)OutDataBuf, insize); + } + guiUARTVendor_cb((unsigned int)&cbw); + } + } + break; + + } + return 0; +} + +_THUMB2 static void uart_upgrade_routine(void) +{ + static int idx_cdb = 0; + static INT32U cdb[4] = {0}; + + char *p_cdb = (char *)cdb; + + p_cdb[idx_cdb++] = m_console->getc(); + + // loop to cdb fill 16 bytes + if (idx_cdb < 16) { + return ; + } + + idx_cdb = 0; // reset idx + + // Parse SCSI command + if (!(((cdb[0] & 0xFF) == SCSI_OP_SET0) || ((cdb[0] & 0xFF) == SCSI_OP_SET1) || ((cdb[0] & 0xFF) == SCSI_OP_SET2))) { + uart_send_csw(cdb, 1); + debug_err("uart opset ng.\r\n"); + } + + if (calc_sum(cdb[0], cdb[1], cdb[2], cdb[3]) != 0) { + uart_send_csw(cdb, 1); + debug_err("uart cmd sum ng.\r\n"); + return; + } + + uart_cmd(cdb); +} + +_THUMB2 void uart_upgrade_procedure() +{ + //if(utl_get_chipversion() != CHIPVER_A) { + m_console = get_uart_object(CONSOLE_UART0); + // } else { + // m_console = get_uart_object(CONSOLE_UART1); + //} + + m_console->hook(); + + while (1) { + + if (uartrom_exit > 0) { + break; + } + + uart_upgrade_routine(); + } + + uartrom_exit = 0; + +} + +_THUMB2 void loader_installUART_Verify_CB(UART_Verify_CB callback) +{ + guiUARTCheck_cb = callback; +} + +_THUMB2 void loader_installUART_Vendor_CB(UART_Vendor_CB callback) +{ + guiUARTVendor_cb = callback; +} + + diff --git a/loader/Project/Model/Src/UART/uart_upgrade.h b/loader/Project/Model/Src/UART/uart_upgrade.h new file mode 100755 index 000000000..499f05d30 --- /dev/null +++ b/loader/Project/Model/Src/UART/uart_upgrade.h @@ -0,0 +1,101 @@ +#ifndef __UART_UPGRADE_H +#define __UART_UPGRADE_H + +/** + Open NVT Device + + The commands except SCSIOP_IN_IS_NVT can be run if open device success. + If not open first, the operation commands got CSW Status 0x1 means command failed. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_OPEN_DEVICE 0x01C0 + + +/** + Send Write Loader + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[16] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: OUT. Size is at CBW[8]~[11] DataTransferLength. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_WRLOADER 0x02C0 + +/** + Address WRITE WORD (DRAM/REG/SRAM dont care) + + The Write Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + The Write DATA @ CDB[6]~[9]. + For example address 0x12345678 shall fill CDB[6]=0x78 CDB[7]=0x56 CDB[8]=0x34 CDB[9]=0x12 + CDB[10]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_OUT_ADDR_WRITE 0x03C0 + +/** + Address READ WORD (DRAM/REG/SRAM dont care) + + The READ Address @ CDB[2]~[5]; + For example address 0xFE080000 shall fill CDB[2]=0x00 CDB[3]=0x00 CDB[4]=0x08 CDB[5]=0xFE + CDB[6]~[15] shall follow checksum rule. Content is dont care. + + @DATA_PHASE: IN 8 bytes return. DATA[0]~[3] is repeat CDB address. Read out DATA is [3] ~[7]. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. +*/ +#define UARTOP_IN_ADDR_READ 0x83C0 + + +/** + Ask if NVT Device + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: IN 4 bytes return; The value 0x81200000 woule be return for 98321. <8321 = 0x2081> If checksum fail, the 0x0 would be returned. + @CSW_PHASE status code: 0 is success. 0x1 means checksum failed. + +*/ +#define UARTOP_IN_IS_NVT 0x81C0 // ???O???O???a?? device (?o?????n?? SCSIOP_IN_OPEN_DEVICE) + + +/** + End USB ROM CODE. + + Exit USB ROM code after receiving this command. The checksum must be correct. + + CDB[2]~[15] shall follow checksum rule + + @DATA_PHASE: None. + @CSW_PHASE status code: 0 is success and end usb rom. 0x1 means checksum failed. +*/ +#define UARTOP_IN_WAIT_DONE 0x82C0 + +#define TOP_CTRL_VERSION_REG (0xF00100F0) + + +typedef int (*UART_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*UART_Vendor_CB)(unsigned int pCmdBuf); ///< Callback for Vendor Command processing + + +extern void loader_installUARTCB(UART_Verify_CB callback); +extern void uart_upgrade_procedure(void); + +static __inline unsigned int uart_read_reg(unsigned int reg) +{ + return *((volatile unsigned int *)reg); +} + +static __inline void uart_write_reg(unsigned int reg, unsigned int value) +{ + *((volatile unsigned int *)reg) = value; +} + + + +#endif diff --git a/loader/Project/Model/Src/USB/usb_update.c b/loader/Project/Model/Src/USB/usb_update.c new file mode 100755 index 000000000..0e9ac0c85 --- /dev/null +++ b/loader/Project/Model/Src/USB/usb_update.c @@ -0,0 +1,1231 @@ + +//#include "board.h" +#include "fuart.h" +#include "usb_update.h" +#include "debug.h" +#include "timer.h" + +#define IOADDR_USB_REG_BASE (0xFF600000) +#define _THUMB2 __attribute__((target("thumb2"))) + + +_THUMB2 void fLib_USB_Update_FW(void); + +int usbrom_exit = 0; +volatile DEV *ptusbdev; +#define ptotg ((volatile OTG200 *)IOADDR_USB_REG_BASE) + +#define FUSB200_MAX_EP 8 // 1..10 +#define FUSB200_MAX_FIFO 4 // 0.. 9 + +#define mUsbEPMap(EPn, MAP) (ptusbdev->ep_map[EPn-1] = MAP) +#define mUsbEPMapRd(EPn) (ptusbdev->ep_map[EPn-1]) + +#define mUsbFIFOMap(FIFOn, MAP) (ptusbdev->fifo_map[FIFOn] = MAP) +#define mUsbFIFOMapRd(FIFOn) (ptusbdev->fifo_map[FIFOn]) +#define mUsbFIFOConfigRd(FIFOn) (ptusbdev->fifo_cfg[FIFOn]) + +static USB_st tusb; +static MassStorageState eUsbMassStorageState = MS_STATE_CBW; +CBW tCBW; +CSW tCSW; +SCSISense tSCSIsense; +SCSIDeviceResp tSCSIDeviceResp; + +MSDC_Verify_CB guiU2MsdcCheck_cb; +MSDC_VenDone_CB guiU2MsdcVendorDone_cb; + +int trigger_done_cb = 0; + +static const unsigned char u8RequestSenseData[DATA_LENGTH_REQUEST_SENSE] __attribute__((aligned(4))) = +{ + 0x70, // 0, response code + 0x00, // 1, obsolete + 0x00, // 2, sense key + 0x00, // 3-6, information + + 0x00, + 0x00, + 0x00, + 0x0A, // 7, additional length (n - 7), n = 17 + + 0x00, // 8-11, information + 0x00, + 0x00, + 0x00, + + 0x00, // 12, additional sense code + 0x00, // 13, additional sense code qualifier + 0x00, // 14, field replaceable unit code + 0x00, // 15-17, sense-key specific + + 0x00, + 0x00 +}; + + +static const unsigned char u8ModeSenseData[DATA_LENGTH_MODE_SENSE] __attribute__((aligned(4))) = +{ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + + +#define USB_BUFF_SZ 128 +unsigned int u32Usb_buffer[USB_BUFF_SZ/4]; // may less than USB_BUFF_SZ + +static INT32U nvtdev_opened = 1; +#define mCxType(cmd) ((cmd[0] & (BIT6 | BIT5)) >> 5) +#define mCxRequest(cmd) ((unsigned char)(cmd[0] >> 8)) +#define mCxValue(cmd) ((unsigned short)(cmd[0] >> 16)) // get 3rd byte, 4th byte +#define mCxIndex(cmd) ((unsigned short)(cmd[1])) // get 5th byte, 6th byte +#define mCxLength(cmd) ((unsigned short)(cmd[1] >> 16)) // get 7th byte, 8th byte + + +#define mUsbRmWkupST() (ptusbdev->main_ctl & BIT0) +#define mUsbRmWkupClr() (ptusbdev->main_ctl &= ~BIT0) +#define mUsbRmWkupSet() (ptusbdev->main_ctl |= BIT0) +#define mUsbTsMdWr(item) (ptusbdev->phy_tms = item) +#define mUsbIntF2OUTDis() (ptusbdev->int_mgrp1 |= (BIT5 | BIT4)) +#define mUsbIntF2OUTEn() (ptusbdev->int_mgrp1 &= ~(BIT5 | BIT4)) +#define mUsbIntF0INDis() (ptusbdev->int_mgrp1 |= BIT16) +#define mUsbIntF0INEn() (ptusbdev->int_mgrp1 &= ~BIT16) +// Endpoint & FIFO Configuration +#define mUsbEPMxPtSz(EPn, dir, size) (ptusbdev->ep_xpsz[dir][EPn - 1] = size) +#define mUsbEPStallST(EPn, dir) (((ptusbdev->ep_xpsz[dir][EPn - 1]) & BIT11) >> 11) +#define mUsbEPRsTgSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT12) +#define mUsbEPRsTgClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT12) +#define mUsbEPStallClr(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] &= ~BIT11) +#define mUsbEPStallSet(EPn, dir) (ptusbdev->ep_xpsz[dir][EPn-1] |= BIT11) + +extern void CPUflushReadCache(UINT32 uiStartAddr, UINT32 uiLength); +extern void CPUflushWriteCache(UINT32 uiStartAddr, UINT32 uiLength); + +INT32S my_SCSICmd(CBW * ptcbw); + +_THUMB2 signed int usb_DxFifoRdWr(unsigned char * buf, unsigned int count, unsigned int Rd) +{ + signed int ret = -1; // assume fail + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: enter usb_DxFifoRdWr\r\n"); + //#endif + + CPUflushWriteCache((UINT32) buf, (UINT32) count); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //#ifdef __FREERTOS + //if(buf == (unsigned char *)0xFE080000) + // ptusbdev->dma_addr = (INT32U)buf; + //else + // ptusbdev->dma_addr = dma_getPhyAddr(buf); + + //dma_flushWriteCache((UINT32)buf, count); + //dma_flushReadCache((UINT32)buf, count); + //#else + ptusbdev->dma_addr = (INT32U)buf;//dma_getPhyAddr(buf); + + __asm__ __volatile__("dsb\n\t"); + //#endif + + + if (Rd) { + // fifo select + ptusbdev->dma_fifo = BIT2; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (0 << 1); // fifo 2 memory + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: count = %d, Read CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + + } else { + // fifo select + ptusbdev->dma_fifo = BIT0; + // ctrl setting + ptusbdev->dma_ctl = (count << 8) | // dma byte count + (0 << 2) | // not dma io to io + (1 << 1); // memory 2 fifo + + #ifdef USBROM_RTOS_DBG + debug_msg("MSG: Write count = %d, Write CTRL = %x\r\n", count, ptusbdev->dma_ctl); + #endif + } + + // dma start + ptusbdev->dma_ctl |= BIT0; + + while (1) { + INT32U temp; + + temp = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (temp & BIT7) { // dma completion + ret = 0; // ok + break; + } + if (temp & (BIT2 | BIT1)) { // bus condiction + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + if (temp & BIT8) { // dma error + // clear cx fifo + ptusbdev->cx_cf |= BIT3; + break; + } + } + + // clear (dma error & dma completion) interrupt + ptusbdev->int_grp2 |= (BIT8 | BIT7); + CPUflushReadCache((UINT32) buf, (UINT32) count); + + //debug_msg("done\r\n"); + + //#ifdef __FREERTOS + //dma_flushReadCache((UINT32)buf, count); + //#endif + + return ret; +} + +_THUMB2 void vSCSIHWError(void) +{ + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_OUT) { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } else { + //debug_msg("S1\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + } + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: vSCSIHWError\r\n"); + //#endif + + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; +} + + +////////////////////////////////////////////////////////////////////////////////// +_THUMB2 MassStorageState eScsiIn(void) +{ + + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + // unit: byte + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) { + // wait for fifo empty + while ((ptusbdev->cx_cf & (BIT8 | BIT9)) != (BIT8 | BIT9)) { + // if (VBUS == 0) + // return MS_STATE_CSW; + } + //debug_msg("S2\r\n"); + //mUsbEPStallSet(IN_EP, DIRECTION_IN); // case MS13Case_5: + } + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 0) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_IN); // case MS13Case_11: + } + break; + + + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + + +////////////////////////////////////////////////////////////////////////////////// +_THUMB2 MassStorageState eScsiOut(void) +{ + switch (tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + if (usb_DxFifoRdWr((INT8U *)u32Usb_buffer, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + if (tCSW.u32DataResidue) + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + return MS_STATE_CSW; + } + break; + + case CARD_INDEX_FSM_SS: + if (usb_DxFifoRdWr((INT8U *)tSCSIDeviceResp.u32IOAddr, tSCSIDeviceResp.u16DataResidue, 1) >= 0) { + tCSW.u32DataResidue -= tSCSIDeviceResp.u16DataResidue; + return MS_STATE_CSW; + } else { + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); // case MS13Case_11: + } + break; + default: + break; + } + vSCSIHWError(); + return MS_STATE_CSW; +} + +typedef unsigned int size_t; +extern void *utl_memcpy(void *dest, const void *src, size_t count); + +_THUMB2 void vSCSICmd_RequestSense(void) +{ + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = sizeof(u8RequestSenseData); + + // copy response to sram + utl_memcpy ((UINT32 *)u32Usb_buffer, (UINT32 *)u8RequestSenseData, (UINT32)sizeof(u8RequestSenseData)); + + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_KEY>>2)) += (tSCSIsense.u8Key&0xFF)<<16; + *((unsigned int *)u32Usb_buffer + (SENSE_OFFSET_ADD>>2)) += (tSCSIsense.u8KeyAdd&0xFF); + + // all key disappear + tSCSIsense.u8Key = KEY_NO_SENSE; + tSCSIsense.u8KeyAdd = ADDKEY_NO_ADDITIONAL; +} + +_THUMB2 void vSCSICmd_ModeSense(void) +{ + + //switch (tCBW.u8CB[2]) { + switch ((tCBW.CB1_CB15[0]>>8)&0xFF) { + case 0x00: // return mode parameter header and block descriptor + //debug_msg("MODE_SENSE 00\r\n"); + tSCSIDeviceResp.u16DataResidue = 0x0C; + break; + case 0x3F: // all pages + //debug_msg("MODE_SENSE 3F\r\n"); + tSCSIDeviceResp.u16DataResidue = sizeof(u8ModeSenseData); + break; + default: + //debug_msg("MODE_SENSE ERR\r\n"); + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_FIELD_IN_CMD; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + return; + } + // Device intend to send data + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + + // copy response to sram + utl_memcpy((UINT32 *)u32Usb_buffer, (UINT32 *)u8ModeSenseData, (UINT32)tSCSIDeviceResp.u16DataResidue); +} + + + +_THUMB2 void vSCSICmd_Unsupport(void) +{ + // Device intend to transfer no data + tSCSIsense.u8Key = KEY_ILLEGAL_REQUEST; + tSCSIsense.u8KeyAdd = ADDKEY_INVALID_CMD_OP_CODE; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + + //#ifdef DISPLAY_USB_INFORMATION + //DBG_DUMP("MSG: UnSupported SCSI Command (op code = 0x%x)\r\n", tCBW.u8CB[0]); + //#endif +} + +_THUMB2 MassStorageState eMassStorage13case(void) +{ + MassStorage13Case eCase = 0x0; + MassStorageState estate; + INT32U u32DeviceRespDataLength = 0x0; + + switch(tSCSIDeviceResp.u8MemIndex) { + case CARD_INDEX_SRAM: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + tSCSIDeviceResp.u32IOAddr += tSCSIDeviceResp.u16TfSzCurrent; + break; + case CARD_INDEX_FSM_SS: + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue; + break; + default:// SPI + u32DeviceRespDataLength = tSCSIDeviceResp.u16DataResidue * 2112; + break; + } + + // Mass Storage the thirteen case + if (tCBW.u32DataTransferLength == u32DeviceRespDataLength) { + // normal case + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_1; // MassStorage case (1) + else { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == tSCSIDeviceResp.u8Flags) { + if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) + eCase = MS13Case_6; // MassStorage case (6) + else + eCase = MS13Case_12; // MassStorage case (12) + } + } + + //#ifdef DISPLAY_USB_INFORMATION + // vShowSCSI(); + //#endif + + } else { + if (tCBW.u32DataTransferLength == 0) + eCase = MS13Case_2_3; // MassStorage case (2)(3) + else if ((tCBW.CB0_cblen_lun_flag&0xFF) == CBW_FLAG_IN) { + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_4; // MassStorage case (4) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_IN) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_5; // MassStorage case (5) + else + eCase = MS13Case_7_8; // MassStorage case (7)(8) + } + } + else { //tCBW.u8Flags == CBW_FLAG_OUT + if (u32DeviceRespDataLength == 0) + eCase = MS13Case_9; // MassStorage case (9) + else if (tSCSIDeviceResp.u8Flags == CBW_FLAG_OUT) { + if (tCBW.u32DataTransferLength > u32DeviceRespDataLength) + eCase = MS13Case_11; // MassStorage case (11) + else + eCase = MS13Case_10_13; // MassStorage case (10)(13) + } + } + +//#ifdef DISPLAY_USB_INFORMATION +// { + //vShowUsb(); +// DBG_DUMP("MSG: MS13Case = 0x%x\r\n", eCase); +// DBG_DUMP("MSG: , u32DeviceRespDataLength = 0x%x\r\n", u32DeviceRespDataLength); +// } +//#endif + + } + + // assume the next state is STATE_CSW + estate = MS_STATE_CSW; + switch (eCase) { + case MS13Case_2_3: + //debug_msg("S3\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_4: + //debug_msg("S4\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + case MS13Case_5: + case MS13Case_6: + estate = eScsiIn(); + break; + case MS13Case_11: + case MS13Case_12: + estate = eScsiOut(); + break; + case MS13Case_7_8: + //debug_msg("S5\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + break; + case MS13Case_9: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + break; + case MS13Case_10_13: + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + tCSW.u8Status = CSW_STATUS_PHASE_ERROR; + //debug_msg("S6\r\n"); + mUsbEPStallSet(IN_EP, DIRECTION_IN); + break; + default: // MS13Case_1; + // do nothing here + break; + } + return estate; +} + + +_THUMB2 MassStorageState eSCSI_CmdDecode(void) //trace, different from FUSB100-CardReader +{ + //debug_msg("eSCSI_CmdDecode\r\n"); + // Assume SCSI Response data length will be 0 + tSCSIDeviceResp.u16DataResidue = 0; + if (((tCBW.CB0_cblen_lun_flag >> 8)&0xFF) >= CARD_TYPE_MAX_REPORT) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_LOGICAL_UNIT_NOT_SUPPORT; + } else { + // Parse SCSI command + //switch (tCBW.u8CB[0]) { // Operation Code + switch ((tCBW.CB0_cblen_lun_flag >> 24)&0xFF) { // Operation Code + case SCSI_OP_REQUEST_SENSE: + vSCSICmd_RequestSense(); + //debug_msg("vSCSICmd_RequestSense\r\n"); + break; + case SCSI_OP_MEDIUM_REMOVAL: + //vSCSICmd_MediumRemoval(); + debug_msg("SCSI_OP_MEDIUM_REMOVAL\r\n"); + break; + case SCSI_OP_INQUIRY: + //vSCSICmd_Inquiry(); + debug_msg("SCSI_OP_INQUIRY\r\n"); + break; + case SCSI_OP_MODE_SENSE: + vSCSICmd_ModeSense(); + //debug_msg("SCSI_OP_MODE_SENSE 22\r\n"); + break; + + case SCSI_OP_TEST_UNIT_READY: + case SCSI_OP_READ_CAPACITY: + case SCSI_OP_READ_10: + case SCSI_OP_WRITE_10: + case SCSI_OP_VERIFY: + //debug_msg("SCSI_OP_TEST_UNIT_READY\r\n"); + tSCSIsense.u8Key = KEY_NOT_READY; + tSCSIsense.u8KeyAdd = ADDKEY_MEDIUM_NOT_PRESENT; + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + break; + + default: + if (my_SCSICmd(&tCBW) < 0) { + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: SCSI cmd: UNSUPPOR\r\n"); + //#endif + vSCSICmd_Unsupport(); + } + break; + } + } + return eMassStorage13case(); +} + + + + + +_THUMB2 MassStorageState eUsbProessCBW(void) +{ + usb_DxFifoRdWr((unsigned char *)&tCBW, 31, 1); + + if(tCBW.u32Signature != CBW_SIGNATE) { + return MS_STATE_CBW; + } else { + // pass u32DataTransferLength to u32DataResidue + tCSW.u32DataResidue = tCBW.u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: tCSW.u32DataResidue = %d, dir = %d\r\n", tCBW.u32DataTransferLength, tCBW.u8Flags); + #endif + + // pass Tag from CBW to CSW + tCSW.u32Tag = tCBW.u32Tag; + // Assume Status is CMD_PASS + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + return eSCSI_CmdDecode(); + } +} + +_THUMB2 void vUsbUnplug(void) +{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Unplug.. pls check\r\n"); + //#endif + // mUsbUnPlug(); + ptusbdev->phy_tms |= BIT0; +} + +_THUMB2 void vUsb_BulkIntOnOff(void) +{ + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: st 0x%x", eUsbMassStorageState); + //#endif + + switch(eUsbMassStorageState) + { + case MS_STATE_CBW: + mUsbIntF2OUTEn(); + mUsbIntF0INDis(); + break; + case MS_STATE_CB_DMA_IN: + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else + mUsbIntF0INEn(); + break; + case MS_STATE_CB_DMA_OUT: + mUsbIntF2OUTEn(); + break; + case MS_STATE_CSW: + mUsbIntF2OUTDis(); + if (mUsbEPStallST (IN_EP, DIRECTION_IN)) { + // wait for clear feature, and then enable F0 + } + else { + mUsbIntF0INEn(); + } + break; + case MS_STATE_BGD: + mUsbIntF2OUTDis(); + mUsbIntF0INDis(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error MS_STATE\r\n"); + //#endif + vUsbUnplug(); + break; + } +} + +_THUMB2 void vUsb_F0_In(void) +{ + switch(eUsbMassStorageState) + { + case MS_STATE_CSW: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 IN CSW\r\n"); + //#endif + + if (trigger_done_cb) { + trigger_done_cb = 0; + + if (guiU2MsdcVendorDone_cb != NULL) { + if (guiU2MsdcVendorDone_cb((unsigned int)&tCBW) != 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } + } + } + + usb_DxFifoRdWr((unsigned char *)&tCSW, 13, 0); + + //mUsbFIFODone(FIFO0); + eUsbMassStorageState = MS_STATE_CBW; + if(usbrom_exit == 1) + usbrom_exit = 2; + break; + case MS_STATE_CB_DMA_IN: + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP1 CS DMA IN\r\n"); + //#endif + eUsbMassStorageState = eScsiOut(); + break; + default: + //#ifdef USBROM_RTOS_DBG + debug_msg("MSG: Error FIFO0_IN interrupt.\r\n"); + //#endif + + break; + } + vUsb_BulkIntOnOff(); +} + +_THUMB2 void vUsb_F2_Out(unsigned int u32FIFOByteCount) +{ + switch(eUsbMassStorageState) { + case MS_STATE_CBW: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CBW\r\n"); + //#endif + + if (u32FIFOByteCount == 31) { + eUsbMassStorageState = eUsbProessCBW(); + } + else{ + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP out STAL SET\r\n"); + //#endif + + mUsbEPStallSet(OUT_EP, DIRECTION_OUT); + } + break; + case MS_STATE_CB_DMA_OUT: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: EP2 Out CB DMA Out\r\n"); + //#endif + + eUsbMassStorageState = eScsiOut(); + break; + default: + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: Error FIFO2_OUT interrupt.\r\n"); + //#endif + + break; + } + + vUsb_BulkIntOnOff(); +} + + + + +/////////////////////////////////////////////////////////////////////////////// +// bClear_feature() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/////////////////////////////////////////////////////////////////////////////// +_THUMB2 signed int usb_Clear_feature(void) +{ + unsigned int ep_n; + unsigned int fifo_n; + signed int bdir; + + switch (mCxValue (tusb.u32UsbCmd)) { // FeatureSelector + case 0: // ENDPOINT_HALE + // Clear "Endpoint_Halt", Turn off the "STALL" bit in Endpoint Control Function Register + if(mCxIndex (tusb.u32UsbCmd) == 0x00) + tusb.bUsbEP0HaltSt = FALSE; + else { + ep_n = mCxIndex (tusb.u32UsbCmd) & 0x7F; // which ep will be clear + // over the Max. ep count ? + if (ep_n > FUSB200_MAX_EP) + return -1; + // the direction of this ep + // bdir =0 if OUT + bdir = mCxIndex (tusb.u32UsbCmd) & BIT7;; + // get the relatived FIFO number + if (bdir) + fifo_n = mUsbEPMapRd(ep_n) & 0x0F; + else + fifo_n = mUsbEPMapRd(ep_n) >> 4; + // over the Max. fifo count ? + if (fifo_n >= FUSB200_MAX_FIFO) + return -1; + + // Check the FIFO had been enable ? + if ((mUsbFIFOConfigRd(fifo_n) & BIT5) == 0) + return -1; + // bdir =0 if IN, 1 if OUT + bdir = bdir ? 0: 1; + mUsbEPRsTgSet(ep_n, bdir); // Set Rst_Toggle Bit + mUsbEPRsTgClr(ep_n, bdir); // Clear Rst_Toggle Bit + mUsbEPStallClr(ep_n, bdir); // Clear Stall Bit + vUsb_BulkIntOnOff(); + } + break; + case 1 : // Device Remote Wakeup + // Clear "Device_Remote_Wakeup", Turn off the"RMWKUP" bit in Main Control Register + mUsbRmWkupClr(); + break; + case 2 : // Test Mode + // do not break here + default : + return -1; + } + tusb.eUsbCxAction = ACT_DONE; + return 0; +} + + + +_THUMB2 signed int usb_StandardCommand(void) +{ + switch (mCxRequest (tusb.u32UsbCmd)) { // by Standard Request codes + //case 0: // get status + // return (usb_Get_status()); + + case 1: // clear feature + return (usb_Clear_feature()); + + //case 3: // set feature + // return (usb_Set_feature()); + + //case 5: // set address + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_address()); + // break; + + //case 6: // get descriptor + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_descriptor()); + // break; + + //case 8: // get configuration + // if (!tusb.bUsbEP0HaltSt) + // vGet_configuration(); + // return 0; + + //case 9: // set configuration + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_configuration()); + // break; + + //case 10: // get interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Get_interface()); + // break; + + // case 11: // set interface + // if (!tusb.bUsbEP0HaltSt) + // return(usb_Set_interface()); + // break; + + case 2: // Reserved for further use + case 4: // Reserved for further use + case 7: // set descriptor, not support + case 12: // synch frame, not support + default: + break; + } + return -1; +} + +/////////////////////////////////////////////////////////////////////////////// +// vUsb_ep0setup() +// Description: +// 1. Read 8-byte setup packet. +// 2. Decode command as Standard, Class, Vendor or NOT support command +// input: none +// output: none +/////////////////////////////////////////////////////////////////////////////// +_THUMB2 void vUsb_ep0setup(void) +{ + /* + if(tusb.bUsbChirpFinish == 0) + { + // first ep0 command after usb reset, means we can check usb speed right now. + tusb.bUsbChirpFinish = 1; + + if (ptusbdev->main_ctl & BIT6) { + tusb.bHighSpeed = 1; + //DBG_DUMP("MSG: L%x, high speed mode\r\n", tusb.u8LineCount ++); + } + else { + tusb.bHighSpeed = 0; + //DBG_DUMP("MSG: L%x, full speed mode\r\n", tusb.u8LineCount ++); + } + // Init AP + vUsbMassStorageInit(); + } + */ + + // select dma target fifo no.: + //ptusbdev->dma_fifo = BIT4; + + // Read 8-byte setup packet from FIFO + tusb.u32UsbCmd[0] = ptusbdev->dma_data; + tusb.u32UsbCmd[1] = ptusbdev->dma_data; + + #if 0//def USBROM_RTOS_DBG + DBG_DUMP("MSG: L%x, EP0Cmd: %x %x %x %x %x %x %x %x\r\n", + tusb.u8LineCount ++, (INT8U)(tusb.u32UsbCmd[0] >> 0) + , (INT8U)(tusb.u32UsbCmd[0] >> 8) + , (INT8U)(tusb.u32UsbCmd[0] >> 16) + , (INT8U)(tusb.u32UsbCmd[0] >> 24) + , (INT8U)(tusb.u32UsbCmd[1] >> 0) + , (INT8U)(tusb.u32UsbCmd[1] >> 8) + , (INT8U)(tusb.u32UsbCmd[1] >> 16) + , (INT8U)(tusb.u32UsbCmd[1] >> 24)); + #endif + + // Command Decode + switch (mCxType(tusb.u32UsbCmd)) { + case 0: // standard command + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: Standard command\r\n"); + //#endif + + if (usb_StandardCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; +/* + case 1: // class command + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: class command\r\n"); + #endif + + if (usb_ClassCommand() < 0) + tusb.eUsbCxAction = ACT_STALL; + break; + + case 2: // vendor command + #ifdef USBROM_RTOS_DBG + DBG_DUMP("MSG: vendor command\r\n"); + #endif +// if (usb_UsbVendorCommand() < 0 + tusb.eUsbCxAction = ACT_STALL; + break; +*/ + default: + // Invalid(bad) command, Return EP0_STALL flag + tusb.eUsbCxAction = ACT_STALL; + break; + } +} + + + + +_THUMB2 void vUsbInit(void) +{ + ptusbdev = ((volatile DEV *)(IOADDR_USB_REG_BASE + 0x100)); + + // init variables + tusb.eUsbCxAction = ACT_IDLE; + tusb.bUsbChirpFinish = 0; + + tusb.u16TxRxCounter = 0; + tusb.eUsbCxCommand = CMD_VOID; + tusb.u8UsbConfigValue = 0; + tusb.u8UsbInterfaceValue = 0; + tusb.u8UsbInterfaceAlternateSetting = 0; + tusb.bUsbEP0HaltSt = FALSE; + + // init hardware + //vFUSB200Init(); + tusb.u8LineCount = 1; + + tCSW.u32Signature = CSW_SIGNATE; + eUsbMassStorageState = MS_STATE_CBW; + mUsbIntF2OUTEn (); + mUsbIntF0INDis(); + +} + + + +_THUMB2 void vUsbIsr2(void) +{ + INT32U level1; + INT32U level2; + + level1 = ptusbdev->int_grp & ~ ptusbdev->int_mgrp; + + if (0 == level1) + return; + + if (level1 & BIT2) { //Group 2 + + level2 = ptusbdev->int_grp2 & ~ ptusbdev->int_mgrp2; + + if (level2) { + + //debug_msg("MSG: IntSCR2\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: BUS RST\r\n"); + } + + if (level2 & BIT1) { + //debug_msg("MSG: BUS SUSPEND\r\n"); + ptusbdev->int_grp2 |= BIT1; + } + + if (level2 & BIT2) { + //debug_msg("MSG: BUS RESUME\r\n"); + ptusbdev->int_grp2 |= BIT2; + } + + if (level2 & BIT5) { + //debug_msg("MSG: TX0B\r\n"); + + ptusbdev->tx0byte |= 0; + ptusbdev->int_grp2 |= BIT5; + } + + if (level2 & BIT6) { + //debug_msg("MSG: RX0B\r\n"); + ptusbdev->rx0byte |= 0; + ptusbdev->int_grp2 |= BIT6; + } + + } + } + + + if (level1 & BIT0) { //Group 0 + level2 = ptusbdev->int_grp0 & ~ ptusbdev->int_mgrp0; + if (level2) { + //debug_msg("MSG: IntSCR0\r\n"); + + if (level2 & BIT0) { + //debug_msg("MSG: USB ep0 Setup\r\n"); + vUsb_ep0setup(); + } + else if (level2 & BIT3) { + //debug_msg("MSG: USB ep0 end\r\n"); + //vUsb_ep0end(); + } + if (level2 & BIT1) { + //debug_msg("MSG: USB ep0 TX\r\n"); + //vUsb_ep0tx(); + } + if (level2 & BIT2) { + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 RX\r\n"); + //#endif + //vUsb_ep0rx(); + } + if (level2 & BIT4) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: USB ep0 fail\r\n"); + //#endif + // stall cx: mUsbEP0StallSet(); + //ptusbdev->cx_cf |= BIT2; + } + if (level2 & BIT5) { + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: cmd abort\r\n"); + //#endif + ptusbdev->int_grp0 |= BIT5; + } + } + + + if (tusb.eUsbCxAction == ACT_STALL) { + ptusbdev->cx_cf |= BIT2; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 STALL\r\n"); + //#endif + } + else if (tusb.eUsbCxAction == ACT_DONE) { + ptusbdev->cx_cf |= BIT0; + + //#ifdef USBROM_RTOS_DBG + //DBG_DUMP("MSG: EP0 DONE\r\n"); + //#endif + } + // Clear Action + tusb.eUsbCxAction = ACT_IDLE; + + + } + + if (level1 & BIT1) { //Group Byte 1 + level2 = ptusbdev->int_grp1 & ~ ptusbdev->int_mgrp1; + + //#ifdef USBROM_RTOS_DBG + //debug_msg("MSG: IntSCR1\r\n"); + //#endif + + if (level2 & (BIT5 | BIT4)) { // F2 out (full or short) + vUsb_F2_Out(ptusbdev->fifo_bc[2]); + } + + if (level2 & BIT16) // F0 in + vUsb_F0_In(); + } +} + + + +_THUMB2 static INT32U calc_sum_v2(INT32U dat0, INT32U dat1, INT32U dat2, INT32U dat3) +{ + INT32U sum=0; + + sum = (dat0&0xFFFF)+((dat0>>16))+(dat1&0xFFFF)+((dat1>>16)) + + (dat2&0xFFFF)+((dat2>>16))+(dat3&0xFFFF)+((dat3>>16)) + 28; + + //DBG_DUMP("SUM = 0x%08X\r\n",sum); + return sum&0xFFFF; +} + +_THUMB2 INT32S my_SCSICmd(CBW * ptcbw) +{ + INT32U temp1, temp2; + INT32U CDB[4]; + + CDB[0] = ((ptcbw->CB0_cblen_lun_flag >> 24) & 0xFF) + ((ptcbw->CB1_CB15[0]&0xFFFFFF)<<8); + CDB[1] = ((ptcbw->CB1_CB15[0] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[1]&0xFFFFFF)<<8); + CDB[2] = ((ptcbw->CB1_CB15[1] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[2]&0xFFFFFF)<<8); + CDB[3] = ((ptcbw->CB1_CB15[2] >> 24) & 0xFF) + ((ptcbw->CB1_CB15[3]&0xFFFFFF)<<8); + + // Parse SCSI command + if (!(((CDB[0]&0xFF) == SCSI_OP_SET0)||((CDB[0]&0xFF) == SCSI_OP_SET1)||((CDB[0]&0xFF) == SCSI_OP_SET2))) + return -1; + + // check sum + if(calc_sum_v2(CDB[0],CDB[1],CDB[2],CDB[3])) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + u32Usb_buffer[0] = 0; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("CHKSUM FAILED\r\n"); + #endif + return -1; + } + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + + switch (((CDB[0] >> 8) &0xFF)) { + + case SCSIOP_OUT_OPEN_DEVICE: { + nvtdev_opened = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_OPEN_DEVICE\r\n"); + #endif + } + break; + + case SCSIOP_IN_WAIT_DONE: { + usbrom_exit = 1; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_WAIT_DONE\r\n"); + #endif + } + break; + + + case SCSIOP_IN_IS_NVT: { + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 4; + + tCSW.u8Status = CSW_STATUS_CMD_PASS; + u32Usb_buffer[0] = 0x70210000; + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_IS_NVT\r\n"); + #endif + } + break; + + case SCSIOP_OUT_ADDR_WRITE: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + // data + temp2 = ((CDB[1]>>16)&0xFFFF)+((CDB[2]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[6]); + + *(INT32U *)temp1 = temp2; + __asm__ __volatile__("dsb\n\t"); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_ADDR_WRITE 0x%08X 0x%08X\r\n", temp1, temp2); + #endif + } + } + break; + + case SCSIOP_IN_ADDR_READ: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_SRAM; + tSCSIDeviceResp.u16DataResidue = 8; + u32Usb_buffer[0] = temp1; + u32Usb_buffer[1] = *((INT32U *)temp1); + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_IN_ADDR_READ 0x%08X 0x%08X\r\n", temp1, u32Usb_buffer[1]); + #endif + } + } + break; +#if 0 //only rom code support + case SCSIOP_OUT_WRLOADER: { + + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + // address + temp1 = ((CDB[0]>>16)&0xFFFF)+((CDB[1]&0xFFFF)<<16);//u8to32(&ptcbw->u8CB[2]); + + tSCSIDeviceResp.u32IOAddr = temp1; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + + #ifdef USBROM_RTOS_DBG + DBG_DUMP("SCSIOP_OUT_WRLOADER 0x%08X 0x%08X\r\n", temp1, tSCSIDeviceResp.u16DataResidue); + #endif + + } + } + break; +#endif + default: { + if(nvtdev_opened == 0) { + tCSW.u8Status = CSW_STATUS_CMD_FAIL; + } else { + int ret = -1; + unsigned int OutDataBuf=0, insize=0; + + if (guiU2MsdcCheck_cb != NULL) { + ret = guiU2MsdcCheck_cb((unsigned int)ptcbw, (unsigned int *) &OutDataBuf, (unsigned int *)&insize); + } else { + ret = -1; + } + + if(ret == 0) { + + if (ptcbw->CB0_cblen_lun_flag & CBW_FLAG_IN) { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_IN; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = insize; + + } else { + tSCSIDeviceResp.u32IOAddr = OutDataBuf; + tSCSIDeviceResp.u8Flags = CBW_FLAG_OUT; + tSCSIDeviceResp.u8MemIndex = CARD_INDEX_FSM_SS; + tSCSIDeviceResp.u16DataResidue = ptcbw->u32DataTransferLength; + } + + trigger_done_cb = 1; + } else { + return ret; + } + } + } + break; + + } + + return 0; + +} + + + +_THUMB2 void fLib_USB_Update_FW(void) +{ + debug_msg("USBFW UPDATE\r\n"); + + vUsbInit(); + + while (1) { + + vUsbIsr2(); + + if(usbrom_exit > 1) { + //mdelay(300); //make sure that pc recevie scsi status + timer_delay(300000); + vUsbUnplug(); + timer_delay(300000); + //mdelay(300); //make sure that pc recevie usb plug-out single + break; + } + + } + + usbrom_exit = 0; + +} + diff --git a/loader/Project/Model/Src/USB/usb_update.h b/loader/Project/Model/Src/USB/usb_update.h new file mode 100755 index 000000000..dde457078 --- /dev/null +++ b/loader/Project/Model/Src/USB/usb_update.h @@ -0,0 +1,323 @@ + +#ifndef __USB_UPDATE_H +#define __USB_UPDATE_H +#include "scsi_op.h" + + +#define BIT0 0x00000001L +#define BIT1 0x00000002L +#define BIT2 0x00000004L +#define BIT3 0x00000008L +#define BIT4 0x00000010L +#define BIT5 0x00000020L +#define BIT6 0x00000040L +#define BIT7 0x00000080L +#define BIT8 0x00000100L +#define BIT9 0x00000200L +#define BIT10 0x00000400L +#define BIT11 0x00000800L +#define BIT12 0x00001000L +#define BIT13 0x00002000L +#define BIT14 0x00004000L +#define BIT15 0x00008000L +#define BIT16 0x00010000L +#define BIT17 0x00020000L +#define BIT18 0x00040000L +#define BIT19 0x00080000L +#define BIT20 0x00100000L +#define BIT21 0x00200000L +#define BIT22 0x00400000L +#define BIT23 0x00800000L + + +typedef int (*MSDC_Verify_CB)(unsigned int pCmdBuf, unsigned int *pDataBuf, unsigned int *IN_size); ///< Callback for verify the Vendor Command is supported or not +typedef int (*MSDC_VenDone_CB)(unsigned int pCmdBuf); ///< Callback for verify the Vendor Command is supported or not + + +// KEY_ILLEGAL_REQUEST: Additional key +#define ADDKEY_INVALID_CMD_OP_CODE 0x20 +#define ADDKEY_INVALID_FIELD_IN_CMD 0x24 + +#define CBW_FLAG_IN 0x80 +#define CBW_FLAG_OUT 0x00 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 ///1 +#define DIRECTION_OUT 1 ///0 + +#define EP0 0x00 +#define EP1 0x01 +#define EP2 0x02 +#define EP3 0x03 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 + +#define OUT_EP EP2 +#define IN_EP EP1 +#define OUT_FIFO FIFO2 +#define IN_FIFO FIFO0 + +typedef enum { + MS13Case_1 = 0, + MS13Case_2_3, + MS13Case_4, + MS13Case_5, + MS13Case_6, + MS13Case_7_8, + MS13Case_9, + MS13Case_10_13, + MS13Case_11, + MS13Case_12 +} MassStorage13Case; + +#define CBW_SIGNATE 0x43425355 +#define CSW_SIGNATE 0x53425355 +#define CSW_STATUS_CMD_PASS 0x00 +#define CSW_STATUS_CMD_FAIL 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +// Request Sense data format +#define SENSE_OFFSET_KEY 0x02 +#define SENSE_OFFSET_ADD 0x0C +#define SENSE_OFFSET_ADD_QUALIFIER 0x0D + +// KEY_NO_SENSE: Additional key +#define ADDKEY_NO_ADDITIONAL 0x00 + +// all response data length +#define DATA_LENGTH_INQUIRY 36 +#define DATA_LENGTH_REQUEST_SENSE 18 +#define DATA_LENGTH_MODE_SENSE 8 + +// SCSI command operation code +#define SCSI_OP_TEST_UNIT_READY 0x00 +#define SCSI_OP_REQUEST_SENSE 0x03 +#define SCSI_OP_INQUIRY 0x12 +#define SCSI_OP_MODE_SELECT 0x15 +#define SCSI_OP_MODE_SENSE 0x1A +#define SCSI_OP_MEDIUM_REMOVAL 0x1E +#define SCSI_OP_READ_FORMAT_CAPACITY 0x23 // unsupported +#define SCSI_OP_READ_CAPACITY 0x25 +#define SCSI_OP_READ_10 0x28 +#define SCSI_OP_WRITE_10 0x2A +#define SCSI_OP_VERIFY 0x2F + +#define CARD_INDEX_SRAM 7 +#define CARD_INDEX_FSM_SS 3 +#define CARD_TYPE_MAX_REPORT 1 + +// KEY_NOT_READY: Additional key +#define ADDKEY_LOGICAL_UNIT_NOT_READY 0x04 +#define ADDKEY_LOGICAL_UNIT_NOT_SUPPORT 0x25 +#define ADDKEY_MEDIUM_NOT_PRESENT 0x3A + +// Sense key +#define KEY_NO_SENSE 0x00 +#define KEY_RECOVERED_ERROR 0x01 +#define KEY_NOT_READY 0x02 +#define KEY_MEDIUM_ERROR 0x03 +#define KEY_HARDWARE_ERROR 0x04 +#define KEY_ILLEGAL_REQUEST 0x05 +#define KEY_UNIT_ATTENTION 0x06 +#define KEY_DATA_PROTECT 0x07 +#define KEY_BLANK_CHECK 0x08 +#define KEY_VENDOR_SPECIFIC 0x09 +#define KEY_COPY_ABORTED 0x0A +#define KEY_ABORTED_CMD 0x0B +#define KEY_OBSOLETE 0x0C +#define KEY_VOLUMN_OVERFLOW 0x0D +#define KEY_MISCOMPARE 0x0E +#define KEY_RESERVED 0x0F + +typedef struct // SCSI device response +{ + unsigned int u8MemIndex; // current access memory type + unsigned int u8Flags; // In or Out + unsigned int u32IOAddr; // block addr in Card controller + unsigned int u16DataResidue; // residue (block count for card content, or byte count for information) + unsigned int u16TfSzCurrent; // current transfer length (block count for card content, or byte count for information) +} SCSIDeviceResp; + +typedef struct SCSI_Sense_Data +{ + unsigned int u8Key; + unsigned int u8KeyAdd; +} SCSISense; + +typedef enum { + MS_STATE_IDLE = 0, + MS_STATE_CBW = 1, + MS_STATE_CB_DMA_IN = 2, + MS_STATE_CB_DMA_OUT = 3, + MS_STATE_CSW = 4, + MS_STATE_STALL = 5, + MS_STATE_BGD = 6 +} MassStorageState; + + +typedef struct CommandBlockWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataTransferLength; + unsigned int CB0_cblen_lun_flag; + unsigned int CB1_CB15[4]; + //unsigned char u8Flags; + //unsigned char u8LUN; + //unsigned char u8CBLength; + //unsigned char u8CB[16]; +} CBW; + +typedef struct CommandStatusWrapper +{ + unsigned int u32Signature; + unsigned int u32Tag; + unsigned int u32DataResidue; + unsigned int u8Status; +} CSW; + +// Host Controller (HC) +typedef struct { + INT32U cap; // 0x00: capability + INT32U ports; // 0x04: Structural Parameter + INT32U capp; // 0x08: capability Parameter + INT32U reserved1; // 0X0c + INT32U cmd; // 0x10: USB command + INT32U status; // 0X14: status + INT32U int_en; // 0X18: interrupt enable + INT32U fm_idx; // 0X1c: frame Index + INT32U reserved2; // 0x20 + INT32U periodic; // 0X24: periodic Frame List Base Address. must 4KB align. + INT32U asynch; // 0X28: Current Asynchronous List Address, must 32B align. + INT32U reserved3; // 0X2c + INT32U port; // 0x30: port status and Control + INT32U reserved4[3]; // 0X34 ~ 0X3c + INT32U misc; // 0x40 + INT32U reserved5[15]; // 0x44 ~ 0x7C +} HC; + +// OTG Controller (OTG) +typedef struct { + INT32U ctl_st; // 0x80: control/status + INT32U int_st; // 0x84: interrupt status + INT32U int_en; // 0x88: interrupt enable + INT32U reserved[13]; // 0x8C ~ 0xBC +} OTG; + +// Global Controller (GL) +typedef struct { + INT32U int_st; // 0xC0: interrupt status + INT32U interrupt; // 0xC4: interrupt mask + INT32U reserved[14]; // 0xC8 ~ 0xFC +} GL; + +// Device Controller (DEV) +typedef struct { + INT32U main_ctl; // 0x100: device main control + INT32U dev_adr; // 0x104: device address + INT32U tst_ep; // 0x108: device test + INT32U frm_no; // 0x10C: device SOF [13: 11] SOF micro frame number, [10: 0] SOF frame number + INT32U sof_tmsk; // 0x110: device SOF mask timer [15: 0] SOF mask timer + INT32U phy_tms; // 0x114: PHY test mode selector + INT32U vnd_ctl; // 0x118: vendor specific IO control + INT32U cx_cs; // 0x11C: CX configuration and status + INT32U cx_cf; // 0x120: CX configuration and FIFO empty status + INT32U idle_cnt; // 0x124: Device idel counter + INT32U cx_dataport; // 0x128: device cx data register + INT32U reserved1[1]; // 0x128 ~ 0x12C + INT32U int_mgrp; // 0x130: mask of interrupt group + INT32U int_mgrp0; // 0x134: mask of interrupt source group 0 + INT32U int_mgrp1; // 0x138: mask of interrupt source group 1 + INT32U int_mgrp2; // 0x13C: mask of interrupt source group 2 + INT32U int_grp; // 0x140: interrupt group + INT32U int_grp0; // 0x144: interrupt group 0 + INT32U int_grp1; // 0x148: interrupt group 1 + INT32U int_grp2; // 0x14C: interrupt group 2 + INT32U rx0byte; // 0x150: receive zero-length data packet + INT32U tx0byte; // 0x154: rtransfer zero-length data packet + INT32U iso_seq_err; // 0x158: iso. sequential error/abort + INT32U reserved2; // 0x15C + INT32U ep_xpsz[2][8]; // 0x160: IN endpoint x MaxPacketSize Reg + // 0x170: IN endpoint x MaxPacketSize Reg + // 0x180: OUT endpoint x MaxPacketSize Reg + // 0x190: OUT endpoint x MaxPacketSize Reg + INT8U ep_map[8]; // 0x1A0: endpoint 1 ~ 8 map Reg + INT8U fifo_map[4]; // 0x1A8: FIFO 0 ~ 3 map Reg + INT8U fifo_cfg[4]; // 0x1AC: FIFO 0 ~ 3 configuration + INT32U fifo_bc[4]; // 0x1B0: FIFO x instruction and byte count + INT32U dma_fifo; // 0x1C0: dma target FIFO number + INT32U reserved3; // 0x1C4 + INT32U dma_ctl; // 0x1C8: DMA controller parameter setting 1 + INT32U dma_addr; // 0x1CC: DMA controller parameter setting 2, address + INT32U dma_data; // 0x1D0: DMA controller parameter setting 3, Cx data +} DEV; + +// OTG Controller +typedef struct { + HC hc; // 0x00 ~ 0x7F + OTG otg; // 0x80 ~ 0xBF + GL gl; // 0xC0 ~ 0xFF + DEV dev; // 0x100 ~ 0x1FF +} OTG200; + + + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL, + + ACT_DUMMY = 0x80000000 +} Action; + +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR, // Set_Descriptor command + + CommandType_dummy = 0x80000000 +} CommandType; + +typedef struct USB_s +{ + // end pointer 0 information + unsigned int u32UsbCmd[8/4]; + unsigned int bUsbChirpFinish; + Action eUsbCxAction; + unsigned int u16TxRxCounter; + unsigned char * pu8Descriptor; + unsigned int u8UsbConfigValue; + unsigned int u8UsbInterfaceValue; + unsigned int u8UsbInterfaceAlternateSetting; + unsigned int bUsbEP0HaltSt; + unsigned int bHighSpeed; // high speed + CommandType eUsbCxCommand; + // for display + unsigned int u8LineCount; +} USB_st; + + + + + + + +#endif /* __USB_OTG_H */ + + + + + + diff --git a/loader/Project/Model/Src/prj_main.c b/loader/Project/Model/Src/prj_main.c new file mode 100755 index 000000000..342dbb886 --- /dev/null +++ b/loader/Project/Model/Src/prj_main.c @@ -0,0 +1,262 @@ +/* + Project layer Main control function + + This file is implement by user mode + + @file prj_main.c + + Copyright Novatek Microelectronics Corp. 2015. All rights reserved. +*/ + +#include "fuart.h" +#include "fat.h" +#include "rtc.h" +#include "timer.h" +#include "StorageDef.h" +#include "global.h" +#include "Clock.h" +#include "string.h" +#include "prj_main.h" +#include "debug.h" +#include "pad.h" + +#define _THUMB2 __attribute__((target("thumb2"))) + +/* 68CS */ +#if (MODEL == MODEL_68CS) +#define GPIO_KEY_OK C_GPIO_19 +#define GPIO_KEY_ISP C_GPIO_18 +#define GPIO_KEY_LEFT GPIO_KEY_ISP +#define GPIO_KEY_DOWN C_GPIO_20 +#define GPIO_KEY_MENU C_GPIO_21 +#define GPIO_KEY_UP C_GPIO_22 +#define GPIO_KEY_RIGHT C_GPIO_4 +#define GPIO_FASTBOOT_KEY GPIO_KEY_RIGHT +#define GPIO_SPECIAL_KEY GPIO_KEY_RIGHT +/* S530*/ +#elif (MODEL == MODEL_S530) +#define GPIO_KEY_TEST S_GPIO_6 +#define GPIO_FASTBOOT_KEY GPIO_KEY_TEST +#define GPIO_SPECIAL_KEY GPIO_KEY_TEST + +/* Unknown */ +#else +#error "Unknown Model" +#endif + + + + +#if defined(_STORAGEINT_EMMC_NAND_COMBO_) +#if (CHECK_CARD_EXIST == ENABLE) +#undef CHECK_CARD_EXIST +#define CHECK_CARD_EXIST DISABLE +#endif + +#endif + +extern UINT32 LoaderInternalInfo[]; + +#if (DEBUG_MSG == DISABLE) +//weak function mechanism for debug msg output +extern void debug_disable_msg(void); +void debug_disable_msg(void) {} +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) +/** + Check special key1(s) is(are) pressed. + + Check special key1(s) is(are) pressed or not. + + @return Key pressed status + - @b TRUE: Special key(s) is(are) pressed + - @b FALSE: Otherwise +*/ +static BOOL prj_isSpecialKeyPressed(void) +{ + // Detect key example, must press shutter2 and playback mode keys + // OUT_0: DGPIO 0 + // OUT_1: DGPIO 14 + // OUT_2: DGPIO 2 + // OUT_3: DGPIO 3 + // OUT_4: DGPIO 4 + // IN_0 : DGPIO 5 + // IN_1 : DGPIO 6 + // IN_2 : DGPIO 7 + // IN_3 : DGPIO 8 + // KEY_IN_0 KEY_IN_1 KEY_IN_2 KEY_IN_3 + // KEY_OUT_0 MENU SET PLAYBACK DISPLAY + // KEY_OUT_1 WIDE LEFT MOVIE + // KEY_OUT_2 TELE DOWN TRASH + // KEY_OUT_3 SHUTTER2 RIGHT CAPTURE + // KEY_OUT_4 SHUTTER1 UP + // Add the necessary code.. +// if (gpio_getPin(P_GPIO_8) && gpio_getPin(P_GPIO_9)) { + + if (!gpio_getPin(GPIO_SPECIAL_KEY)) { + return TRUE; + } else { + return FALSE; + } + //return TRUE; +} +#endif + +#if (FASTBOOT_KEY == ENABLE) +static BOOL prj_isFastbootKeyPressed(void) +{ + return TRUE; + /*if (gpio_getPin(GPIO_KEY_UP)) { + return FALSE; + } else { + return TRUE; + }*/ +} +#endif + +#if (CHECK_CARD_EXIST == ENABLE) +// MC16 default is config as input and pull up +_THUMB2 static BOOL prj_checkCardExist(void) +{ +#if (STORAGE_EXT_TYPE == STORAGE_EXT_ETH) + return TRUE; // force ethernet probe DHCP server +#else + return (gpio_getPin(DGPIO_CARD_DETECT) == 0 ? TRUE : FALSE); +#endif +} +#endif + +#if 0 +static BOOL bl_spiIdentify(UINT32 uiMfgID, UINT32 uiTypeID, UINT32 uiCapacityID, PSPI_IDENTIFY pIdentify) +{ + // Sample to support SST25VF032 + if ((uiMfgID == 0xBF) && + (uiCapacityID == 0x4A)) { + pIdentify->bDualRead = FALSE; + pIdentify->bSupportAAI = TRUE; + pIdentify->bSupportEWSR = TRUE; + pIdentify->uiFlashSize = 4 * 1024 * 1024; + return TRUE; + } + + return FALSE; +} + +static void bl_flashLED(void) +{ + // use GPIO to control LED +} +#endif + +// main entry of project layer code +_THUMB2 void prj_main(void) +{ + PSTORAGE_OBJ strg_obj = NULL; + loader_setVersion(_LDR_VER_); + + debug_msg("\r\n"); + debug_msg("LD_VER "); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 28) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 24) & 0xF)); + debug_msg("."); + debug_msg(Dec2HexStr2Bytes((LoaderInternalInfo[1] >> 16) & 0xFF)); + debug_msg("\r\n"); + + // Print project layer info + if((LoaderInternalInfo[6] & 0x100000) == 0x100000) { + if(gpio_getPin((((LoaderInternalInfo[6]>>12)&0x7)*32) + ((LoaderInternalInfo[6]>>15)&0x1f))) { + debug_msg(_LOADER_VERSION_STR2_); + } else { + debug_msg(_LOADER_VERSION_STR_); + } + } else { + debug_msg(_LOADER_VERSION_STR_); + } + + // Setup loader/fw file names + loader_setUpdateFwName(_UPDATE_FW_NAME_); + loader_setUpdateLdrName(_UPDATE_LOADER_NAME_); + loader_setRunFwName(_RUN_FW_NAME_); + // Setup FW_MAC_CODE_SIZE (i.e. FWResvSize in RTOS) + +#if 0 + // Sample to hook spi flash extending function + flash_installIdentifyCB(bl_spiIdentify); +#endif + +#if 0 + // Sample to hook flash programming LED callback + flash_installAccessCB(bl_flashLED); +#endif + +#if (SPECIAL_KEY_UPDATE == ENABLE) + loader_installSpecialKeyCB(prj_isSpecialKeyPressed); +#endif + +#if (CHECK_CARD_EXIST == ENABLE) + loader_installCardDetectCB(prj_checkCardExist); +#endif + +#if (FASTBOOT_KEY == ENABLE) + loader_installFastbootKeyCB(prj_isFastbootKeyPressed); +#endif + +#if defined(_STORAGEINT_NandSpi_) + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + + // set Nand Flash speed to 96MHz + strg_obj->flash_setFrequency(96); + +#elif defined(_STORAGEINT_SpiFlash_) + strg_obj = nor_get_storage_object(); + debug_msg("set nor clk 120M\r\n"); + strg_obj->flash_setFrequency(120); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); + +// debug_msg("flash_setFrequency 120MHz"); + strg_obj->flash_setFrequency(120); + debug_msg("SF 120\r\n"); + +#elif defined(_STORAGEINT_EMMC_) + strg_obj = emmc_get_storage_object(); + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); +#elif defined(_STORAGEINT_EMMC_NAND_COMBO_) + if (top_get_bs() == BOOT_SOURCE_SPI_NAND_2K || top_get_bs() == BOOT_SOURCE_SPI_NAND_4K) { + debug_msg_var("NAND,BS=", top_get_bs()); + strg_obj = nand_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NAND, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_EMMC_4BIT || top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + debug_msg("eMMC"); + strg_obj = emmc_get_storage_object(); + if (top_get_bs() == BOOT_SOURCE_EMMC_8BIT) { + strg_obj->flash_setConfig(FLASH_CFG_ID_EMMC_SUPPORT_8BITS, TRUE); + debug_msg("[8bit]\r\n"); + } else { + debug_msg("[4bit]\r\n"); + } + loader_setStorageIntType(STORAGEINT_EMMC, strg_obj); + } else if (top_get_bs() == BOOT_SOURCE_SPI) { + debug_msg("NOR\r\n"); + strg_obj = nor_get_storage_object(); +#if (SPI_PINMUX_SETTING == SPI_PINMUX_4BITS) + strg_obj->flash_setConfig(FLASH_CFG_ID_SPI_SUPPORT_4BITS, TRUE); +#endif + loader_setStorageIntType(STORAGEINT_SPI_NOR, strg_obj); + } else { + debug_msg_var("unknow BS=", top_get_bs()); + } +#endif +} + diff --git a/loader/Project/Model/Src/prj_main.h b/loader/Project/Model/Src/prj_main.h new file mode 100755 index 000000000..4e91f0494 --- /dev/null +++ b/loader/Project/Model/Src/prj_main.h @@ -0,0 +1,99 @@ +/** + Loader project header file + + Loader project header file + + @file prj_main.h + @note Nothing +*/ + +#ifndef _PRJ_MAIN_H +#define _PRJ_MAIN_H + +#include "constant.h" +#include "loader.h" +#include "GPIO.h" + +// Define SPECIAL_KEY_UPDATE == ENABLE will require user to press special key +// to update firmware +#ifndef SPECIAL_KEY_UPDATE +#define SPECIAL_KEY_UPDATE ENABLE +#endif + +#ifndef FASTBOOT_KEY +#define FASTBOOT_KEY ENABLE +#endif + +#ifndef SPI_PINMUX_NORMAL +#define SPI_PINMUX_NORMAL (0) +#endif + +#ifndef SPI_PINMUX_4BITS +#define SPI_PINMUX_4BITS (1) +#endif + +#ifndef SPI_PINMUX_SETTING +#define SPI_PINMUX_SETTING (SPI_PINMUX_4BITS) +#endif + +// Define MACROs for external storage +// +#ifndef STORAGE_EXT_UNKOWN +#define STORAGE_EXT_UNKOWN (0) +#endif + +#ifndef STORAGE_EXT_SDIO1 +#define STORAGE_EXT_SDIO1 (1) +#endif + +#ifndef STORAGE_EXT_SDIO2 +#define STORAGE_EXT_SDIO2 (2) +#endif + +#ifndef STORAGE_EXT_UART +#define STORAGE_EXT_UART (3) +#endif + +#ifndef STORAGE_EXT_USB +#define STORAGE_EXT_USB (4) +#endif + +#ifndef STORAGE_EXT_ETH +#define STORAGE_EXT_ETH (5) +#endif + +#ifndef STORAGE_EXT_NONE +#define STORAGE_EXT_NONE (6) +#endif + +#ifndef STORAGE_EXT_TYPE +#define STORAGE_EXT_TYPE (STORAGE_EXT_SDIO1) +#endif + + + +// Card detect GPIO offset +#if (CARD_DETECT_PIN == _CARD_DETECT_TYPE_1_) +#define DGPIO_CARD_DETECT (C_GPIO_9) +#elif (CARD_DETECT_PIN == _CARD_DETECT_TYPE_2_) +#if defined(_STORAGEINT_EMMC_) +#define DGPIO_CARD_DETECT (DSI_GPIO_2) +#else +#define DGPIO_CARD_DETECT (C_GPIO_9) +#endif +#else +#define DGPIO_CARD_DETECT (C_GPIO_9) +#endif + + +#define CHECK_CARD_EXIST (ENABLE) + +// disable debug msg +#define DEBUG_MSG (DISABLE) + +#define MODEL_68CS 0 +#define MODEL_S530 1 + +#define MODEL MODEL_S530 /* 1. MODEL_68CS 2. MODEL_S530 */ + +#endif diff --git a/loader/Project/Model/Src/prj_main.h.bak b/loader/Project/Model/Src/prj_main.h.bak new file mode 100755 index 000000000..b8e6ed303 --- /dev/null +++ b/loader/Project/Model/Src/prj_main.h.bak @@ -0,0 +1,94 @@ +/** + Loader project header file + + Loader project header file + + @file prj_main.h + @note Nothing +*/ + +#ifndef _PRJ_MAIN_H +#define _PRJ_MAIN_H + +#include "constant.h" +#include "loader.h" +#include "GPIO.h" + +// Define SPECIAL_KEY_UPDATE == ENABLE will require user to press special key +// to update firmware +#ifndef SPECIAL_KEY_UPDATE +#define SPECIAL_KEY_UPDATE DISABLE +#endif + +#ifndef FASTBOOT_KEY +#define FASTBOOT_KEY DISABLE +#endif + +#ifndef SPI_PINMUX_NORMAL +#define SPI_PINMUX_NORMAL (0) +#endif + +#ifndef SPI_PINMUX_4BITS +#define SPI_PINMUX_4BITS (1) +#endif + +#ifndef SPI_PINMUX_SETTING +#define SPI_PINMUX_SETTING (SPI_PINMUX_4BITS) +#endif + +// Define MACROs for external storage +// +#ifndef STORAGE_EXT_UNKOWN +#define STORAGE_EXT_UNKOWN (0) +#endif + +#ifndef STORAGE_EXT_SDIO1 +#define STORAGE_EXT_SDIO1 (1) +#endif + +#ifndef STORAGE_EXT_SDIO2 +#define STORAGE_EXT_SDIO2 (2) +#endif + +#ifndef STORAGE_EXT_UART +#define STORAGE_EXT_UART (3) +#endif + +#ifndef STORAGE_EXT_USB +#define STORAGE_EXT_USB (4) +#endif + +#ifndef STORAGE_EXT_ETH +#define STORAGE_EXT_ETH (5) +#endif + +#ifndef STORAGE_EXT_NONE +#define STORAGE_EXT_NONE (6) +#endif + +#ifndef STORAGE_EXT_TYPE +#define STORAGE_EXT_TYPE (STORAGE_EXT_SDIO1) +#endif + + + +// Card detect GPIO offset +#if (CARD_DETECT_PIN == _CARD_DETECT_TYPE_1_) +#define DGPIO_CARD_DETECT (C_GPIO_9) +#elif (CARD_DETECT_PIN == _CARD_DETECT_TYPE_2_) +#if defined(_STORAGEINT_EMMC_) +#define DGPIO_CARD_DETECT (DSI_GPIO_2) +#else +#define DGPIO_CARD_DETECT (C_GPIO_9) +#endif +#else +#define DGPIO_CARD_DETECT (C_GPIO_9) +#endif + + +#define CHECK_CARD_EXIST (DISABLE) + +// disable debug msg +#define DEBUG_MSG (ENABLE) + +#endif diff --git a/loader/Project/Model/init.gdb b/loader/Project/Model/init.gdb new file mode 100755 index 000000000..0ba83c50b --- /dev/null +++ b/loader/Project/Model/init.gdb @@ -0,0 +1,4 @@ +target remote localhost:3333 +#set endian little +#file dramtestram +set $pc = 0xF07F0028 diff --git a/loader/Project/Model/init_IceMode.gdb b/loader/Project/Model/init_IceMode.gdb new file mode 100755 index 000000000..63699fced --- /dev/null +++ b/loader/Project/Model/init_IceMode.gdb @@ -0,0 +1 @@ +target remote localhost:3333 \ No newline at end of file diff --git a/loader/Tools/Bin/Configram560 b/loader/Tools/Bin/Configram560 new file mode 100755 index 000000000..03e3104ef Binary files /dev/null and b/loader/Tools/Bin/Configram560 differ diff --git a/loader/Tools/Bin/aes.txt b/loader/Tools/Bin/aes.txt new file mode 100755 index 000000000..11391e132 --- /dev/null +++ b/loader/Tools/Bin/aes.txt @@ -0,0 +1,7 @@ +04030201080706051211100916151413 +#01020304050607080910111213141516 +#01020304050607080910111213141516 +#01020304050607080910111213141516 +#13141516091011120506070801020304 +#0D2CCD32C8131C75F53B4C12B0B09C9B +#0d2ccd32c8131c75f53b4c12b0b09c9b \ No newline at end of file diff --git a/loader/Tools/Bin/bfc b/loader/Tools/Bin/bfc new file mode 100755 index 000000000..03b06d7d9 Binary files /dev/null and b/loader/Tools/Bin/bfc differ diff --git a/loader/Tools/Bin/bfc.exe b/loader/Tools/Bin/bfc.exe new file mode 100755 index 000000000..30df1ef61 Binary files /dev/null and b/loader/Tools/Bin/bfc.exe differ diff --git a/loader/Tools/Bin/bin2byte_linux b/loader/Tools/Bin/bin2byte_linux new file mode 100755 index 000000000..0945428c6 Binary files /dev/null and b/loader/Tools/Bin/bin2byte_linux differ diff --git a/loader/Tools/Bin/encrypt_boot b/loader/Tools/Bin/encrypt_boot new file mode 100755 index 000000000..899da5df7 Binary files /dev/null and b/loader/Tools/Bin/encrypt_boot differ diff --git a/loader/Tools/Bin/encrypt_boot.exe b/loader/Tools/Bin/encrypt_boot.exe new file mode 100755 index 000000000..54dc89135 Binary files /dev/null and b/loader/Tools/Bin/encrypt_boot.exe differ diff --git a/loader/Tools/Bin/encrypt_boot_dump b/loader/Tools/Bin/encrypt_boot_dump new file mode 100755 index 000000000..305f0a861 Binary files /dev/null and b/loader/Tools/Bin/encrypt_boot_dump differ diff --git a/loader/Tools/Bin/encrypt_boot_dump.exe b/loader/Tools/Bin/encrypt_boot_dump.exe new file mode 100755 index 000000000..2a05fdeec Binary files /dev/null and b/loader/Tools/Bin/encrypt_boot_dump.exe differ diff --git a/loader/Tools/Bin/nvt-ld-op b/loader/Tools/Bin/nvt-ld-op new file mode 100755 index 000000000..99cf292f3 Binary files /dev/null and b/loader/Tools/Bin/nvt-ld-op differ diff --git a/loader/Tools/Bin/nvt-ld-op.exe b/loader/Tools/Bin/nvt-ld-op.exe new file mode 100755 index 000000000..b7316f7f9 Binary files /dev/null and b/loader/Tools/Bin/nvt-ld-op.exe differ diff --git a/loader/Tools/Bin/rsa_genkey b/loader/Tools/Bin/rsa_genkey new file mode 100755 index 000000000..1d8ad4008 Binary files /dev/null and b/loader/Tools/Bin/rsa_genkey differ diff --git a/loader/Tools/Bin/rsa_priv.txt b/loader/Tools/Bin/rsa_priv.txt new file mode 100755 index 000000000..e848075f7 --- /dev/null +++ b/loader/Tools/Bin/rsa_priv.txt @@ -0,0 +1,7 @@ +N = D3A263B309CC0D6E2963B1FD1DC421B240684CF24810E089F53E5ADE66D5F6D5289B04D7F67480A9CE7EC3164184A36259FCC81C76111870F84EE1E190997A2CD63BB42E2360B968FCC60CF7124165A9D7527B35A53EB7331A664D5E293D12469DF168F565642BC9AEDA1C4653C22DD5EA87B42B946D80508A3A5113DAE4D93D503455C7C52A32AC1E66CA0D288F587FC7419B96F3CFBF641CAA9C6E210D15AF1EE69102CFF12A71C2F2979F1B857ACFA8674427FB2CDC5AC5ABDA437EA3CA841C7E48E2BA59234F37A43F7CA1E16096B1C81CF521FE9FB33789987F2B4D2AEC6EE66D33427EA77F5C3EEDECDE2713E0A89B8EC6116AD0FDD00D9E3FB4A0AF67 +D = 0A4966E231743724E7231EE82835BBD38FB8E22096AB2756DD524A156C573317BA510AA3BAA9800580F17D670C0937EDD464EA8F239802219F9829F78E513F748577427349A9EE69317C28EE2B777D4B0B99C93E5AC9591B4549BAB1FC7C28F2C0C396AFF2DD3319AB0394034117FBA55DB079EBF25B7E34ABFB58AC87E3BEC15B0ED3B74309ABC631BB830F3C31CB5379C620A8D2E695A25E7A0D0CB9B95678C799B06848E39919A1EDA0B8A4DD1E81636250E28F7D776F1E2628D334A7868863D3AE8EC3B87B5FD95B4D0AD6612C5AB90F40CFABA5510C68A3592B206B26BFD3EE0F1E7E3FB79D052D3BBA0B22CB0E938087391CA9FB2CDEBF8A247AE10129 +P = EC3BC3068A7214BA43632A21A9A7DC3DC3582F8D25C4E1CC90A8C0CF2E8BF80E5D87031DC9EDEC3C434954D2BBB487A6C5A80E4C84E466F1637C7AF29441A6036CB67F968202C29B46DA7E001C9214339482F04BE0DBE83674BD117FEF32489130CCB67CE1B522DB9B1B9A73A562C7C2BBD34E861B56A32883554B9E91D7C8EF +Q = E557B3D1482539F665439C7C0CE7C3D7340AA86F94CA5493287B9138BE057FFBF67F18B9CDCEAF8B48FE1D0BA77AD9A4BC5B4BCE7E46F014AC4C775B1551C60050F1E80A94935DD2C826E7EDF60505EA88EB7F9A63F9796D98E897081BA7DE9F03ED06FDF3F50BDF9A38ABA6A3769C21415B6B79788AE3CA229DCFB6F3F95109 +DP = 076B1102C192378869D9515761467E2A0A5A5893EC1DB4A181E16ABC96CF9A688913564BB72D9B7F80F56A8E7B8A7DC004F0F411FF1255113B788B3BD6E000E096A75C76537AD6B59D91FAE6F1FEBC57AA503A4F87AE202AA59BD252DC260E15511CFC960B586ED1CA9B214C846307B6DBC314F22D2599560A59C1582768494D +DQ = DD08F0D28460F48327C7C8FABA09697370C1D0E27199AB7784EDCAE1D02A46D65514DB84BFF932B0E031A156C91C9AC4AD90A3F829363F4EFD5C59305CD4CA2B25D86FD63AA9E9242C296B20AA1ADF3FD2A47E0013D8AE1255EBDD1C4063432928C47A17A9D7039186F69560EE6C733F8DD90935325B51FD4FED9EF2EA22E0D9 +QP = 975A8A4F24F0D9505C625F29BA610F712893646A9532F6858F88157B283BF87235F01C88ACCC598C7157718E8B7425CD19B9D9FC31BA3E1480B5D793AC58810B82E303F9EEA44182D44A4BA953743976198A784D6FFAB1FC10A8E27CACF6D5C0CC699C6DC4C9E6D4AC012C704EF950E7E0CAE6D4B333C32BC6BBB27F4714D536 diff --git a/loader/Tools/Bin/rsa_pub.txt b/loader/Tools/Bin/rsa_pub.txt new file mode 100755 index 000000000..8d6b39e11 --- /dev/null +++ b/loader/Tools/Bin/rsa_pub.txt @@ -0,0 +1,2 @@ +N = D3A263B309CC0D6E2963B1FD1DC421B240684CF24810E089F53E5ADE66D5F6D5289B04D7F67480A9CE7EC3164184A36259FCC81C76111870F84EE1E190997A2CD63BB42E2360B968FCC60CF7124165A9D7527B35A53EB7331A664D5E293D12469DF168F565642BC9AEDA1C4653C22DD5EA87B42B946D80508A3A5113DAE4D93D503455C7C52A32AC1E66CA0D288F587FC7419B96F3CFBF641CAA9C6E210D15AF1EE69102CFF12A71C2F2979F1B857ACFA8674427FB2CDC5AC5ABDA437EA3CA841C7E48E2BA59234F37A43F7CA1E16096B1C81CF521FE9FB33789987F2B4D2AEC6EE66D33427EA77F5C3EEDECDE2713E0A89B8EC6116AD0FDD00D9E3FB4A0AF67 +E = 0000000000000000000000000000000000000000000000000000000000010001 diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_507_1024.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_1024.ini new file mode 100755 index 000000000..841c64e82 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016083 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550035 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x0E +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x01 +# reg_21 +reg_21 = 0x01 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x53 +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x13 +# reg_B8 +reg_B8 = 0x76 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x77 +# descew_c1_reg01 +descew_c1_reg01 = 0x77 +# descew_c1_reg02 +descew_c1_reg02 = 0x77 +# descew_c1_reg03 +descew_c1_reg03 = 0x77 +# descew_c1_reg04 +descew_c1_reg04 = 0x77 +# descew_c1_reg05 +descew_c1_reg05 = 0x76 +# descew_c1_reg06 +descew_c1_reg06 = 0x76 +# descew_c1_reg07 +descew_c1_reg07 = 0x76 +# descew_c1_reg08 +descew_c1_reg08 = 0x76 +# descew_c1_reg09 +descew_c1_reg09 = 0x76 +# descew_c1_reg0A +descew_c1_reg0A = 0x76 +# descew_c1_reg0B +descew_c1_reg0B = 0x76 +# descew_c1_reg0C +descew_c1_reg0C = 0x76 +# descew_c1_reg0D +descew_c1_reg0D = 0x76 +# descew_c1_reg0E +descew_c1_reg0E = 0x77 +# descew_c1_reg0F +descew_c1_reg0F = 0x77 +# descew_c1_reg10 +descew_c1_reg10 = 0x77 +# descew_c1_reg11 +descew_c1_reg11 = 0x77 +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_507_2048.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_2048.ini new file mode 100755 index 000000000..def76a545 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016084 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F55004F +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x0E +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x01 +# reg_21 +reg_21 = 0x01 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x53 +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x13 +# reg_B8 +reg_B8 = 0x76 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x77 +# descew_c1_reg01 +descew_c1_reg01 = 0x77 +# descew_c1_reg02 +descew_c1_reg02 = 0x77 +# descew_c1_reg03 +descew_c1_reg03 = 0x77 +# descew_c1_reg04 +descew_c1_reg04 = 0x77 +# descew_c1_reg05 +descew_c1_reg05 = 0x76 +# descew_c1_reg06 +descew_c1_reg06 = 0x76 +# descew_c1_reg07 +descew_c1_reg07 = 0x76 +# descew_c1_reg08 +descew_c1_reg08 = 0x76 +# descew_c1_reg09 +descew_c1_reg09 = 0x76 +# descew_c1_reg0A +descew_c1_reg0A = 0x76 +# descew_c1_reg0B +descew_c1_reg0B = 0x76 +# descew_c1_reg0C +descew_c1_reg0C = 0x76 +# descew_c1_reg0D +descew_c1_reg0D = 0x76 +# descew_c1_reg0E +descew_c1_reg0E = 0x77 +# descew_c1_reg0F +descew_c1_reg0F = 0x77 +# descew_c1_reg10 +descew_c1_reg10 = 0x77 +# descew_c1_reg11 +descew_c1_reg11 = 0x77 +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_507_4096.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_4096.ini new file mode 100755 index 000000000..9b52caf56 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x21210906 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016085 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x0E +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x01 +# reg_21 +reg_21 = 0x01 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x53 +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x13 +# reg_B8 +reg_B8 = 0x76 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x77 +# descew_c1_reg01 +descew_c1_reg01 = 0x77 +# descew_c1_reg02 +descew_c1_reg02 = 0x77 +# descew_c1_reg03 +descew_c1_reg03 = 0x77 +# descew_c1_reg04 +descew_c1_reg04 = 0x77 +# descew_c1_reg05 +descew_c1_reg05 = 0x76 +# descew_c1_reg06 +descew_c1_reg06 = 0x76 +# descew_c1_reg07 +descew_c1_reg07 = 0x76 +# descew_c1_reg08 +descew_c1_reg08 = 0x76 +# descew_c1_reg09 +descew_c1_reg09 = 0x76 +# descew_c1_reg0A +descew_c1_reg0A = 0x76 +# descew_c1_reg0B +descew_c1_reg0B = 0x76 +# descew_c1_reg0C +descew_c1_reg0C = 0x76 +# descew_c1_reg0D +descew_c1_reg0D = 0x76 +# descew_c1_reg0E +descew_c1_reg0E = 0x77 +# descew_c1_reg0F +descew_c1_reg0F = 0x77 +# descew_c1_reg10 +descew_c1_reg10 = 0x77 +# descew_c1_reg11 +descew_c1_reg11 = 0x77 +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_507_8192.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_8192.ini new file mode 100755 index 000000000..fd272a3d0 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_507_8192.ini @@ -0,0 +1,138 @@ +ini_ver = 0x21210906 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x002A4000 +#Dram Configuration register(0xF0000000) +config_reg = 0x00016086 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x10707507 +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x0F550081 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x0010191A +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000403 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC0 +# reg_0D +reg_0D = 0x0E +# reg_0F +reg_0F = 0x0D +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x01 +# reg_21 +reg_21 = 0x01 +# reg_38 +reg_38 = 0x07 +# reg_39 +reg_39 = 0x07 +# reg_40 +reg_40 = 0x0D +# reg_41 +reg_41 = 0x0D +# reg_42 +reg_42 = 0x08 +# reg_43 +reg_43 = 0x08 +# reg_44 +reg_44 = 0x08 +# reg_45 +reg_45 = 0x08 +# reg_46 +reg_46 = 0x08 +# reg_47 +reg_47 = 0x08 +# reg_53 +reg_53 = 0x07 +# reg_54 +reg_54 = 0x0B +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0B +# reg_58 +reg_58 = 0x07 +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x53 +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x13 +# reg_B8 +reg_B8 = 0x76 +# reg_D5 +reg_D5 = 0x0B +# reg_D6 +reg_D6 = 0x0B +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x77 +# descew_c1_reg01 +descew_c1_reg01 = 0x77 +# descew_c1_reg02 +descew_c1_reg02 = 0x77 +# descew_c1_reg03 +descew_c1_reg03 = 0x77 +# descew_c1_reg04 +descew_c1_reg04 = 0x77 +# descew_c1_reg05 +descew_c1_reg05 = 0x76 +# descew_c1_reg06 +descew_c1_reg06 = 0x76 +# descew_c1_reg07 +descew_c1_reg07 = 0x76 +# descew_c1_reg08 +descew_c1_reg08 = 0x76 +# descew_c1_reg09 +descew_c1_reg09 = 0x76 +# descew_c1_reg0A +descew_c1_reg0A = 0x76 +# descew_c1_reg0B +descew_c1_reg0B = 0x76 +# descew_c1_reg0C +descew_c1_reg0C = 0x76 +# descew_c1_reg0D +descew_c1_reg0D = 0x76 +# descew_c1_reg0E +descew_c1_reg0E = 0x77 +# descew_c1_reg0F +descew_c1_reg0F = 0x77 +# descew_c1_reg10 +descew_c1_reg10 = 0x77 +# descew_c1_reg11 +descew_c1_reg11 = 0x77 +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_760_1024.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_1024.ini new file mode 100755 index 000000000..52322c98c --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003F5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x16F80052 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_760_2048.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_2048.ini new file mode 100755 index 000000000..6af56c5cc --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003F5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x16F80078 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_760_4096.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_4096.ini new file mode 100755 index 000000000..9e4357e68 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11210906 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003F5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x16F800C5 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_760_8192.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_8192.ini new file mode 100755 index 000000000..eaa24d05f --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_760_8192.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11210906 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x003F5555 +#Dram Configuration register(0xF0000000) +config_reg = 0x000180B6 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x40D0B60B +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x16F800C5 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x00192027 +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x00000000 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x00 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0x00 +# reg_86 +reg_86 = 0x00 +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x55 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_933_1024.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_1024.ini new file mode 100755 index 000000000..bf83841cc --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_1024.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D3 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C620064 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_933_2048.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_2048.ini new file mode 100755 index 000000000..c7bc7bb28 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_2048.ini @@ -0,0 +1,138 @@ +ini_ver = 0x10211104 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D4 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C620093 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_933_4096.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_4096.ini new file mode 100755 index 000000000..bf0c71eea --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_4096.ini @@ -0,0 +1,138 @@ +ini_ver = 0x11210818 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D5 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C6200F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/loader/Tools/ConfigRam/560/51089A_DRAM1_933_8192.ini b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_8192.ini new file mode 100755 index 000000000..250df6ac0 --- /dev/null +++ b/loader/Tools/ConfigRam/560/51089A_DRAM1_933_8192.ini @@ -0,0 +1,138 @@ +ini_ver = 0x21210906 +#DMA freq PLL 0x[XX][0x84][0x83][0x82]=12*(0x84*256*256+0x83*256+0x82)/131072 +pllratio = 0x004DC000 +#Dram Configuration register(0xF0000000) +config_reg = 0x000190D6 +#Dram Timming0 Register(0xF0000008) +timing_reg0 = 0x30D0C50C +#Dram Timming1 Register(0xF000000C) +timing_reg1 = 0x1C6200F3 +#Dram Timming2 Register(0xF0000010) +timing_reg2 = 0x001C202C +#Dram Timming3 Register(0xF0000014) +timing_reg3 = 0x00000605 +#Dram Timming4 Register(0xF0000040) +timing_reg4 = 0x02000000 +#Engineer Register1(0xC0000050) +engineer_reg = 0x00280D21 +#ODT Register(0xF0000024) +odt_reg = 0x01111113 +# reg_0B +reg_0B = 0xC6 +# reg_0D +reg_0D = 0x03 +# reg_0F +reg_0F = 0x03 +# reg_17 +reg_17 = 0x00 +# reg_20 +reg_20 = 0x02 +# reg_21 +reg_21 = 0x02 +# reg_38 +reg_38 = 0x0A +# reg_39 +reg_39 = 0x0A +# reg_40 +reg_40 = 0x10 +# reg_41 +reg_41 = 0x10 +# reg_42 +reg_42 = 0x1A +# reg_43 +reg_43 = 0x1A +# reg_44 +reg_44 = 0x1A +# reg_45 +reg_45 = 0x1A +# reg_46 +reg_46 = 0x1A +# reg_47 +reg_47 = 0x1A +# reg_53 +reg_53 = 0x0A +# reg_54 +reg_54 = 0x0E +# reg_55 +reg_55 = 0x00 +# reg_56 +reg_56 = 0x00 +# reg_57 +reg_57 = 0x0E +# reg_58 +reg_58 = 0x0A +# reg_59 +reg_59 = 0x0E +# reg_5A +reg_5A = 0x0E +# reg_61 +reg_61 = 0x01 +# reg_64 +reg_64 = 0x44 +# reg_85 +reg_85 = 0xBB +# reg_86 +reg_86 = 0xBB +# reg_89 +reg_89 = 0x00 +# reg_8A +reg_8A = 0x00 +# reg_AE +reg_AE = 0x15 +# reg_AF +reg_AF = 0x1C +# reg_B0 +reg_B0 = 0x73 +# reg_B1 +reg_B1 = 0x4F +# reg_B2 +reg_B2 = 0x15 +# reg_B3 +reg_B3 = 0x1C +# reg_B7 +reg_B7 = 0x90 +# reg_B8 +reg_B8 = 0x65 +# reg_D5 +reg_D5 = 0x0C +# reg_D6 +reg_D6 = 0x0D +# reg_DE +reg_DE = 0x04 +# descew_c1_reg00 +descew_c1_reg00 = 0x7A +# descew_c1_reg01 +descew_c1_reg01 = 0x7A +# descew_c1_reg02 +descew_c1_reg02 = 0x7A +# descew_c1_reg03 +descew_c1_reg03 = 0x7A +# descew_c1_reg04 +descew_c1_reg04 = 0x7A +# descew_c1_reg05 +descew_c1_reg05 = 0x7A +# descew_c1_reg06 +descew_c1_reg06 = 0x7A +# descew_c1_reg07 +descew_c1_reg07 = 0x7A +# descew_c1_reg08 +descew_c1_reg08 = 0x7A +# descew_c1_reg09 +descew_c1_reg09 = 0x7A +# descew_c1_reg0A +descew_c1_reg0A = 0x7A +# descew_c1_reg0B +descew_c1_reg0B = 0x7A +# descew_c1_reg0C +descew_c1_reg0C = 0x7A +# descew_c1_reg0D +descew_c1_reg0D = 0x7A +# descew_c1_reg0E +descew_c1_reg0E = 0x7A +# descew_c1_reg0F +descew_c1_reg0F = 0x7A +# descew_c1_reg10 +descew_c1_reg10 = 0x7A +# descew_c1_reg11 +descew_c1_reg11 = 0x7A +#end \ No newline at end of file diff --git a/rtos/.vscode/settings.json b/rtos/.vscode/settings.json new file mode 100644 index 000000000..8938482aa --- /dev/null +++ b/rtos/.vscode/settings.json @@ -0,0 +1,19 @@ +{ + "search.exclude": { + "**/56*_CARDV*": true, + "**/565_HUNTING_EMMC_LINUX_4G": true, + "**/565_HUNTING_EVB_LINUX_4G": true, + "**/565_HUNTING_EVB_LINUX_4G_68CS": true, + "**/565_HUNTING_NOR_EVB*": true + }, + "files.exclude": { + "**/56*_CARDV*": true, + "**/565_HUNTING_EMMC_LINUX_4G": true, + "**/565_HUNTING_EVB_LINUX_4G": true, + "**/565_HUNTING_EVB_LINUX_4G_68CS": true, + "**/565_HUNTING_NOR_EVB*": true + }, + "editor.codeActionsOnSave": { + + } +} \ No newline at end of file diff --git a/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/DxHunting.c b/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/DxHunting.c old mode 100755 new mode 100644 index 3199a8998..8ac928c1a --- a/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/DxHunting.c +++ b/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/DxHunting.c @@ -137,11 +137,13 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) if(first_entry == TRUE){ + VOS_TICK t1, t2; + first_entry = FALSE; #if HUNTING_CAMERA_MCU == ENABLE - int ret = 1; + //int ret = 1; UINT8 value; UIMenuStoreInfo *puiPara = sf_ui_para_get(); @@ -150,11 +152,14 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) g_uiBootMode = DX_HUNTING_MODE_OTHER; return g_uiBootMode; } - ret = sf_mod_init(); - printf("%s:%d ret:%d\n", __FUNCTION__, __LINE__,ret); + + vos_perf_mark(&t1); + // ret = sf_mod_init(); + // printf("%s:%d ret:%d\n", __FUNCTION__, __LINE__,ret); value = sf_get_power_on_mode(); - sf_mcu_wdg_set(5); - sf_mcu_reg_set(SF_MCU_CTRL_MODULE_PIR, 1); + //sf_mcu_power_on_para_get(SF_MCU_POWERON); + //sf_mcu_wdg_set(5); + //sf_mcu_reg_set(SF_MCU_CTRL_MODULE_PIR, 1); switch(value) { @@ -179,7 +184,6 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) default: - printf("%s:%d CamMode:%lu\n", __FUNCTION__, __LINE__,puiPara->CamMode); if(SF_CAM_MODE_PHOTO == puiPara->CamMode) { g_uiBootMode = DX_HUNTING_MODE_PHOTO; @@ -193,7 +197,9 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) g_uiBootMode = DX_HUNTING_MODE_PHOTO_MOVIE; } break; - } + } + printf("%s:%d CamMode:%lu DebugMode:%lu\n", __FUNCTION__, __LINE__,puiPara->CamMode,puiPara->DebugMode); + #else // UINT8 bit0 = 0; // UINT8 bit1 = 0; @@ -226,7 +232,9 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) g_uiBootMode = DX_HUNTING_MODE_PHOTO_MOVIE; #endif + vos_perf_mark(&t2); + DBG_DUMP("********** first_entry = %lu\n", vos_perf_duration(t1, t2)); } return g_uiBootMode; @@ -236,6 +244,8 @@ UINT32 DrvGPIO_GetPhotoMovieModeFromMonitor(void) void DrvGOIO_Turn_Onoff_IRCUT(UINT8 onoff) { static UINT32 ir_flag = 1; + static UINT32 ir_flag_on = 1; + static UINT32 ir_flag_off = 1; printf("[%s:%d]s onoff:%d\n",__FUNCTION__,__LINE__,onoff); if(ir_flag) @@ -245,24 +255,24 @@ void DrvGOIO_Turn_Onoff_IRCUT(UINT8 onoff) ir_flag = 0; } - if(onoff ==1) - { + if((onoff == 1) && (ir_flag_on == 1)){//Just open it once. night gpio_setPin(GPIO_IRCUT_MEN1); gpio_clearPin(GPIO_IRCUT_MEN2); sf_ir_cut_ctrl_PowerOff(); - - } - else if(onoff == 0) - { + ir_flag_off = 1; + ir_flag_on = 0; + }else if((onoff == 0) && (ir_flag_off == 1)){//Just open it once. gpio_setPin(GPIO_IRCUT_MEN2); gpio_clearPin(GPIO_IRCUT_MEN1); sf_ir_cut_ctrl_PowerOff(); - } - else - { + ir_flag_off = 0; + ir_flag_on = 1; + }else if(onoff == 2){ gpio_clearPin(GPIO_IRCUT_MEN1); gpio_clearPin(GPIO_IRCUT_MEN2); - } + }else{ + printf("[%s:%d] on off\n",__FUNCTION__,__LINE__); + } //DBG_DUMP("\r\n DrvGPIO_SetIRCut value:%d \r\n",onoff); //Delay_DelayMs(20); //gpio_clearPin(GPIO_IRCUT_MEN1); diff --git a/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/sf_led.c b/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/sf_led.c index 73f311fd7..e08aede18 100755 --- a/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/sf_led.c +++ b/rtos/code/application/source/cardv/SrcCode/Dx/565_HUNTING_EVB_LINUX_4G_S530/sf_led.c @@ -38,7 +38,7 @@ void sf_trigger_time_led_cb(UINT32 cnt) { printf("[%s:%d] led\n", __FUNCTION__, __LINE__); gpio_direction_output(GPIO_GREEN_LED, 1); - gpio_set_value(GPIO_GREEN_LED, 1); + gpio_set_value(GPIO_GREEN_LED, cnt); } diff --git a/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.c b/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.c index 7ed6c97a1..f8d8f55bf 100644 --- a/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.c +++ b/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.c @@ -92,6 +92,18 @@ static UINT32 g_shdr_mode = 0; extern UINT16 IRSHTTER; extern void get_preset_param(void); static ISP_SENSOR_INIT_INFO preset_param; +static BOOL g_stop_flag = FALSE; + +void flow_preview_set_stop_flag(BOOL flag) +{ + g_stop_flag = flag; +} + +extern BOOL flow_preview_get_stop_flag(void) +{ + return g_stop_flag; +} + ISP_SENSOR_INIT_INFO *sen_preset_param(void) { return &preset_param; @@ -130,86 +142,86 @@ HD_RESULT fastflow_common_init(void) static HD_RESULT flowpreview_mem_relayout(void) { - HD_RESULT ret; - HD_COMMON_MEM_INIT_CONFIG mem_cfg = {0}; - UIAPP_PHOTO_SENSOR_INFO *pSensorInfo = UIAppPhoto_get_SensorInfo(0); - UINT8 idx = 0; + HD_RESULT ret; + HD_COMMON_MEM_INIT_CONFIG mem_cfg = {0}; + UIAPP_PHOTO_SENSOR_INFO *pSensorInfo = UIAppPhoto_get_SensorInfo(0); + UINT8 idx = 0; - // config common pool (cap) - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_RAW_BUFSIZE(pSensorInfo->sSize.w, pSensorInfo->sSize.h, CAP_OUT_FMT) - +VDO_CA_BUF_SIZE(CA_WIN_NUM_W, CA_WIN_NUM_H) - +VDO_LA_BUF_SIZE(LA_WIN_NUM_W, LA_WIN_NUM_H); + // config common pool (cap) + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_RAW_BUFSIZE(pSensorInfo->sSize.w, pSensorInfo->sSize.h, CAP_OUT_FMT) + +VDO_CA_BUF_SIZE(CA_WIN_NUM_W, CA_WIN_NUM_H) + +VDO_LA_BUF_SIZE(LA_WIN_NUM_W, LA_WIN_NUM_H); - mem_cfg.pool_info[idx].blk_cnt = 6; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; - // config common pool (main) - // mem_cfg.pool_info[1].type = HD_COMMON_MEM_COMMON_POOL; - // mem_cfg.pool_info[1].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(pSensorInfo->sSize.w, pSensorInfo->sSize.h, HD_VIDEO_PXLFMT_YUV420); - // mem_cfg.pool_info[1].blk_cnt = 2; - // mem_cfg.pool_info[1].ddr_id = DDR_ID0; + mem_cfg.pool_info[idx].blk_cnt = 6; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + // config common pool (main) + // mem_cfg.pool_info[1].type = HD_COMMON_MEM_COMMON_POOL; + // mem_cfg.pool_info[1].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(pSensorInfo->sSize.w, pSensorInfo->sSize.h, HD_VIDEO_PXLFMT_YUV420); + // mem_cfg.pool_info[1].blk_cnt = 2; + // mem_cfg.pool_info[1].ddr_id = DDR_ID0; #if POWERON_FAST_SLICE_ENC == ENABLE - idx++; - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; - mem_cfg.pool_info[idx].blk_size = PhotoFast_SliceEncode_Get_Max_Dst_Slice_Buffer_Size(HD_VIDEO_PXLFMT_YUV420); - mem_cfg.pool_info[idx].blk_cnt = 1; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + idx++; + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + mem_cfg.pool_info[idx].blk_size = PhotoFast_SliceEncode_Get_Max_Dst_Slice_Buffer_Size(HD_VIDEO_PXLFMT_YUV420); + mem_cfg.pool_info[idx].blk_cnt = 1; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; - DBG_DUMP("************ blk_size = %lx ************\n", mem_cfg.pool_info[idx].blk_size); + DBG_DUMP("************ blk_size = %lx ************\n", mem_cfg.pool_info[idx].blk_size); #else - // config common pool (primary image) - { - UINT32 u32W, u32H; - u32W = GetPhotoSizeWidth(SysGetFlag(FL_PHOTO_SIZE)); - u32H = GetPhotoSizeHeight(SysGetFlag(FL_PHOTO_SIZE)); - mem_cfg.pool_info[2].type = HD_COMMON_MEM_COMMON_POOL; - u32W = ALIGN_CEIL_16(u32W); - u32H = ALIGN_CEIL_16(u32H); - mem_cfg.pool_info[2].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(u32W, u32H, HD_VIDEO_PXLFMT_YUV420); - mem_cfg.pool_info[2].blk_cnt = 1; - mem_cfg.pool_info[2].ddr_id = DDR_ID0; - } + // config common pool (primary image) + { + UINT32 u32W, u32H; + u32W = GetPhotoSizeWidth(SysGetFlag(FL_PHOTO_SIZE)); + u32H = GetPhotoSizeHeight(SysGetFlag(FL_PHOTO_SIZE)); + mem_cfg.pool_info[2].type = HD_COMMON_MEM_COMMON_POOL; + u32W = ALIGN_CEIL_16(u32W); + u32H = ALIGN_CEIL_16(u32H); + mem_cfg.pool_info[2].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(u32W, u32H, HD_VIDEO_PXLFMT_YUV420); + mem_cfg.pool_info[2].blk_cnt = 1; + mem_cfg.pool_info[2].ddr_id = DDR_ID0; + } -#endif +#endif - // config common pool (screennail image) - idx++; - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + // config common pool (screennail image) + idx++; + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; #if HUNTING_CAMERA_MCU == ENABLE - UIMenuStoreInfo *puiPara = sf_ui_para_get(); - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(sf_get_screen_nail_width(puiPara->SendPicSize), sf_get_screen_nail_height(puiPara->SendPicSize), HD_VIDEO_PXLFMT_YUV420); + UIMenuStoreInfo *puiPara = sf_ui_para_get(); + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(sf_get_screen_nail_width(puiPara->SendPicSize), sf_get_screen_nail_height(puiPara->SendPicSize), HD_VIDEO_PXLFMT_YUV420); #else - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(CFG_SCREENNAIL_W, CFG_SCREENNAIL_H, HD_VIDEO_PXLFMT_YUV420); + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(CFG_SCREENNAIL_W, CFG_SCREENNAIL_H, HD_VIDEO_PXLFMT_YUV420); #endif - mem_cfg.pool_info[idx].blk_cnt = 1; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; - // config common pool (thumbnail image) - idx++; - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(CFG_THUMBNAIL_W, CFG_THUMBNAIL_H, HD_VIDEO_PXLFMT_YUV420); - mem_cfg.pool_info[idx].blk_cnt = 1; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; - // config common pool (EXIF) - idx++; - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+CFG_JPG_HEADER_SIZE; - mem_cfg.pool_info[idx].blk_cnt = 1; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + mem_cfg.pool_info[idx].blk_cnt = 1; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + // config common pool (thumbnail image) + idx++; + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+VDO_YUV_BUFSIZE(CFG_THUMBNAIL_W, CFG_THUMBNAIL_H, HD_VIDEO_PXLFMT_YUV420); + mem_cfg.pool_info[idx].blk_cnt = 1; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + // config common pool (EXIF) + idx++; + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE()+CFG_JPG_HEADER_SIZE; + mem_cfg.pool_info[idx].blk_cnt = 1; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; #if (_PACKAGE_BOOTLOGO_) - idx++; - mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; - mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE() + ((BOOT_LOGO_LCD_WIDTH * BOOT_LOGO_LCD_HEIGHT * 3) / 2); - mem_cfg.pool_info[idx].blk_cnt = 2; - mem_cfg.pool_info[idx].ddr_id = DDR_ID0; + idx++; + mem_cfg.pool_info[idx].type = HD_COMMON_MEM_COMMON_POOL; + mem_cfg.pool_info[idx].blk_size = DBGINFO_BUFSIZE() + ((BOOT_LOGO_LCD_WIDTH * BOOT_LOGO_LCD_HEIGHT * 3) / 2); + mem_cfg.pool_info[idx].blk_cnt = 2; + mem_cfg.pool_info[idx].ddr_id = DDR_ID0; #endif - ret = vendor_common_mem_relayout(&mem_cfg); - return ret; + ret = vendor_common_mem_relayout(&mem_cfg); + return ret; } /////////////////////////////////////////////////////////////////////////////// @@ -865,15 +877,6 @@ int flow_preview(void) } } -#if HUNTING_CAMERA_MCU == ENABLE - if(sf_is_night_mode(1) !=TRUE) - { - DrvGOIO_Turn_Onoff_IRCUT(1); - } -#else -DrvGOIO_Turn_Onoff_IRCUT(1); -#endif - // quick sensor setup vos_flag_clr(flag_task, FLAG_SENSOR_TASK_EXIT); handle_sensor = vos_task_create(thread_sensor, NULL, "init_sensor", 10, DEFAULT_TASK_STACK_SIZE); @@ -1025,32 +1028,42 @@ void flow_preview_close_module(void) { HD_RESULT hd_ret; - hd_ret = hd_videocap_stop(stream[0].cap_path); - if (hd_ret != HD_OK) { - DBG_ERR("vcap stop failed, hd_ret = %d\r\n", hd_ret); + if(stream[0].cap_path){ + hd_ret = hd_videocap_stop(stream[0].cap_path); + if (hd_ret != HD_OK) { + DBG_ERR("vcap stop failed, hd_ret = %d\r\n", hd_ret); + } } - hd_ret = hd_videoproc_stop(stream[0].proc_path); - if (hd_ret != HD_OK) { - DBG_ERR("vprc stop failed, hd_ret = %d\r\n", hd_ret); + if(stream[0].proc_path){ + hd_ret = hd_videoproc_stop(stream[0].proc_path); + if (hd_ret != HD_OK) { + DBG_ERR("vprc stop failed, hd_ret = %d\r\n", hd_ret); + } } - hd_ret = hd_videocap_close(stream[0].cap_path); - if (hd_ret != HD_OK) { - DBG_ERR("vcap close failed, hd_ret = %d\r\n", hd_ret); + if(stream[0].cap_path){ + hd_ret = hd_videocap_close(stream[0].cap_path); + if (hd_ret != HD_OK) { + DBG_ERR("vcap close failed, hd_ret = %d\r\n", hd_ret); + } } - hd_ret = hd_videoproc_close(stream[0].proc_path); - if (hd_ret != HD_OK) { - DBG_ERR("vprc close failed, hd_ret = %d\r\n", hd_ret); + if(stream[0].proc_path){ + hd_ret = hd_videoproc_close(stream[0].proc_path); + if (hd_ret != HD_OK) { + DBG_ERR("vprc close failed, hd_ret = %d\r\n", hd_ret); + } } #if HUNTING_PHOTO_FAST_AE_60_FPS == ENABLE #else - hd_ret = hd_videocap_unbind(HD_VIDEOCAP_0_OUT_0); - if (hd_ret != HD_OK) { - DBG_ERR("vcap unbind failed, hd_ret = %d\r\n", hd_ret); + if(stream[0].cap_path){ + hd_ret = hd_videocap_unbind(HD_VIDEOCAP_0_OUT_0); + if (hd_ret != HD_OK) { + DBG_ERR("vcap unbind failed, hd_ret = %d\r\n", hd_ret); + } } #endif @@ -1267,7 +1280,7 @@ void setet_preset_param(void) preset_param.expt= ae_status_info.status_info.expotime[0]; preset_param.gain= ae_status_info.status_info.iso_gain[0]; total_gain.id = 0; - total_gain.gain = preset_param.gain/5; + total_gain.gain = preset_param.gain; vendor_isp_set_common(ISPT_ITEM_TOTAL_GAIN, &total_gain); } diff --git a/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.h b/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.h old mode 100755 new mode 100644 index 76221355f..25c17de5d --- a/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.h +++ b/rtos/code/application/source/cardv/SrcCode/FastFlow/flow_preview.h @@ -17,4 +17,6 @@ typedef enum _FLOW_PREIVEW_PATH { extern void flow_preview_get_path(HD_PATH_ID *pPath, FLOW_PREIVEW_PATH PathType, UINT32 id); extern void flow_preview_close_module(void); extern void flow_preview_uninit_module(void); +extern void flow_preview_set_stop_flag(BOOL flag); +extern BOOL flow_preview_get_stop_flag(void); #endif \ No newline at end of file diff --git a/rtos/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h b/rtos/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h index 01049ae18..42aa63592 100644 --- a/rtos/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h +++ b/rtos/code/application/source/cardv/SrcCode/PrjCfg_HUNTING_S530.h @@ -98,7 +98,7 @@ #define POWERON_TRACE DISABLE //stop and wait for user enter cmd: "dsc boot" #define POWERON_BOOT_REPORT ENABLE #define POWERON_FAST_BOOT DISABLE -#define POWERON_FAST_BOOT_MSG ENABLE // disable boot msg for fast boot, but hard to debug +#define POWERON_FAST_BOOT_MSG DISABLE // disable boot msg for fast boot, but hard to debug #define POWERON_FAST_CPU2_BOOT DISABLE #define POWERON_FAST_RECORD DISABLE #define POWERON_FAST_WIFI DISABLE //NOTE: need to enable POWERON_FAST_CPU2_BOOT too @@ -948,10 +948,10 @@ #define MOVIE_AI_DEMO DISABLE #define HUNTING_MCU_I2C DISABLE #define HUNTING_MCU_UART ENABLE -#define HUNTING_IR_LED_940 DISABLE +#define HUNTING_IR_LED_940 ENABLE//DISABLE #define SF_EXIF_MN_BUF_SIZE 256 -#define SF_BASE_VERSION "7MD4RCwD3T6" -#define SF_TRIGGER_TIME_TEST DISABLE//ENABLE +#define SF_BASE_VERSION "7MD4RCwD3T8" +#define SF_TRIGGER_TIME_TEST DISABLE #define HUNTING_PHOTO_FAST_AE_60_FPS ENABLE #define HW_S530 1 diff --git a/rtos/code/application/source/cardv/SrcCode/System/SysMain_cmd.c b/rtos/code/application/source/cardv/SrcCode/System/SysMain_cmd.c old mode 100755 new mode 100644 index 684970740..67c32b4fc --- a/rtos/code/application/source/cardv/SrcCode/System/SysMain_cmd.c +++ b/rtos/code/application/source/cardv/SrcCode/System/SysMain_cmd.c @@ -192,6 +192,15 @@ static BOOL Cmd_user_ShowPowerStatus(unsigned char argc, char **argv) return TRUE; } +#include "flow_preview.h" + +static BOOL Cmd_PowerOff_Test(unsigned char argc, char **argv) +{ + flow_preview_set_stop_flag(TRUE); + + return TRUE; +} + SXCMD_BEGIN(sys_cmd_tbl, "system command") SXCMD_ITEM("mem %", cmd_sys_mem, "system memory layout") SXCMD_ITEM("pip %", Cmd_user_pip, "pip view style") @@ -203,6 +212,9 @@ SXCMD_ITEM("event %", Cmd_user_EventTest, "lvgl user event test") #if (CURL_FUNC == ENABLE) SXCMD_ITEM("curl", Cmd_user_CurlTest, "curl command test") #endif + +SXCMD_ITEM("power_off %", Cmd_PowerOff_Test, "flowpreview power off test") + SXCMD_END() diff --git a/rtos/code/application/source/cardv/SrcCode/System/rtos-main.c b/rtos/code/application/source/cardv/SrcCode/System/rtos-main.c old mode 100755 new mode 100644 index 6c5cbe367..42e089281 --- a/rtos/code/application/source/cardv/SrcCode/System/rtos-main.c +++ b/rtos/code/application/source/cardv/SrcCode/System/rtos-main.c @@ -168,7 +168,14 @@ static void insmod_system(void) sdio_platform_init(); // sdio for emmc storage object #endif storage_partition_init(); // storage partition for partial load - + #if HUNTING_CAMERA_MCU == ENABLE + sf_mcu_flag_init(); + UIMenuStoreInfo *puiPara = sf_ui_para_get(); + if(puiPara->DebugMode == 1) + { + fastboot_msg_en(ENABLE); + } + #endif if(hwclock_open(HWCLOCK_MODE_DRTC) != E_OK){ DBG_ERR("open hwclock failed!\n"); } @@ -193,8 +200,6 @@ static void insmod_system(void) #endif } - - vos_perf_list_mark("b_sys", __LINE__, 1); } @@ -376,6 +381,24 @@ static void * get_fdt_by_sensor_type(char *name) return fdt_get_sensor(); } +static void mcu_task(void) +{ + #if HUNTING_CAMERA_MCU == ENABLE + vos_util_delay_ms(5); + sf_mcu_power_on_para_get(SF_MCU_POWERON); + sf_mcu_wdg_set(5); + sf_mcu_reg_set(SF_MCU_CTRL_MODULE_PIR, 1); + + //vos_util_delay_ms(15); + //if(sf_is_night_mode(1) !=TRUE) + //{ + // DrvGOIO_Turn_Onoff_IRCUT(1); + //} + #else + DrvGOIO_Turn_Onoff_IRCUT(1); + #endif +} + static void insmod_sensor(void) { SENSOR_DTSI_INFO dtsi_info; @@ -394,7 +417,7 @@ static void sie_vd_cb(const UINT32 vd_cnt) { if(vd_cnt == (PHOTOFAST_START_CAP_FRAME_CNT-1)){ - #if SF_TRIGGER_TIME_TEST == ENABLE + #if SF_TRIGGER_TIME_TEST == ENABLE && HUNTING_CAMERA_MCU == ENABLE sf_trigger_time_led_cb(1); #endif vos_perf_list_mark("sie_vd", __LINE__, 0); @@ -745,6 +768,9 @@ void insmod(void) vos_task_resume(vkt_decoder); } + VK_TASK_HANDLE vkt_mcu = vos_task_create(fastboot_thread, mcu_task, "init_mcu", 5, DEFAULT_STASK_SIZE); + vos_task_resume(vkt_mcu); + #if !DBG_PART_LOAD /* normal partial load */ //start partial load VK_TASK_HANDLE vkt_partload = vos_task_create(fastboot_thread, fwload_partload, "init_partload", 10, DEFAULT_STASK_SIZE); @@ -848,6 +874,14 @@ static void fastboot(void) serial_open(); // uart init first for debug message printf("\nHello RTOS World! (%s)\n\n", __DATE__ " - " __TIME__); +#if HUNTING_CAMERA_MCU == ENABLE + VOS_TICK t1, t2; + vos_perf_mark(&t1); + sf_mod_init(); + vos_perf_mark(&t2); + DBG_DUMP("sf_mod_init: %lu\n", vos_perf_duration(t1, t2)); +#endif + // insmod for modules initialzation insmod(); @@ -925,7 +959,7 @@ static void fastboot(void) System_OnPowerPreInit(); System_OnVideoFastbootInit(); - handle_movie_filenaming = vos_task_create(MovieFast_InitFileNamingThread, "init_fn", NULL, 10, DEFAULT_STASK_SIZE); + handle_movie_filenaming = vos_task_create(MovieFast_InitFileNamingThread, "init_fn", NULL, 10, 8192); if (!handle_movie_filenaming) { DBG_ERR("create MovieFast_InitFileNamingThread failed\r\n"); } @@ -934,7 +968,7 @@ static void fastboot(void) fastboot_wait_done(BOOT_INIT_FILENAMINGOK); - handle_movie_moviemode = vos_task_create(MovieFast_InitMovieModeThread, "init_movie", NULL, 10, DEFAULT_STASK_SIZE); + handle_movie_moviemode = vos_task_create(MovieFast_InitMovieModeThread, "init_movie", NULL, 10, 8192); if (!handle_movie_moviemode) { DBG_ERR("create MovieFast_InitMovieModeThread failed\r\n"); } @@ -1050,7 +1084,7 @@ void rtos_main(void) UIMenuStoreInfo *puiPara = sf_ui_para_get(); if(puiPara->DebugMode == 0) { - fastboot_msg_en(DISABLE); + //fastboot_msg_en(DISABLE); } #endif VK_TASK_HANDLE vkt_boot = vos_task_create(fastboot_thread, fastboot, "boot", 9, 10240); @@ -1065,7 +1099,7 @@ void rtos_main(void) #if HUNTING_CAMERA_MCU == ENABLE if(puiPara->DebugMode == 0) { - fastboot_msg_en(ENABLE); + // fastboot_msg_en(ENABLE); } #endif diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c b/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c old mode 100755 new mode 100644 index a2d4b9595..bffbd484c --- a/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_CommPoolInit.c @@ -36,8 +36,8 @@ #define VDO_MAIN_SIZE_W 2560 #define VDO_MAIN_SIZE_H 1440 -#define VDO_CLONE_SIZE_W 848 -#define VDO_CLONE_SIZE_H 480 +#define VDO_CLONE_SIZE_W 1920 +#define VDO_CLONE_SIZE_H 1080 #endif #if (defined(_disp_ifdsi_lcd1_s3003l0_st7701s_)) @@ -202,7 +202,7 @@ void Movie_CommPoolInit(void) mem_cfg.pool_info[id].blk_cnt = 4; #endif // (MOVIE_DIRECT_FUNC == ENABLE) #else // (defined(_MODEL_565_CARDV_HS880C_)||defined(_MODEL_565_CARDV_HS880CC_)||defined(_MODEL_565_CARDV_WH565_)) - mem_cfg.pool_info[id].blk_cnt = 6; + mem_cfg.pool_info[id].blk_cnt = 4; #endif // (defined(_MODEL_565_CARDV_HS880C_)||defined(_MODEL_565_CARDV_HS880CC_)||defined(_MODEL_565_CARDV_WH565_)) mem_cfg.pool_info[id].ddr_id = DDR_ID0; #endif // (SENSOR_CAPS_COUNT == 1) diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c b/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c index 6d025b6af..a24a229ff 100755 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/Movie/UIAppMovie_RecSetting.c @@ -107,7 +107,7 @@ MOVIE_RECODE_INFO gMovie_Clone_Info[SENSOR_MAX_NUM] = { #endif 30, //MOVIE_CFG_FRAME_RATE 250 * 1024, //MOVIE_CFG_TARGET_RATE - _CFG_CODEC_H264, //MOVIE_CFG_CODEC + _CFG_CODEC_H265, //MOVIE_CFG_CODEC _CFG_AUD_CODEC_AAC, //MOVIE_CFG_AUD_CODEC _CFG_REC_TYPE_AV, //MOVIE_CFG_REC_MODE #if (defined(_NVT_ETHREARCAM_TX_)) diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/MovieFast/MovieFast.c b/rtos/code/application/source/cardv/SrcCode/UIApp/MovieFast/MovieFast.c index 798c637d5..d2ce9bcd1 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/MovieFast/MovieFast.c +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/MovieFast/MovieFast.c @@ -2,6 +2,7 @@ #include "PrjInc.h" #include "ImageApp/ImageApp_MovieMulti.h" #include "avfile/movieinterface_def.h" +#include "kwrap/task.h" #include "sys_mempool.h" #include "sys_fdt.h" #include "UIApp/MovieStamp/MovieStamp.h" @@ -29,6 +30,7 @@ #include "DCF.h" #include "flow_boot_linux.h" #include "DxHunting.h" +#include "flow_preview.h" #if defined(_UI_STYLE_LVGL_) #include "flow_lvgl.h" @@ -67,14 +69,16 @@ static char thumb_current_path_clone[256] = {'\0'}; #define FILEDB_MAX_NUM 5000 #define MOVIE_THUMB_WIDTH 640 #define PRI_MOVIEFAST_CMDTSK 11 -#define STKSIZE_MOVIEFAST_CMDTSK 10240 +#define STKSIZE_MOVIEFAST_CMDTSK 8192 //local variable static DCF_HANDLE g_dcf_hdl = 0; static ID MOVIEFAST_FLG_ID = 0; static UINT32 g_moviefast_tsk_run = 1; +static UINT32 g_moviefast_poweroff_tsk_run = 1; static UINT32 g_MovieFast_InitCommonMemFinish=0; static THREAD_HANDLE g_moviefast_tsk_id = 0; +static THREAD_HANDLE g_moviefast_power_off_tsk_id = 0; static BOOL g_bIsRecStatus = FALSE; @@ -99,6 +103,36 @@ static ER MovieFast_InstallID(void) return ret; } +static THREAD_RETTYPE MovieFast_PowerOffTsk(void) +{ + const BOOL delay_ms = 200; + + THREAD_ENTRY(); + + DBG_DUMP("MovieFast_PowerOffTsk started\n"); + + g_moviefast_poweroff_tsk_run = TRUE; + + while(g_moviefast_poweroff_tsk_run) + { + if(TRUE == flow_preview_get_stop_flag()){ + DBG_ERR("Stop!!!!!!!!!!!!!!!!!\n"); + break; + } + + vos_util_delay_ms(delay_ms); + } + + if(MOVIEFAST_FLG_ID){ + vos_flag_set(MOVIEFAST_FLG_ID, FLGMOVIEFAST_SHUTDOWN); + } + else{ + MovieFast_ShutDown(); + } + + THREAD_RETURN(0); +} + static THREAD_RETTYPE MovieFast_CmdTsk(void) { FLGPTN uiFlag = 0, wait_flag = 0; @@ -117,7 +151,6 @@ static THREAD_RETTYPE MovieFast_CmdTsk(void) if (uiFlag & FLGMOVIEFAST_RECSTART) { if (DCF_GetDBInfo(DCF_INFO_IS_9999)) { DBG_ERR("Exceed max dcf file!\r\n"); - g_moviefast_tsk_run = 0; MovieFast_ShutDown(); } @@ -125,7 +158,6 @@ static THREAD_RETTYPE MovieFast_CmdTsk(void) } else if (uiFlag & FLGMOVIEFAST_RECSTOP) { MovieFast_OnRecStop(); } else if (uiFlag & FLGMOVIEFAST_SHUTDOWN) { - g_moviefast_tsk_run = 0; MovieFast_ShutDown(); }else{ DBG_WRN("No flag for MovieFast_CmdTsk\r\n"); @@ -146,14 +178,6 @@ static void MovieFast_ShutDown(void) fastboot_msg_en(ENABLE); #endif -#if HUNTING_CAMERA_MCU == ENABLE - UIMenuStoreInfo *puiPara = sf_ui_para_get(); - if(puiPara->DebugMode == 0) - { - fastboot_msg_en(ENABLE); - } -#endif - #if HUNTING_CAMERA_BOOT_LINUX /* Boot Linux */ #if POWERON_BOOT_REPORT == ENABLE @@ -246,12 +270,40 @@ static void MovieFast_RecMovieStamp(void) UINT32 uiStampMemSize; WATERLOGO_BUFFER waterLogoSrc={0}; HD_PATH_ID uiVEncOutPortId = 0; - STAMP_COLOR StampColorBg = {RGB_GET_Y( 16, 16, 16), RGB_GET_U( 16, 16, 16), RGB_GET_V( 16, 16, 16)}; // date stamp background color - STAMP_COLOR StampColorFr = {RGB_GET_Y( 16, 16, 16), RGB_GET_U( 16, 16, 16), RGB_GET_V( 16, 16, 16)}; // date stamp frame color - STAMP_COLOR StampColorFg = {RGB_GET_Y(224, 224, 192), RGB_GET_U(224, 224, 192), RGB_GET_V(224, 224, 192)}; // date stamp foreground color UINT32 i, mask; UINT32 movie_rec_mask, clone_rec_mask; +#if defined(_UI_STYLE_LVGL_) + lv_color32_t color = (lv_color32_t){.full = LV_USER_CFG_STAMP_COLOR_BACKGROUND}; + uint8_t r = LV_COLOR_GET_R32(color); + uint8_t g = LV_COLOR_GET_G32(color); + uint8_t b = LV_COLOR_GET_B32(color); + STAMP_COLOR StampColorBg = {RGB_GET_Y(r, g, b), RGB_GET_U(r, g, b), RGB_GET_V(r, g, b)}; // date stamp foreground color +#else + STAMP_COLOR StampColorBg = {RGB_GET_Y( 16, 16, 16), RGB_GET_U( 16, 16, 16), RGB_GET_V( 16, 16, 16)}; // date stamp background color +#endif + +#if defined(_UI_STYLE_LVGL_) + color = (lv_color32_t){.full = LV_USER_CFG_STAMP_COLOR_FRAME}; + r = LV_COLOR_GET_R32(color); + g = LV_COLOR_GET_G32(color); + b = LV_COLOR_GET_B32(color); + STAMP_COLOR StampColorFr = {RGB_GET_Y(r, g, b), RGB_GET_U(r, g, b), RGB_GET_V(r, g, b)}; // date stamp foreground color +#else + STAMP_COLOR StampColorFr = {RGB_GET_Y( 16, 16, 16), RGB_GET_U( 16, 16, 16), RGB_GET_V( 16, 16, 16)}; // date stamp frame color +#endif + + +#if defined(_UI_STYLE_LVGL_) + color = (lv_color32_t){.full = LV_USER_CFG_STAMP_COLOR_TEXT}; + r = LV_COLOR_GET_R32(color); + g = LV_COLOR_GET_G32(color); + b = LV_COLOR_GET_B32(color); + STAMP_COLOR StampColorFg = {RGB_GET_Y(r, g, b), RGB_GET_U(r, g, b), RGB_GET_V(r, g, b)}; // date stamp foreground color +#else + STAMP_COLOR StampColorFg = {RGB_GET_Y(224, 224, 192), RGB_GET_U(224, 224, 192), RGB_GET_V(224, 224, 192)}; // date stamp foreground color +#endif + movie_rec_mask = Movie_GetMovieRecMask(); clone_rec_mask = Movie_GetCloneRecMask(); //DBG_DUMP("setup_rec_moviestamp sen_cnt=%d\r\n",sen_cnt); @@ -424,7 +476,7 @@ static void MovieFast_SetRecInfoByUISetting(void) gMovie_Rec_Info[i].frame_rate = MovieMapping_GetFrameRate(size_idx, ipl_id); gMovie_Rec_Info[i].target_bitrate = MovieMapping_GetTargetBitrate(size_idx, ipl_id); gMovie_Rec_Info[i].dar = MovieMapping_GetDispAspectRatio(size_idx, ipl_id); - gMovie_Rec_Info[i].codec = _CFG_CODEC_H265; + gMovie_Rec_Info[i].codec = (UI_GetData(FL_MOVIE_CODEC) == MOVIE_CODEC_H265) ? _CFG_CODEC_H265 : _CFG_CODEC_H264; //#NT#2018/02/14#KCHong -begin //#NT#support sensor rotate setting gMovie_Rec_Info[i].sensor_rotate = FALSE; @@ -457,7 +509,7 @@ static void MovieFast_SetRecInfoByUISetting(void) gMovie_Clone_Info[i].frame_rate = MovieMapping_GetCloneFrameRate(size_idx, ipl_id); gMovie_Clone_Info[i].target_bitrate = MovieMapping_GetCloneTargetBitrate(size_idx, ipl_id); gMovie_Clone_Info[i].dar = MovieMapping_GetCloneDispAspectRatio(size_idx, ipl_id); - gMovie_Clone_Info[i].codec = _CFG_CODEC_H264; + gMovie_Clone_Info[i].codec = (UI_GetData(FL_MOVIE_CODEC) == MOVIE_CODEC_H265) ? _CFG_CODEC_H265 : _CFG_CODEC_H264; MovieMapping_GetCloneAqInfo(size_idx, ipl_id, (UINT32)&gMovie_Clone_Info[i].aq_info); MovieMapping_GetCloneCbrInfo(size_idx, ipl_id, (UINT32)&gMovie_Clone_Info[i].cbr_info); movie_aspect_ratio_idx = MovieMapping_GetCloneImageRatio(size_idx, ipl_id); @@ -694,6 +746,7 @@ static void MovieFast_UserEventCb(UINT32 id, MOVIE_USER_CB_EVENT event_id, UINT3 #endif case MOVIE_USER_CB_EVENT_CLOSE_FILE_COMPLETED: { + sf_ir_led_set(0, 0, 0, 0); //MOVIEMULTI_CLOSE_FILE_INFO *info = (MOVIEMULTI_CLOSE_FILE_INFO *)value; //DCF_AddDBfile(info->path); //DBG_DUMP("%s added to DCF\r\n", info->path); @@ -821,6 +874,12 @@ EXIT: extern void Set_NIGHTMODE(UINT32 id, UINT8 isSnapVideo); extern void Set_AEMODE(UINT32 id); extern void setet_preset_param(void); + +void MovieFast_Set_Shutdown_flag(void) +{ + vos_flag_set(MOVIEFAST_FLG_ID, FLGMOVIEFAST_SHUTDOWN); +} + THREAD_RETTYPE MovieFast_InitMovieModeThread(void *arg) { UINT32 i; @@ -951,8 +1010,14 @@ THREAD_RETTYPE MovieFast_InitMovieModeThread(void *arg) //Set_AEMODE(1); //vos_util_delay_ms(500); + if ((g_moviefast_power_off_tsk_id = vos_task_create(MovieFast_PowerOffTsk, 0, "MovieFastPwrTsk", PRI_MOVIEFAST_CMDTSK, STKSIZE_MOVIEFAST_CMDTSK)) == 0) { + DBG_ERR("MovieFast_PowerOffTsk create failed.\r\n"); + } else { + vos_task_resume(g_moviefast_power_off_tsk_id); + } + if ((g_moviefast_tsk_id = vos_task_create(MovieFast_CmdTsk, 0, "MovieFastTsk", PRI_MOVIEFAST_CMDTSK, STKSIZE_MOVIEFAST_CMDTSK)) == 0) { - DBG_ERR("MovieFastTsk create failed.\r\n"); + DBG_ERR("MovieFast_CmdTsk create failed.\r\n"); } else { vos_task_resume(g_moviefast_tsk_id); } @@ -960,7 +1025,6 @@ THREAD_RETTYPE MovieFast_InitMovieModeThread(void *arg) vos_flag_set(MOVIEFAST_FLG_ID, FLGMOVIEFAST_RECSTART); THREAD_RETURN(0); - } static void MovieFast_Close(void) diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.c b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.c index 47f95571f..a938a3d28 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.c +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.c @@ -65,7 +65,7 @@ #define STKSIZE_PHOTOFAST_CMDTSK 4096 #define FASTCAPTURE_AE_DEBUG 1 -#define VD_TICK_BUF_SIZE (PHOTOFAST_CAP_FRAME_CNT * 3) +#define VD_TICK_BUF_SIZE (PHOTOFAST_START_CAP_FRAME_CNT * 3) //global variable static _FDB_SN_FASTBOOT g_fdb_sn_fastboot={ @@ -86,7 +86,7 @@ static MEM_RANGE g_photo_fast_fdb_pool = { static CHAR g_photo_fast_write_file_Path[NMC_TOTALFILEPATH_MAX_LEN] = {0}; static INT32 g_photo_fast_id_mapping[PHOTO_CAP_ID_MAX] = {-1,-1}; static PHOTO_FILENAME_CB *g_fpPhotoFastFileNameCB = NULL; -static DCF_HANDLE g_dcf_hdl = 0; +static DCF_HANDLE g_dcf_hdl = -1; static HD_PATH_ID g_video_enc_path[PHOTO_ENC_JPG_TYPE_MAX_ID] = {0}; static UINT32 g_bVideoEncPathStart[PHOTO_ENC_JPG_TYPE_MAX_ID] = {0}; static HD_VIDEOENC_BUFINFO g_enc_buf_info[PHOTO_ENC_JPG_TYPE_MAX_ID] = {0}; @@ -98,6 +98,7 @@ static UINT32 g_enc_vir_addr[PHOTO_ENC_JPG_TYPE_MAX_ID] = {0}; static BOOL g_bPreViewPullFlag = TRUE; static UINT32 g_vcap_frm_cnt = 1; /* start from 1 */ +static UINT32 g_vprc_frm_cnt_ae_preset = 9999; static UINT32 g_vprc_frm_cnt = 1; /* start from 1 */ static BOOL g_ae_preset_flag = FALSE; static UINT32 g_exif_buf_pa = 0, g_exif_buf_va = 0; @@ -480,6 +481,12 @@ static ER PhotoFast_UninitExif(void) ER ret = E_OK; HD_RESULT hd_ret; + if(g_exif_buf_pa == 0){ + ret = E_OK; + return ret; + } + + if ((hd_ret = hd_common_mem_free(g_exif_buf_pa, (void *)g_exif_buf_va)) != HD_OK) { DBG_ERR("hd_common_mem_free failed(%d)\r\n", hd_ret); ret = E_SYS; @@ -601,10 +608,14 @@ static ER PhotoFast_InstallID(void) if ((ret |= vos_flag_create(&PHOTOFAST_FLG_ID, &cflg, "PHOTOFAST_FLG")) != E_OK) { DBG_ERR("PHOTOFAST_FLG_ID fail\r\n"); } - return ret; } +static void PhotoFast_CmdTsk_Exit(void) +{ + g_photofast_tsk_run = 0; +} + static THREAD_RETTYPE PhotoFast_CmdTsk(void* arg) { FLGPTN uiFlag = 0, wait_flag = 0; @@ -622,10 +633,11 @@ static THREAD_RETTYPE PhotoFast_CmdTsk(void* arg) vos_flag_wait(&uiFlag, PHOTOFAST_FLG_ID, wait_flag, TWF_ORW | TWF_CLR); if (uiFlag & FLGPHOTOFAST_SHUTDOWN) { - g_photofast_tsk_run = 0; PhotoFast_ShutDown(); } else if (uiFlag & FLGPHOTOFAST_CHGMODE) { - g_photofast_tsk_run = 0; + + PhotoFast_CmdTsk_Exit(); + switch (DrvGPIO_GetPhotoMovieModeFromMonitor()) { case DX_HUNTING_MODE_PHOTO_MOVIE: case DX_HUNTING_MODE_CAMERA_PHOTO_MOVIE: @@ -695,6 +707,9 @@ INT32 PhotoFast_FileNaming_Open(void) .WorkbuffSize = POOL_SIZE_DCF_BUFFER, }; g_dcf_hdl = DCF_Open(&dcfParm); + if(g_dcf_hdl < 0){ + DBG_ERR("get dcf handle error!\n"); + } DCF_SetParm(DCF_PRMID_REMOVE_DUPLICATE_FOLDER, TRUE); DCF_SetParm(DCF_PRMID_REMOVE_DUPLICATE_FILE, TRUE); @@ -709,7 +724,11 @@ INT32 PhotoFast_FileNaming_Open(void) INT32 PhotoFast_FileNaming_Close(void) { - DCF_Close(g_dcf_hdl); + if(g_dcf_hdl >= 0){ + DCF_Close(g_dcf_hdl); + g_dcf_hdl = -1; + } + DCF_UnInstallID(); return 0; } @@ -1107,6 +1126,11 @@ static BOOL bCaptureStartFirstEntry = TRUE; #if POWERON_FAST_SLICE_ENC == ENABLE +static void PhotoFast_CaptureStop(void) +{ + PhotoFast_Sliceencode2_Stop(); +} + static void PhotoFast_CaptureStart(HD_VIDEO_FRAME *p_video_frame) { HD_PATH_ID vprc_path; @@ -1327,6 +1351,7 @@ static void PhotoFast_CaptureStart(HD_VIDEO_FRAME *p_video_frame) THREAD_RETTYPE PhotoFast_InitFileNamingThread(void *arg) { + fastboot_wait_done(BOOT_INIT_FILESYSOK); PhotoFast_FileNaming_Open(); fastboot_set_done(BOOT_INIT_FILENAMINGOK); @@ -1349,6 +1374,7 @@ THREAD_RETTYPE PhotoFast_FlowPreviewThread(void *arg) HD_PATH_ID vprc_path = 0, vout_path = 0, vcap_path = 0; UINT32 max_cnt = 0; BOOL start_cap = FALSE; + BOOL stop_flag = FALSE; #if HUNTING_CAMERA_MCU == ENABLE UIMenuStoreInfo *puiPara = sf_ui_para_get(); @@ -1390,7 +1416,23 @@ THREAD_RETTYPE PhotoFast_FlowPreviewThread(void *arg) #if POWERON_FAST_SLICE_ENC_VER2 == ENABLE - UINT32 period = 1000 / max_cnt; + + UINT32 period = 0; +#if HUNTING_CAMERA_MCU == ENABLE + if(1 == puiPara->MultiShotIntevel) + { + period = 1000;//The interval between consecutive shots of each photo is 1 second + } + else if(2 == puiPara->MultiShotIntevel) { + period = 2000;//The interval between consecutive shots of each photo is 2 second + } + else { + period = 1000 / max_cnt; + } +#else + period = 1000 / max_cnt; +#endif + PhotoFast_SliceEncode2_Open(vprc_path, max_cnt); nvt_cmdsys_runcmd("ae set_speed 0 128 600 600 100 "); @@ -1423,16 +1465,25 @@ THREAD_RETTYPE PhotoFast_FlowPreviewThread(void *arg) #endif while(g_bPreViewPullFlag) { - if((g_vcap_frm_cnt > 3) && (g_ae_preset_flag == FALSE)){ - - memset(&ae_status, 0, sizeof(AET_STATUS_INFO)); - vendor_isp_get_ae(AET_ITEM_STATUS, &ae_status); - if ((ae_status.status_info.state_adj == 0) || (g_vcap_frm_cnt >= PHOTOFAST_CAP_FRAME_CNT)){ - g_ae_preset_flag = TRUE; - Set_AEMODE(1); - setet_preset_param(); - } - } + if(TRUE == flow_preview_get_stop_flag()){ + DBG_ERR("Stop!!!!!!!!!!!!!!!!!\n"); + stop_flag = TRUE; + hd_ret = HD_ERR_ABORT; + goto exit; + } + + if((g_vcap_frm_cnt > 2) && (g_ae_preset_flag == FALSE)){ + + memset(&ae_status, 0, sizeof(AET_STATUS_INFO)); + vendor_isp_get_ae(AET_ITEM_STATUS, &ae_status); + if ((ae_status.status_info.state_adj == 0) || (g_vcap_frm_cnt >= PHOTOFAST_AE_PRESET_FRAME_CNT)){ + g_ae_preset_flag = TRUE; + g_vprc_frm_cnt_ae_preset = g_vprc_frm_cnt; + DBG_DUMP("ae preset vprc frame cnt = %lu\n", g_vprc_frm_cnt_ae_preset); + Set_AEMODE(1); + setet_preset_param(); + } + } //DBG_WRN(">>>>>>> adj %d lum %d explum %d exp %d iso %d\r\n",ae_status.status_info.state_adj,ae_status.status_info.lum,ae_status.status_info.expect_lum,ae_status.status_info.iso_gain[0],ae_status.status_info.expotime[0]); #if POWERON_FAST_SLICE_ENC_VER2 == ENABLE @@ -1444,7 +1495,7 @@ THREAD_RETTYPE PhotoFast_FlowPreviewThread(void *arg) sf_ir_led_set(((2 == puiPara->NightMode) ? 2 : 1),puiPara->FlashLed, puiPara->NightMode,0); } #endif - vos_util_delay_ms(200); + vos_util_delay_ms(170); } #endif @@ -1474,16 +1525,35 @@ THREAD_RETTYPE PhotoFast_FlowPreviewThread(void *arg) DBG_ERR("failed to hd_videoproc_pull_out_buf, er=%d\n", (int)hd_ret); goto exit; } - DBG_DUMP("vcap:%lu vprc:%lu\n", g_vcap_frm_cnt, g_vprc_frm_cnt); - if((g_vcap_frm_cnt >= PHOTOFAST_CAP_FRAME_CNT) && (start_cap == FALSE)){ - // if (g_vcap_frm_cnt > PHOTOFAST_START_CAP_FRAME_CNT) { + DBG_DUMP("vcap:%lu vprc:%lu vprc_ae_preset:%lu\n", g_vcap_frm_cnt, g_vprc_frm_cnt, g_vprc_frm_cnt_ae_preset); + + /***************************************************************************************** + * trigger rule: + * + * 1. PHOTOFAST_START_CAP_FRAME_CNT arrived + * + * 2. third frame since ae preset + ******************************************************************************************/ + if(((g_vcap_frm_cnt >= PHOTOFAST_START_CAP_FRAME_CNT) || (g_ae_preset_flag == TRUE && g_vprc_frm_cnt >= (g_vprc_frm_cnt_ae_preset + 3))) && (start_cap == FALSE)){ + + if(g_vcap_frm_cnt >= PHOTOFAST_START_CAP_FRAME_CNT){ + DBG_DUMP("triggered by PHOTOFAST_START_CAP_FRAME_CNT\n"); + } + else if(g_ae_preset_flag == TRUE && g_vprc_frm_cnt >= (g_vprc_frm_cnt_ae_preset + 3)){ + DBG_DUMP("triggered by AE preset\n"); + } + + + #if HUNTING_PHOTO_FAST_AE_60_FPS == ENABLE PhotoFast_SetTriggerFrmCnt(video_cap_frame.count); /* unbind mode , use vcap frame count */ #else PhotoFast_SetTriggerFrmCnt(video_frame.count); /* bind mode , vprc frame count = vcap frame count */ #endif start_cap = TRUE; + + DBG_DUMP("*** trigger frame count = %llu (start from 1)\n", video_cap_frame.count); /* UINT64, use %llu */ //Set_AEMODE(1); } @@ -1577,6 +1647,9 @@ exit: PhotoFast_PhotoClose(); vos_perf_list_mark("sie_vd", __LINE__, 3); #if HUNTING_CAMERA_MCU == ENABLE + #if SF_TRIGGER_TIME_TEST == ENABLE + sf_trigger_time_led_cb(0); + #endif if(sf_get_power_off_flag()) { vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); @@ -1608,21 +1681,32 @@ exit: */ #endif - switch (DrvGPIO_GetPhotoMovieModeFromMonitor()) { - case DX_HUNTING_MODE_PHOTO: - vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); - break; + + if(stop_flag == TRUE){ + /* Check if cmd task flag is already initialized or shutdown directly */ + if(PHOTOFAST_FLG_ID){ + vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); + } + else{ + PhotoFast_ShutDown(); + } + } + else{ - case DX_HUNTING_MODE_PHOTO_MOVIE: - case DX_HUNTING_MODE_CAMERA_PHOTO_MOVIE: - - - vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_CHGMODE); - break; + switch (DrvGPIO_GetPhotoMovieModeFromMonitor()) { + case DX_HUNTING_MODE_PHOTO: + vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); + break; - case DX_HUNTING_MODE_CAMERA_PHOTO: - vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); - break; + case DX_HUNTING_MODE_PHOTO_MOVIE: + case DX_HUNTING_MODE_CAMERA_PHOTO_MOVIE: + vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_CHGMODE); + break; + + case DX_HUNTING_MODE_CAMERA_PHOTO: + vos_flag_set(PHOTOFAST_FLG_ID, FLGPHOTOFAST_SHUTDOWN); + break; + } } } } @@ -1636,6 +1720,7 @@ exit: { #if POWERON_FAST_SLICE_ENC_VER2 == ENABLE + PhotoFast_CaptureStop(); PhotoFast_SliceEncode2_Close(); #endif PhotoFast_FileNaming_Close(); @@ -1688,17 +1773,11 @@ exit: static void PhotoFast_ShutDown(void) { + PhotoFast_CmdTsk_Exit(); #if (POWERON_FAST_BOOT_MSG == DISABLE) fastboot_msg_en(ENABLE); #endif -#if HUNTING_CAMERA_MCU == ENABLE - UIMenuStoreInfo *puiPara = sf_ui_para_get(); - if(puiPara->DebugMode == 0) - { - fastboot_msg_en(ENABLE); - } -#endif #if HUNTING_CAMERA_BOOT_LINUX /* Boot Linux */ @@ -1747,7 +1826,7 @@ void Set_NIGHTMODE(UINT32 id, UINT8 isSnapVideo) //IQT_EDGE_PARAM edge = {0}; - if(sf_is_night_mode(0) ==TRUE) + if(sf_is_night_mode(1) ==TRUE) { if ((hd_ret = vendor_isp_init()) != HD_OK) { DBG_ERR("vendor_isp_init() fail(%d)\r\n", hd_ret); @@ -1784,7 +1863,9 @@ void Set_NIGHTMODE(UINT32 id, UINT8 isSnapVideo) DBG_ERR("vendor_isp_uninit() fail(%d)\r\n", hd_ret); } - } + }else { + DrvGOIO_Turn_Onoff_IRCUT(1); + } #endif diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.h b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.h index 68126bded..ac16bca03 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.h +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFast.h @@ -9,8 +9,8 @@ #define FLGPHOTOFAST_SHUTDOWN 0x00000002 #define FLGPHOTOFAST_MASK FLGPTN_BIT_ALL -#define PHOTOFAST_CAP_FRAME_CNT 6 -#define PHOTOFAST_START_CAP_FRAME_CNT 10 +#define PHOTOFAST_AE_PRESET_FRAME_CNT 6 /* lock AE */ +#define PHOTOFAST_START_CAP_FRAME_CNT (PHOTOFAST_AE_PRESET_FRAME_CNT + 3*2) /* capture frame, it should be larger than PHOTOFAST_AE_PRESET_FRAME_CNT by 3 */ #define PHOTOFAST_HD_PUSH_PULL_TIMEOUT_MS 3000 // Naming rule & FileDB diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.c b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.c index 0ae9543d4..9b5690149 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.c +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.c @@ -1752,6 +1752,22 @@ INT32 PhotoFast_Sliceencode2_Enq_Frame(const HD_VIDEO_FRAME* video_frame) return E_OK; } +INT32 PhotoFast_Sliceencode2_Stop(void) +{ + PhotoFast_SliceEncode_Queue12_Param* queue_ele_out = NULL; + queue_ele_out = (PhotoFast_SliceEncode_Queue12_Param*) malloc(sizeof(PhotoFast_SliceEncode_Queue12_Param)); + memset(queue_ele_out, 0, sizeof(PhotoFast_SliceEncode_Queue12_Param)); + queue_ele_out->comm.terminate = 1; + + while (lfqueue_enq(&queue12, (void*) queue_ele_out) == -1) + { + vos_util_delay_ms(1); + DBG_ERR("ENQ Full ?\r\n"); + } + + return E_OK; +} + INT32 PhotoFast_SliceEncode_CB2(void* user_data) { INT32 ret = E_OK; @@ -1845,7 +1861,7 @@ INT32 PhotoFast_SliceEncode_CB2(void* user_data) } if(queue_ele_in->comm.terminate){ - DBG_ERR("force terminate\n"); + DBG_ERR("abort CB2\n"); free(queue_ele_in); queue_ele_in = NULL; goto EXIT; @@ -2035,7 +2051,7 @@ EXIT: lfqueue_enq(param->queue23, (void*) queue_ele_out); } - DBG_IND("task2 job finished\n"); + DBG_DUMP("task2 job finished\n"); return ret; } @@ -2065,7 +2081,7 @@ INT32 PhotoFast_SliceEncode_CB3(void* user_data) } if(queue_ele_in->comm.terminate){ - DBG_ERR("force terminate\n"); + DBG_ERR("abort CB3\n"); free(queue_ele_in); queue_ele_in = NULL; goto EXIT; @@ -2147,10 +2163,6 @@ INT32 PhotoFast_SliceEncode_CB3(void* user_data) EXIT: - if(param->cnt < param->max_cnt){ - DBG_ERR("force terminate\n"); - } - DBG_DUMP("task3 job finished\n"); return ret; diff --git a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.h b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.h index 923759ab7..6b649f038 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.h +++ b/rtos/code/application/source/cardv/SrcCode/UIApp/PhotoFast/PhotoFastSliceEncode.h @@ -8,7 +8,7 @@ #define CFG_PHOTOFAST_SLICE_ENC_PRIMARY_BUF_HEIGHT 1080 #define CFG_PHOTOFAST_SLICE_ENC_PRIMARY_BUF_SIZE VDO_YUV_BUFSIZE(CFG_PHOTOFAST_SLICE_ENC_PRIMARY_BUF_WIDTH, CFG_PHOTOFAST_SLICE_ENC_PRIMARY_BUF_HEIGHT, HD_VIDEO_PXLFMT_YUV420) #define CFG_PHOTOFAST_SLICE_ENC_BS_BUF_RATIO 8 /* (yuv size / ratio) + header = bs buf size */ -#define CFG_PHOTOFAST_SLICE_ENC_INIT_QUALITY_PRIMARY 85 +#define CFG_PHOTOFAST_SLICE_ENC_INIT_QUALITY_PRIMARY 99 #define CFG_PHOTOFAST_SLICE_ENC_INIT_QUALITY_THUMBNAIL 70 #define CFG_PHOTOFAST_SLICE_ENC_INIT_QUALITY_SCREENNAIL 70 #define CFG_PHOTOFAST_SLICE_ENC_QUALITY_STEP 5 @@ -44,7 +44,7 @@ INT32 PhotoFast_SliceEncode2_Open( VOID PhotoFast_SliceEncode2_Close(VOID); INT32 PhotoFast_Sliceencode2_Enq_Frame(const HD_VIDEO_FRAME* video_frame); - +INT32 PhotoFast_Sliceencode2_Stop(void); #endif #endif diff --git a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h index aaaf83601..b53b05733 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h +++ b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UICfgDefault.h @@ -220,5 +220,6 @@ #define DEFAULT_TIMESEND3_SWITCH SF_OFF #define DEFAULT_TIMESEND4_SWITCH SF_OFF #define DEFAULT_FTP_SWITCH SF_FTP_ON +#define DEFAULT_MULTISHOT_INTEVEL SF_MULTISHOT_INTEVEL_1S #endif diff --git a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c index be16b6126..60284d60e 100755 --- a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c +++ b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.c @@ -1146,7 +1146,8 @@ void SysResetFlag(void) puiPara->GpsAntiTheftSwitch = DEFAULT_GPS_ANTI_THEFT_SWITCH; puiPara->BatteryLogSwitch = DEFAULT_BATTRERY_LOG_SWITCH; puiPara->FtpSwitch = DEFAULT_FTP_SWITCH; - + puiPara->MultiShotIntevel = DEFAULT_MULTISHOT_INTEVEL; + memset(puiPara ->FtpIp,'\0', sizeof(puiPara ->FtpIp)); memset(puiPara ->FtpPort, '\0', sizeof(puiPara ->FtpPort)); memset(puiPara ->FtpUsr, '\0', sizeof(puiPara ->FtpUsr)); diff --git a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h index 51afaa1bf..fe500f35f 100644 --- a/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h +++ b/rtos/code/application/source/cardv/SrcCode/UIWnd/LVGL_SPORTCAM/UIInfo/UIInfo.h @@ -1979,6 +1979,13 @@ typedef enum SF_FTP_MAX, } SF_FTP; +typedef enum { + SF_MULTISHOT_INTEVEL_0S = 0, + SF_MULTISHOT_INTEVEL_1S, + SF_MULTISHOT_INTEVEL_2S, + SF_MULTISHOT_INTEVEL_MAX, +} SF_MULTISHOT_INTEVEL_e; + extern void Load_SysInfo(void); extern void Save_SysInfo(void); extern void Init_SysInfo(void); diff --git a/rtos/code/application/source/cardv/rtos-main-hunting_lvgl.lds b/rtos/code/application/source/cardv/rtos-main-hunting_lvgl.lds index 83c8dfba2..fa86ffc90 100644 --- a/rtos/code/application/source/cardv/rtos-main-hunting_lvgl.lds +++ b/rtos/code/application/source/cardv/rtos-main-hunting_lvgl.lds @@ -262,6 +262,7 @@ SECTIONS libnvt_ide.a(.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) libkflow_videodec.a(.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) ./SrcCode/FastFlow/flow_boot_logo.o (.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) + ./SrcCode/UIWnd/LVGL_SPORTCAM/Resource/BG_Opening.o (.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) #endif /* video codec */ @@ -278,9 +279,7 @@ SECTIONS libFsUitron.a(.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) libfiledb.a(.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) libDCF.a (.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) -#endif - - ./SrcCode/UIWnd/LVGL_SPORTCAM/Resource/BG_Opening.o (.text* .data* .data1* .rodata* .rodata1* .reginfo* .init* .exit*) +#endif } . = ALIGN(4); diff --git a/rtos/code/driver/na51089/include/sf_mcu.h b/rtos/code/driver/na51089/include/sf_mcu.h index deb564e49..c30db6fdb 100644 --- a/rtos/code/driver/na51089/include/sf_mcu.h +++ b/rtos/code/driver/na51089/include/sf_mcu.h @@ -475,6 +475,22 @@ typedef struct sf_FILE_ATTR_S { }SF_FILE_ATTR_S; +typedef enum MCU_FLAG_INIT { + MCU_FLAG_INITT_SYSTEM = 0x00, + MCU_FLAG_INIT_SENSOR = 0x01, + MCU_FLAG_INIT_CAPTURE = 0x02, + MCU_FLAG_INIT_DISPLAY = 0x03, + MCU_FLAG_INIT_STORAGE = 0x04, + MCU_FLAG_INIT_FILESYSOK = 0x05, + MCU_FLAG_INIT_FILENAMINGOK, + MCU_FLAG_INIT_MEIDA_ENCODER, + MCU_FLAG_INIT_MEIDA_DECODER, + MCU_FLAG_INIT_BOOTLOGO, + MCU_FLAG_INIT_OTHERS, + MCU_FLAG_INIT_BOOT, + MCU_FLAG_INIT_MAX_CNT = 32, //flag max bit cnt is 32 +} MCU_FLAG_INIT; + typedef struct sf_SRCFILE_ATTR_S { UINT8 filecnt; SF_FILE_ATTR_S stfileattr[SF_SRCFILE_MAX]; @@ -517,5 +533,11 @@ void sf_file_thumb_cfg_set(SF_SRCFILE_ATTR_S *pThumbFileCfgl); void sf_file_thumb_cfg_clear(void); void sf_file_thumb_cfg_sava(void); void sf_add_file_name_to_send_list(char *sendfname); +UINT8 sf_mcu_power_on_para_get(MCUParam_t attrId); +void sf_mcu_flag_init(void); +void sf_mcu_flag_set_done(MCU_FLAG_INIT boot_init); +void sf_mcu_flag_wait_done(MCU_FLAG_INIT boot_init); +int sf_mcu_flag_wait_done_timeout(MCU_FLAG_INIT boot_init, int timeout_ms); +void sf_mcu_flag_clear_done(MCU_FLAG_INIT boot_init); #endif diff --git a/rtos/code/driver/na51089/source/mcu/sf_commu_mcu.c b/rtos/code/driver/na51089/source/mcu/sf_commu_mcu.c index 70be41e0b..b5eac222c 100644 --- a/rtos/code/driver/na51089/source/mcu/sf_commu_mcu.c +++ b/rtos/code/driver/na51089/source/mcu/sf_commu_mcu.c @@ -60,7 +60,7 @@ extern "C" { #endif #endif - +extern void flow_preview_set_stop_flag(BOOL flag); unsigned char mcu_upgrade_buf[32]; unsigned char mcu_upgrade_buf_len; @@ -146,6 +146,44 @@ THREAD_RETTYPE sf_commu_mcu_task(void *arg); int gsfd = -1; +static ID sf_mcu_flag_id = 0; + +void sf_mcu_flag_init(void) +{ + vos_flag_create(&sf_mcu_flag_id, NULL, "sf_mcu_flag_id"); + vos_flag_clr(sf_mcu_flag_id, (FLGPTN)-1); +} + +void sf_mcu_flag_set_done(MCU_FLAG_INIT boot_init) +{ + vos_flag_set(sf_mcu_flag_id, (FLGPTN)(1 << boot_init)); +} + +void sf_mcu_flag_wait_done(MCU_FLAG_INIT boot_init) +{ + FLGPTN flgptn; + vos_flag_wait(&flgptn, sf_mcu_flag_id, (FLGPTN)(1 << boot_init), TWF_ANDW); +} + +int sf_mcu_flag_wait_done_timeout(MCU_FLAG_INIT boot_init, int timeout_ms) +{ + ER ret = E_OK; + FLGPTN flgptn; + + ret = vos_flag_wait_timeout(&flgptn, sf_mcu_flag_id, (FLGPTN)(1 << boot_init), TWF_ANDW, vos_util_msec_to_tick(timeout_ms)); + if(unlikely(ret != E_OK)){ + DBG_ERR("wait(%lu) init timeout(%ld ms)!\n", boot_init, timeout_ms); + } + + return ret; +} + +void sf_mcu_flag_clear_done(MCU_FLAG_INIT boot_init) +{ + //vos_flag_clr(sf_mcu_flag_id, (FLGPTN)(1 << boot_init)); + vos_flag_clr(sf_mcu_flag_id, (FLGPTN)-1); +} + void mcubuf_reset(void) { mcu_buf_len = 0; @@ -446,6 +484,17 @@ unsigned int sf_get_mcu_reg_ack_depack_many(unsigned char reg[], unsigned char v int sf_commu_wait(unsigned char cmd) { + //sf_mcu_flag_set_done(cmd); + if(sf_mcu_flag_wait_done_timeout(cmd, 30)) + { + sf_commu_reset(); + return - 1; + } + return 0; + //PhotoFast_FileNaming_Open(); + //fastboot_set_done(BOOT_INIT_FILENAMINGOK); + + /* volatile char trytimes = 0; while ((smap_buf.buf[2] != cmd || SMAP_waitAck == 0) && trytimes <= 100) { @@ -458,6 +507,7 @@ int sf_commu_wait(unsigned char cmd) return - 1; } return 0; + */ } void sf_commu_reset(void) @@ -467,6 +517,7 @@ void sf_commu_reset(void) memset(smap_buf.buf, 0x00, sizeof(smap_buf.buf)); memset(cmpRegBuf, 0x00, sizeof(cmpRegBuf)); memset(cmpValBuf, 0x00, sizeof(cmpValBuf)); + sf_mcu_flag_clear_done(0); } int sf_commu_set_mcu(unsigned char reg, unsigned char val) @@ -683,6 +734,7 @@ unsigned char sf_commu_parse_mcu_data(unsigned char * src, unsigned int len) //sf_com_message_send_to_app(&stMessageBuf); ret = 0x05; sf_set_power_off_flag(1); + flow_preview_set_stop_flag(TRUE); //Ux_PostEvent(NVTEVT_SYSTEM_SHUTDOWN, 1, APP_POWER_OFF_APO); } else @@ -831,6 +883,8 @@ THREAD_RETTYPE sf_commu_mcu_task(void *arg) memcpy(smap_buf.buf + smap_buf.index, &buffer[start], copy_size); smap_buf.index += copy_size; //index从0开始 SMAP_waitAck = 1; + //smap_buf.buf[2] + sf_mcu_flag_set_done(smap_buf.buf[2]); //printf("%s:%d SMAP_waitAck 1\n", __FUNCTION__, __LINE__); } diff --git a/rtos/code/driver/na51089/source/mcu/sf_mcu_dev.c b/rtos/code/driver/na51089/source/mcu/sf_mcu_dev.c index 23dfd358a..aa4b2848e 100644 --- a/rtos/code/driver/na51089/source/mcu/sf_mcu_dev.c +++ b/rtos/code/driver/na51089/source/mcu/sf_mcu_dev.c @@ -387,16 +387,33 @@ UINT8 sf_mcu_power_on_para_get(MCUParam_t attrId) if(attrId != SF_MCU_POWERON) { - sf_mcu_read(START_MODE, &dataTemp1); + mcuReg[i++] = START_MODE; + sf_mcu_read_multi(mcuReg, mcuData, i); + i = 0; + dataTemp1 = mcuData[i++]; startMode = dataTemp1 & 0x1F; - + DailyReportStartMode = (dataTemp1 & 0xc0) >> 6; + #if defined(_MODEL_565_HUNTING_EVB_LINUX_4G_S530_) + if(startMode == PWR_ON_TIME_SYNC) + { + startMode = PWR_ON_DAILY_REPORT; + } + else + #endif + { + if(startMode > PWR_ON_TIME_SEND) //if start mode err, USB IN default power on SETUP + { + startMode = PWR_ON_SETUP; + } + } + printf(" start mode = %d \n", startMode); return startMode; } mcuReg[i++] = MCU_SUB_VER; mcuReg[i++] = MCU_VER_L; mcuReg[i++] = MCU_VER_H; mcuReg[i++] = MCU_PRODUCT_INFO; - mcuReg[i++] = START_MODE; + //mcuReg[i++] = START_MODE; //mcuReg[i++] = LUMINANCE_L; //mcuReg[i++] = LUMINANCE_H; @@ -407,9 +424,9 @@ UINT8 sf_mcu_power_on_para_get(MCUParam_t attrId) McuVersion = mcuData[i++]; McuVersion = (UINT16)mcuData[i++] << 8 | McuVersion; McuProductInfo = mcuData[i++]; - dataTemp1 = mcuData[i++]; - startMode = dataTemp1 & 0x1F; - DailyReportStartMode = (dataTemp1 & 0xc0) >> 6; + //dataTemp1 = mcuData[i++]; + //startMode = dataTemp1 & 0x1F; + //DailyReportStartMode = (dataTemp1 & 0xc0) >> 6; //dataTemp1= mcuData[i++]; //dataTemp2 = mcuData[i++]; //IRSHTTER = (dataTemp2 << 8) | dataTemp1; @@ -440,7 +457,7 @@ UINT8 sf_mcu_power_on_para_get(MCUParam_t attrId) sf_mcu_read(LUMINANCE_H, &dataTemp2); IRSHTTER = (dataTemp2 << 8) | dataTemp1; #endif - + /* #if defined(_MODEL_565_HUNTING_EVB_LINUX_4G_S530_) if(startMode == PWR_ON_TIME_SYNC) { @@ -455,6 +472,7 @@ UINT8 sf_mcu_power_on_para_get(MCUParam_t attrId) } } printf(" start mode = %d \n", startMode); + */ //printf(" start mode = %d IRSHTTER = %d\n", startMode, IRSHTTER); sf_get_mcu_rtc_set_sys(); @@ -670,7 +688,8 @@ UINT8 sf_get_power_on_mode(void) if(ModeFlag) { ModeFlag = 0; - PowerOnMode = sf_mcu_power_on_para_get(SF_MCU_POWERON); + //PowerOnMode = sf_mcu_power_on_para_get(SF_MCU_POWERON); + PowerOnMode = sf_mcu_power_on_para_get(SF_MCU_STARTMODE); PowerOnMode &= 0x0f; //sf_is_night_mode(1); if(1 == PowerOnMode) @@ -1960,21 +1979,25 @@ int sf_while_flag(void) *************************************************/ UINT16 sf_mcu_get_irshtter(void) { + static BOOL isRefresh = 1; UINT8 dataTemp1 = 0, dataTemp2 = 0; UINT8 mcuReg[REG_SIZE] = { 0 }; UINT8 mcuData[REG_SIZE] = { 0 }; UINT8 i = 0; + if(isRefresh){ + isRefresh = 0; + mcuReg[i++] = LUMINANCE_L; + mcuReg[i++] = LUMINANCE_H; + sf_mcu_read_multi(mcuReg, mcuData, i); + i = 0; - mcuReg[i++] = LUMINANCE_L; - mcuReg[i++] = LUMINANCE_H; - sf_mcu_read_multi(mcuReg, mcuData, i); - i = 0; + dataTemp1= mcuData[i++]; + dataTemp2 = mcuData[i++]; + + IRSHTTER = (dataTemp2 << 8) | dataTemp1; + } - dataTemp1= mcuData[i++]; - dataTemp2 = mcuData[i++]; - - IRSHTTER = (dataTemp2 << 8) | dataTemp1; printf("%s:%d IRSHTTER = %d\n", __FUNCTION__, __LINE__, IRSHTTER); @@ -2082,14 +2105,16 @@ void sf_file_thumb_cfg_sava(void) //FileSys_CloseFile(fp); free(pThumbFileCfg); #endif - UINT8 fileIndex = 0; - for(fileIndex = 0; fileIndex < pThumbFileCfg->filecnt; fileIndex++) - { - sf_add_file_name_to_send_list(pThumbFileCfg->stfileattr[fileIndex].thumbfileName); - printf("%s:%d thumbfileSize:%ld thumbfileName:%s thumbfilePath:%s\n", __FUNCTION__, __LINE__,pThumbFileCfg->stfileattr[fileIndex].thumbfileSize,pThumbFileCfg->stfileattr[fileIndex].thumbfileName,pThumbFileCfg->stfileattr[fileIndex].thumbfilePath); + UINT8 fileIndex = 0; + if (pThumbFileCfg != NULL) { + for(fileIndex = 0; fileIndex < pThumbFileCfg->filecnt; fileIndex++) + { + sf_add_file_name_to_send_list(pThumbFileCfg->stfileattr[fileIndex].thumbfileName); + printf("%s:%d thumbfileSize:%ld thumbfileName:%s thumbfilePath:%s\n", __FUNCTION__, __LINE__,pThumbFileCfg->stfileattr[fileIndex].thumbfileSize,pThumbFileCfg->stfileattr[fileIndex].thumbfileName,pThumbFileCfg->stfileattr[fileIndex].thumbfilePath); + } + printf("%s:%d e Size:%ld\n", __FUNCTION__, __LINE__,pThumbFileCfg->stfileattr[fileIndex].thumbfileSize); + free(pThumbFileCfg); } - printf("%s:%d e Size:%ld\n", __FUNCTION__, __LINE__,pThumbFileCfg->stfileattr[fileIndex].thumbfileSize); - free(pThumbFileCfg); } /************************************************* diff --git a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi old mode 100755 new mode 100644 index ec3058692..ceb7a44ad --- a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi +++ b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_ae_0.dtsi @@ -7,7 +7,7 @@ version-info = [00 01 00 01]; ae_expect_lum { size = [b0 00 00 00]; - data = [3c 00 00 00 3c 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 3a 00 00 00 44 00 00 00 44 00 00 00 44 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 52 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00]; + data = [3c 00 00 00 3c 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 26 00 00 00 27 00 00 00 2c 00 00 00 32 00 00 00 3a 00 00 00 44 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 51 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 32 00 00 00 3c 00 00 00 46 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00 5a 00 00 00]; }; ae_la_clamp { size = [50 01 00 00]; diff --git a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi old mode 100755 new mode 100644 index dbeef5544..99eab2a2a --- a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi +++ b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_awb_0.dtsi @@ -15,7 +15,7 @@ }; awb_ct_weight { size = [78 00 00 00]; - data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 05 00 00 00 10 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00]; + data = [fc 08 00 00 f0 0a 00 00 74 0e 00 00 5c 12 00 00 64 19 00 00 f8 2a 00 00 48 03 00 00 60 03 00 00 bc 03 00 00 f7 03 00 00 23 04 00 00 c3 04 00 00 01 00 00 00 01 00 00 00 02 00 00 00 04 00 00 00 08 00 00 00 09 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 03 00 00 00 08 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00]; }; awb_target { size = [24 00 00 00]; diff --git a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi old mode 100755 new mode 100644 index afcda0174..975d30e65 --- a/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi +++ b/rtos/code/hdal/vendor/isp/configs/dtsi/os05b10_iq_0.dtsi @@ -11,7 +11,7 @@ }; iq_nr { size = [f4 12 00 00]; - data = [01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 ff 0f 00 00 00 01 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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