200 lines
9.5 KiB
C
Executable File
200 lines
9.5 KiB
C
Executable File
/*
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* MIPS register definitions, originally from:
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*
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* include/asm-mips/regdefs.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License, Version 2. See the file "COPYING" in the main directory of this
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* archive for more details.
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*
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* Copyright (C) 1994, 1995 by Ralf Baechle
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*/
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/*
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* Symbolic register names for 32 bit ABI
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*/
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# define Mode_USR 0x10 /* M[4:0] = 01010 */
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# define Mode_FIQ 0x11 /* M[4:0] = 10001 */
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# define Mode_IRQ 0x12 /* M[4:0] = 10010 */
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# define Mode_SVC 0x13 /* M[4:0] = 10011 */
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# define Mode_ABT 0x17 /* M[4:0] = 10111 */
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# define Mode_UNDEF 0x1B /* M[4:0] = 11011 */
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# define Mode_SYS 0x1F /* M[4:0] = 11111 */
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# define Mode_MSK 0x1F /* M[4:0] = 11111 */
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# define I_Bit 0x80 /* 7 6 5 4 3 2 1 0 */
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# define F_Bit 0x40 /* I F T M4 M3 M2 M1 M0 */
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/*
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************************************************************************
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* Cache Size ID Register, CCSIDR (cp15, 1, c0, c0, 0) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |W|W|R|W|NumSets |Associativity |L |
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* |T|B|A|A| | |S |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_CCSIDR_WT 31
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#define M_CCSIDR_WT (0x1 << S_CCSIDR_WT) /* Support write-through */
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#define S_CCSIDR_WB 30
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#define M_CCSIDR_WB (0x1 << S_CCSIDR_WB) /* Support write-back */
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#define S_CCSIDR_RA 29
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#define M_CCSIDR_RA (0x1 << S_CCSIDR_RA) /* Support read-allocation */
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#define S_CCSIDR_WA 28
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#define M_CCSIDR_WA (0x1 << S_CCSIDR_WA) /* Support write-allocation */
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#define S_CCSIDR_SETS 13
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#define M_CCSIDR_SETS (0x7fff << S_CCSIDR_SETS) /* Number of sets */
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#define S_CCSIDR_A 3
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#define M_CCSIDR_A (0x3ff << S_CCSIDR_A) /* Number of associatiovity */
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#define S_CCSIDR_LS 0
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#define M_CCSIDR_LS (0x7 << S_CCSIDR_LS) /* Cache line size */
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/*
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************************************************************************
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* Cache Level ID Register, CLIDR (cp15, 1, c0, c0, 1) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |0|0|LoUU |LoC |LoUIS|CT7 |CT6 |CT5 |CT4 |CT3 |CT2 |CT1 |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_CLIDR_LoUU 27
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#define M_CLIDR_LoUU (0x7 << S_CLIDR_LoUU)
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#define S_CLIDR_LoC 24
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#define M_CLIDR_LoC (0x7 << S_CLIDR_LoC) /* Cache cohernecy level */
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#define S_CLIDR_LoUIS 21
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#define M_CLIDR_LoUIS (0x7 << S_CLIDR_LoUIS)
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#define S_CLIDR_Ctype7 18
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#define M_CLIDR_Ctype7 (0x7 << S_CLIDR_Ctype7) /* Cache type of level 7 cache */
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#define S_CLIDR_Ctype6 15
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#define M_CLIDR_Ctype6 (0x7 << S_CLIDR_Ctype6) /* Cache type of level 6 cache */
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#define S_CLIDR_Ctype5 12
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#define M_CLIDR_Ctype5 (0x7 << S_CLIDR_Ctype5) /* Cache type of level 5 cache */
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#define S_CLIDR_Ctype4 9
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#define M_CLIDR_Ctype4 (0x7 << S_CLIDR_Ctype4) /* Cache type of level 4 cache */
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#define S_CLIDR_Ctype3 6
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#define M_CLIDR_Ctype3 (0x7 << S_CLIDR_Ctype3) /* Cache type of level 3 cache */
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#define S_CLIDR_Ctype2 3
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#define M_CLIDR_Ctype2 (0x7 << S_CLIDR_Ctype2) /* Cache type of level 2 cache */
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#define S_CLIDR_Ctype1 0
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#define M_CLIDR_Ctype1 (0x7 << S_CLIDR_Ctype1) /* Cache type of level 1 cache */
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#define K_CLIDR_Ctype_NO 0 /* No cache */
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#define K_CLIDR_Ctype_IC 1 /* Instruction cache only */
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#define K_CLIDR_Ctype_DC 2 /* Data cache only */
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#define K_CLIDR_Ctype_ID 3 /* Seperate instruction and data caches, Harvard cache */
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#define K_CLIDR_Ctype_U 4 /* Unified cache, von Neumann cacge */
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/*
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************************************************************************
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* Cache Size Selection Register, CCSELR (cp15, 2, c0, c0, 0) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |Reserved |Level|I|
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* | | |n|
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* | | |D|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_CCSELR_Level 1
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#define M_CCSELR_Level (0x7 << S_CCSELR_Level) /* Cache level */
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#define S_CCSELR_InD 0
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#define M_CCSELR_InD (0x1 << S_CCSELR_InD) /* I$ or D$ */
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/*
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************************************************************************
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* System Control Register, SCTLR (cp15, 0, c1, c0, 0) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |R|T|A|T|N|0|E|V|1|U|F|U|W|1|H|1|0|R|V|I|Z|S|0|0|B|1|B|1|1|C|A|M|
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* | |E|F|R|M| |E|E| | |I|W|X| |A| | | | | | |W| | | | |E| | | | | |
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* | | |E|E|F| | | | | | |X|N| | | | | | | | | | | | | |N| | | | | |
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* | | | | |I| | | | | | |N| | | | | | | | | | | | | | | | | | | | |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_SCTLR_TE 30
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#define M_SCTLR_TE (0x1 << S_SCTLR_TE) /* Thumb exception enable */
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#define S_SCTLR_AFE 29
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#define M_SCTLR_AFE (0x1 << S_SCTLR_AFE) /* Access flag enable */
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#define S_SCTLR_TRE 28
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#define M_SCTLR_TRE (0x1 << S_SCTLR_TRE) /* TXE remap enable */
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#define S_SCTLR_NMFI 27
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#define M_SCTLR_NMFI (0x1 << S_SCTLR_NMFI) /* None-maskable FIQ enbale (RO) */
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#define S_SCTLR_EE 25
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#define M_SCTLR_EE (0x1 << S_SCTLR_EE) /* Exception Endianness: big-endian */
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#define S_SCTLR_VE 24
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#define M_SCTLR_VE (0x1 << S_SCTLR_VE) /* Interrupt Vector Enable */
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#define S_SCTLR_FI 21
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#define M_SCTLR_FI (0x1 << S_SCTLR_FI) /* Fast interrupt configuraiont enable */
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#define S_SCTLR_UWXN 20
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#define M_SCTLR_UWXN (0x1 << S_SCTLR_UWXN) /* */
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#define S_SCTLR_WXN 19
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#define M_SCTLR_WXN (0x1 << S_SCTLR_WXN)
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#define S_SCTLR_HA 17
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#define M_SCTLR_HA (0x1 << S_SCTLR_HA) /* Hardware access flag enable */
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#define S_SCTLR_RR 14
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#define M_SCTLR_RR (0x1 << S_SCTLR_RR) /* Round-robin select */
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#define S_SCTLR_V 13
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#define M_SCTLR_V (0x1 << S_SCTLR_V) /* Vector bits */
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#define S_SCTLR_I 12
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#define M_SCTLR_I (0x1 << S_SCTLR_I) /* Instruction cache enable */
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#define S_SCTLR_Z 11
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#define M_SCTLR_Z (0x1 << S_SCTLR_Z) /* Branch prediction enable */
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#define S_SCTLR_SW 10
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#define M_SCTLR_SW (0x1 << S_SCTLR_SW) /* SW and SWP enable */
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#define S_SCTLR_CP15BEN 5
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#define M_SCTLR_CP15BEN (0x1 << S_SCTLR_CP15BEN) /* CP15 barrier support */
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#define S_SCTLR_C 2
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#define M_SCTLR_C (0x1 << S_SCTLR_C) /* Data and Unidied cache enable */
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#define S_SCTLR_A 1
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#define M_SCTLR_A (0x1 << S_SCTLR_A) /* Alignment fault checking enable */
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#define S_SCTLR_M 0
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#define M_SCTLR_M (0x1 << S_SCTLR_M) /* PL1&0 stage MMU enable */
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/************************************************************************
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* Auxiliary Control Register, ACTLR (cp15, 0, c1, c0, 1) *
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************************************************************************
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |UNP/SBZP |P|A|E|S|RAZ|W|L|L|F|
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* | |a|l|X|M| | |1|2|W|
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* | |r|l|C|P| |f| | | |
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* | | |o|L| | |l|p|p| |
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* | |o|c| | | | |r|r| |
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* | |n| | | | |z|e|e| |
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* | | |o| | | |e|f|f| |
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* | | |n| | | |r| | | |
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* | | |e| | | |o|e|e| |
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* | | | | | | |s|n|n| |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define S_ACTLR_PAR_ON 9
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#define M_ACTLR_PAR_ON (0x1 << S_ACTLR_PAR_ON) /* Parity on */
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#define S_ACTLR_ALLOC_ONE 8
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#define M_ACTLR_ALLOC_ONE (0x1 << S_ACTLR_ALLOC_ONE) /* Alloc in one way */
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#define S_ACTLR_EXCL 7
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#define M_ACTLR_EXCL (0x1 << S_ACTLR_EXCL) /* Exclusive cache */
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#define S_ACTLR_SMP 6
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#define M_ACTLR_SMP (0x1 << S_ACTLR_SMP) /* SMP */
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#define S_ACTLR_W_FL_ZEROS 3
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#define M_ACTLR_W_FL_ZEROS (0x1 << S_ACTLR_W_FL_ZEROS) /* Write full line of zeros mode */
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#define S_ACTLR_L1_PERF_EN 2
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#define M_ACTLR_L1_PERF_EN (0x1 << S_ACTLR_L1_PERF_EN) /* Dside prefetch enable */
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#define S_ACTLR_L2_PERF_EN 1
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#define M_ACTLR_L2_PERF_EN (0x1 << S_ACTLR_L2_PERF_EN) /* L2 prefetch enable */
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#define S_ACTLR_FW 0
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#define M_ACTLR_FW (0x1 << S_ACTLR_FW) /* Cache and TLB maintenance boardcast */
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