147 lines
4.7 KiB
C
Executable File
147 lines
4.7 KiB
C
Executable File
/*
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RSA driver header file
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RSA driver header file.
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@file rsa.h
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@ingroup mIDrvMisc_RSA
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@note Nothing
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Copyright Novatek Microelectronics Corp. 2020. All rights reserved.
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*/
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#ifndef _RSA_H
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#define _RSA_H
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#include <kwrap/nvt_type.h>
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/**
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@addtogroup mIDrvMisc_RSA
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*/
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/**
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Rsa engine clock rate
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*/
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typedef enum
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{
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RSA_CLOCK_240MHz = 0x00, ///< Select RSA clock rate 240 MHz
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RSA_CLOCK_320MHz, ///< Select RSA clock rate 320 MHz
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RSA_CLOCK_Reserved, ///< Select RSA clock rate Reserved
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RSA_CLOCK_PLL9, ///< Select RSA clock rate PLL9(for IDE/ETH)
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RSA_CLOCK_RATE_NUM,
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ENUM_DUMMY4WORD(RSA_CLOCK_RATE)
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} RSA_CLOCK_RATE;
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//@{
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/**
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Rsa engine Key Width
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*/
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typedef enum
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{
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RSA_KEY_256 = 0x00, ///< Select RSA key width for 256 bit
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RSA_KEY_512, ///< Select RSA key width for 512 bit
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RSA_KEY_1024, ///< Select RSA key width for 1024 bit
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RSA_KEY_2048, ///< Select RSA key width for 2048 bit
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RSA_KEY_4096, ///< Select RSA key width for 4096 bit
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RSA_KEY_NUM,
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ENUM_DUMMY4WORD(RSA_KEY)
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} RSA_KEY;
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/**
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Rsa engine Key Width
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*/
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typedef enum
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{
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RSA_MODE_NORMAL = 0x00, ///< Select RSA mode for encryption or decryption
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RSA_MODE_CRC_KEY_ED, ///< Select RSA mode for Key E/D CRC check
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RSA_MODE_CRC_KEY_N = 0x03, ///< Select RSA mode for Key N CRC check
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RSA_MODE_NUM,
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ENUM_DUMMY4WORD(RSA_MODE_CFG)
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} RSA_MODE_CFG;
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/**
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Rsa engine CRC32 Configuration
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*/
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typedef enum
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{
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RSA_CRC_INIT = 0x00, ///< Select RSA mode for encryption or decryption
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RSA_CRC_POLY, ///< Select RSA mode for Key N CRC check
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RSA_CRC_NUM,
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ENUM_DUMMY4WORD(RSA_CRC)
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} RSA_CRC;
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/**
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Rsa order
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*/
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typedef enum
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{
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RSA_ORDER_LSB_FIRST = 0x00, ///< Select RSA order for lsb byte first
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RSA_ORDER_MSB_FIRST, ///< Select RSA order for msb byte first
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RSA_ORDER_NUM,
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ENUM_DUMMY4WORD(RSA_ORDER_CFG)
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} RSA_ORDER_CFG;
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/**
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Rsa configuration identifier
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@note For Rsa_setConfig()
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*/
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typedef enum
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{
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RSA_CONFIG_ID_CLOCK_RATE, ///< Select RSA engine internal clock rate usage
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///< Context can be any of:
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///< - @b RSA_CLOCK_240MHz: Internal clock rate 240MHz
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///< - @b RSA_CLOCK_320MHz: Internal clock rate 320MHz
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///< - @b RSA_CLOCK_PLL9: Internal clock rate PLL9
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RSA_CONFIG_ID_KEY_WIDTH, ///< Select RSA engine key width usage
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///< Context can be any of:
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///< - @b RSA_KEY_256
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///< - @b RSA_KEY_512
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///< - @b RSA_KEY_1024
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///< - @b RSA_KEY_2048
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///< - @b RSA_KEY_4096
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RSA_CONFIG_ID_MODE, ///< Select RSA engine operation mode usage
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///< Context can be any of:
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///< - @b RSA_MODE_NORMAL
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///< - @b RSA_MODE_CRC_KEY_ED
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///< - @b RSA_MODE_CRC_KEY_N
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RSA_CONFIG_ID_CRC32, ///< Select RSA engine CRC32 Initial Value and Polynoms
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///< Context can be any of:
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///< - @b RSA_CRC_INIT
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///< - @b RSA_CRC_POLY
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RSA_CONFIG_ID_REORDER, ///< Select RSA engine byte order usage
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///< Context can be any of:
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///< - @b RSA_ORDER_LSB_FIRST
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///< - @b RSA_ORDER_MSB_FIRST
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ENUM_DUMMY4WORD(RSA_CONFIG_ID)
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} RSA_CONFIG_ID;
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extern ER rsa_open(void);
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extern ER rsa_close(void);
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extern ER rsa_setConfig(RSA_CONFIG_ID cfgid, UINT32 cfgvalue);
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extern void rsa_setkey_n(UINT8* key, UINT32 len, UINT32 msb_first);
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extern void rsa_setkey_ed(UINT8* key, UINT32 len, UINT32 msb_first);
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extern void rsa_pio_enable(UINT8* data, UINT32 len, UINT32 msb_first);
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extern void rsa_getOutput(UINT8 * Output, UINT32 len);
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extern void rsa_getKey_ed(UINT8 * key);
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extern void rsa_KeyCheck(UINT32 * Output, UINT32 crc_init, UINT32 key_poly);
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#if defined(_NVT_FPGA_) || defined(_NVT_EMULATION_)
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extern int rsa_CheckSRAM(UINT32 sram_mask, UINT32 pattern);
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#endif
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//@}
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#endif /* _RSA_H */
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