77 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			77 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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 * Copyright 2015 Freescale Semiconductor, Inc.
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 */
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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	u32 n_ranks;
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	u32 datarate_mhz_high;
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	u32 rank_gb;
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	u32 clk_adjust;
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	u32 wrlvl_start;
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	u32 wrlvl_ctl_2;
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	u32 wrlvl_ctl_3;
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};
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/*
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 * These tables contain all valid speeds we want to override with board
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 * specific parameters. datarate_mhz_high values need to be in ascending order
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 * for each n_ranks group.
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 */
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static const struct board_specific_parameters udimm0[] = {
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	/*
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	 * memory controller 0
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	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
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	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
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	 */
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	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
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	{2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
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	{2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
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	{2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
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	{}
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};
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/* DP-DDR DIMM */
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static const struct board_specific_parameters udimm2[] = {
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	/*
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	 * memory controller 2
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	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
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	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
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	 */
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	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
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	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
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	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
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	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
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	{}
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};
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static const struct board_specific_parameters rdimm0[] = {
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	/*
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	 * memory controller 0
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	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
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	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
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	 */
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	{2,  1666, 0, 8,     0x0F, 0x0D0C0A09, 0x0B0C0E08,},
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	{2,  1900, 0, 8,     0x10, 0x0F0D0B0A, 0x0B0E0F09,},
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	{2,  2200, 0, 8,     0x13, 0x120F0E0B, 0x0D10110B,},
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	{}
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};
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static const struct board_specific_parameters *udimms[] = {
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	udimm0,
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	udimm0,
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	udimm2,
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};
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static const struct board_specific_parameters *rdimms[] = {
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	rdimm0,
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	rdimm0,
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	udimm2,	/* DP-DDR doesn't support RDIMM */
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};
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#endif
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