286 lines
6.5 KiB
C
286 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 1994 - 1999 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1994 - 1999 by Ralf Baechle
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*
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* Changed set_except_vector declaration to allow return of previous
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* vector address value - necessary for "borrowing" vectors.
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*
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* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <asm/asm.h>
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#include <asm/sgidefs.h>
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#include <asm/ptrace.h>
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#include <linux/stringify.h>
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#if 0
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#include <linux/kernel.h>
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#endif
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static __inline__ void
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__sti(void)
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{
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\treorder\n\t"
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".set\tnoat\n\t"
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"mfc0\t$1,$12\n\t"
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"ori\t$1,0x1f\n\t"
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"xori\t$1,0x1e\n\t"
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"mtc0\t$1,$12\n\t"
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".set\tpop\n\t"
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: /* no outputs */
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: /* no inputs */
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: "$1", "memory");
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}
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/*
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* For cli() we have to insert nops to make shure that the new value
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* has actually arrived in the status register before the end of this
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* macro.
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* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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* no nops at all.
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*/
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static __inline__ void
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__cli(void)
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{
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\treorder\n\t"
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".set\tnoat\n\t"
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"mfc0\t$1,$12\n\t"
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"ori\t$1,1\n\t"
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"xori\t$1,1\n\t"
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".set\tnoreorder\n\t"
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"mtc0\t$1,$12\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set\tpop\n\t"
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: /* no outputs */
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: /* no inputs */
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: "$1", "memory");
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}
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#define __save_flags(x) \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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"mfc0\t%0,$12\n\t" \
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".set\tpop\n\t" \
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: "=r" (x))
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#define __save_and_cli(x) \
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__asm__ __volatile__( \
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".set\tpush\n\t" \
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".set\treorder\n\t" \
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".set\tnoat\n\t" \
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"mfc0\t%0,$12\n\t" \
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"ori\t$1,%0,1\n\t" \
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"xori\t$1,1\n\t" \
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".set\tnoreorder\n\t" \
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"mtc0\t$1,$12\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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".set\tpop\n\t" \
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: "=r" (x) \
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: /* no inputs */ \
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: "$1", "memory")
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#define __restore_flags(flags) \
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do { \
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unsigned long __tmp1; \
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\
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__asm__ __volatile__( \
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".set\tnoreorder\t\t\t# __restore_flags\n\t" \
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".set\tnoat\n\t" \
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"mfc0\t$1, $12\n\t" \
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"andi\t%0, 1\n\t" \
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"ori\t$1, 1\n\t" \
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"xori\t$1, 1\n\t" \
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"or\t%0, $1\n\t" \
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"mtc0\t%0, $12\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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".set\tat\n\t" \
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".set\treorder" \
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: "=r" (__tmp1) \
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: "0" (flags) \
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: "$1", "memory"); \
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} while(0)
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#ifdef CONFIG_SMP
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extern void __global_sti(void);
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extern void __global_cli(void);
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extern unsigned long __global_save_flags(void);
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extern void __global_restore_flags(unsigned long);
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# define sti() __global_sti()
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# define cli() __global_cli()
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# define save_flags(x) do { x = __global_save_flags(); } while (0)
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# define restore_flags(x) __global_restore_flags(x)
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# define save_and_cli(x) do { save_flags(x); cli(); } while(0)
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#else /* Single processor */
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# define sti() __sti()
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# define cli() __cli()
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# define save_flags(x) __save_flags(x)
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# define save_and_cli(x) __save_and_cli(x)
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# define restore_flags(x) __restore_flags(x)
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#endif /* SMP */
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/* For spinlocks etc */
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#define local_irq_save(x) __save_and_cli(x);
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#define local_irq_restore(x) __restore_flags(x);
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#define local_irq_disable() __cli();
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#define local_irq_enable() __sti();
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/*
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* These are probably defined overly paranoid ...
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*/
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define rmb() do { } while(0)
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#define wmb() wbflush()
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#define mb() wbflush()
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#else /* CONFIG_CPU_HAS_WB */
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#define mb() \
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__asm__ __volatile__( \
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"# prevent instructions being moved around\n\t" \
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".set\tnoreorder\n\t" \
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"# 8 nops to fool the R4400 pipeline\n\t" \
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"nop;nop;nop;nop;nop;nop;nop;nop\n\t" \
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".set\treorder" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#define rmb() mb()
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#define wmb() mb()
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#endif /* CONFIG_CPU_HAS_WB */
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#define set_mb(var, value) \
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do { var = value; mb(); } while (0)
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#define set_wmb(var, value) \
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do { var = value; wmb(); } while (0)
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#if !defined (_LANGUAGE_ASSEMBLY)
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/*
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* switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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#if 0
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extern asmlinkage void *resume(void *last, void *next);
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#endif
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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#define prepare_to_switch() do { } while(0)
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#define switch_to(prev,next,last) \
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do { \
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(last) = resume(prev, next); \
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} while(0)
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/*
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* For 32 and 64 bit operands we can take advantage of ll and sc.
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* FIXME: This doesn't work for R3000 machines.
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*/
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static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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#ifdef CONFIG_CPU_HAS_LLSC
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unsigned long dummy;
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__asm__ __volatile__(
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".set\tnoreorder\t\t\t# xchg_u32\n\t"
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".set\tnoat\n\t"
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"ll\t%0, %3\n"
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"1:\tmove\t$1, %2\n\t"
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"sc\t$1, %1\n\t"
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"beqzl\t$1, 1b\n\t"
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" ll\t%0, %3\n\t"
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".set\tat\n\t"
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".set\treorder"
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: "=r" (val), "=o" (*m), "=r" (dummy)
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: "o" (*m), "2" (val)
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: "memory");
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return val;
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#else
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unsigned long flags, retval;
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save_flags(flags);
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cli();
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retval = *m;
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*m = val;
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restore_flags(flags);
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return retval;
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#endif /* Processor-dependent optimization */
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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static __inline__ unsigned long
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__xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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}
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return x;
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}
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extern void *set_except_vector(int n, void *addr);
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extern void __die(const char *, struct pt_regs *, const char *where,
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unsigned long line) __attribute__((noreturn));
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extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
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unsigned long line);
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#define die(msg, regs) \
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__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
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#define die_if_kernel(msg, regs) \
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__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
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static inline void execution_hazard_barrier(void)
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{
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__asm__ __volatile__(
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".set noreorder\n"
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"ehb\n"
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".set reorder");
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}
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static inline void instruction_hazard_barrier(void)
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{
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unsigned long tmp;
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asm volatile(
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__stringify(PTR_LA) "\t%0, 1f\n"
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" jr.hb %0\n"
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"1: .insn"
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: "=&r"(tmp));
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}
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#endif /* _ASM_SYSTEM_H */
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