148 lines
3.4 KiB
C
148 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RCar Gen3 memory map tables
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*
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* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#define GEN3_NR_REGIONS 16
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static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x03F00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x47E00000UL,
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.phys = 0x47E00000UL,
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.size = 0x78200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xc0000000UL,
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.phys = 0xc0000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x100000000UL,
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.phys = 0x100000000UL,
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.size = 0xf00000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = gen3_mem_map;
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DECLARE_GLOBAL_DATA_PTR;
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void enable_caches(void)
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{
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u64 start, size;
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int bank, i = 0;
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/* Create map for RPC access */
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gen3_mem_map[i].virt = 0x0ULL;
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gen3_mem_map[i].phys = 0x0ULL;
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gen3_mem_map[i].size = 0x40000000ULL;
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gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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i++;
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/* Generate entires for DRAM in 32bit address space */
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = gd->bd->bi_dram[bank].start;
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size = gd->bd->bi_dram[bank].size;
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/* Skip empty DRAM banks */
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if (!size)
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continue;
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/* Skip DRAM above 4 GiB */
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if (start >> 32ULL)
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continue;
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/* Mark memory reserved by ATF as cacheable too. */
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if (start == 0x48000000) {
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/* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
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gen3_mem_map[i].virt = 0x40000000ULL;
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gen3_mem_map[i].phys = 0x40000000ULL;
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gen3_mem_map[i].size = 0x03F00000ULL;
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gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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i++;
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start = 0x47E00000ULL;
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size += 0x00200000ULL;
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}
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gen3_mem_map[i].virt = start;
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gen3_mem_map[i].phys = start;
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gen3_mem_map[i].size = size;
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gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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i++;
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}
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/* Create map for register access */
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gen3_mem_map[i].virt = 0xc0000000ULL;
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gen3_mem_map[i].phys = 0xc0000000ULL;
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gen3_mem_map[i].size = 0x40000000ULL;
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gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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i++;
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/* Generate entires for DRAM in 64bit address space */
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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start = gd->bd->bi_dram[bank].start;
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size = gd->bd->bi_dram[bank].size;
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/* Skip empty DRAM banks */
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if (!size)
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continue;
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/* Skip DRAM below 4 GiB */
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if (!(start >> 32ULL))
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continue;
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gen3_mem_map[i].virt = start;
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gen3_mem_map[i].phys = start;
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gen3_mem_map[i].size = size;
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gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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i++;
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}
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/* Zero out the remaining regions. */
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for (; i < GEN3_NR_REGIONS; i++) {
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gen3_mem_map[i].virt = 0;
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gen3_mem_map[i].phys = 0;
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gen3_mem_map[i].size = 0;
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gen3_mem_map[i].attrs = 0;
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}
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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