141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018-2019 NXP
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*/
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#ifndef __LX2_QDS_H
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#define __LX2_QDS_H
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#include "lx2160a_common.h"
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/* Qixis */
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#define QIXIS_XMAP_MASK 0x07
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#define QIXIS_XMAP_SHIFT 5
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#define QIXIS_RST_CTL_RESET_EN 0x30
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x20
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_QSPI 0xff
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SD
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#define QIXIS_RCW_SRC_SD 0x08
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#define NON_EXTENDED_DUTCFG
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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/* SYSCLK */
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#define QIXIS_SYSCLK_100 0x0
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#define QIXIS_SYSCLK_125 0x1
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#define QIXIS_SYSCLK_133 0x2
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/* DDRCLK */
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#define QIXIS_DDRCLK_100 0x0
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#define QIXIS_DDRCLK_125 0x1
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#define QIXIS_DDRCLK_133 0x2
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#define BRDCFG4_EMI1SEL_MASK 0xF8
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#define BRDCFG4_EMI1SEL_SHIFT 3
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#define BRDCFG4_EMI2SEL_MASK 0x07
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#define BRDCFG4_EMI2SEL_SHIFT 0
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/* VID */
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#define I2C_MUX_CH_VOL_MONITOR 0xA
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x63
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
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#define CONFIG_VID
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/* The lowest and highest voltage allowed*/
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#define VDD_MV_MIN 775
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#define VDD_MV_MAX 925
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/* PM Bus commands code for LTC3882*/
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#define PMBUS_CMD_PAGE 0x0
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#define PMBUS_CMD_READ_VOUT 0x8B
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#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
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#define PMBUS_CMD_VOUT_COMMAND 0x21
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#define PWM_CHANNEL0 0x0
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#define CONFIG_VOL_MONITOR_LTC3882_SET
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#define CONFIG_VOL_MONITOR_LTC3882_READ
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/* RTC */
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#define CONFIG_SYS_RTC_BUS_NUM 0
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#define I2C_MUX_CH_RTC 0xB
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/*
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* MMC
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*/
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#ifdef CONFIG_MMC
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#ifndef __ASSEMBLY__
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u8 qixis_esdhc_detect_quirk(void);
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#endif
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#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
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#endif
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/* MAC/PHY configuration */
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#if defined(CONFIG_FSL_MC_ENET)
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
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#define AQ_PHY_ADDR1 0x00
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#define AQ_PHY_ADDR2 0x01
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#define AQ_PHY_ADDR3 0x02
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#define AQ_PHY_ADDR4 0x03
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#define CORTINA_NO_FW_UPLOAD
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#define CORTINA_PHY_ADDR1 0x0
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#define INPHI_PHY_ADDR1 0x0
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#define INPHI_PHY_ADDR2 0x1
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#define RGMII_PHY_ADDR1 0x01
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#define RGMII_PHY_ADDR2 0x02
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#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
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#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
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#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
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#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXTRA_ENV_SETTINGS \
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"lx2160aqds_vdd_mv=800\0" \
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"BOARD=lx2160aqds\0" \
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"xspi_bootcmd=echo Trying load from flexspi..;" \
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"sf probe 0:0 && sf read $load_addr " \
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"$kernel_start $kernel_size ; env exists secureboot &&" \
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"sf read $kernelheader_addr_r $kernelheader_start " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
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" bootm $load_addr#$BOARD\0" \
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"sd_bootcmd=echo Trying load from sd card..;" \
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"mmcinfo; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd ;" \
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"env exists secureboot && mmc read $kernelheader_addr_r "\
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$BOARD\0"
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#include <asm/fsl_secure_boot.h>
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#endif /* __LX2_QDS_H */
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