59 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			59 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (c) 2008-2011 Atheros Communications Inc.
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|  *
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|  * Permission to use, copy, modify, and/or distribute this software for any
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|  * purpose with or without fee is hereby granted, provided that the above
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|  * copyright notice and this permission notice appear in all copies.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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|  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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|  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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|  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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|  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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|  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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|  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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|  */
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| 
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| #ifndef PHY_H
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| #define PHY_H
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| 
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| #define CHANSEL_DIV		15
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| #define CHANSEL_2G(_freq)	(((_freq) * 0x10000) / CHANSEL_DIV)
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| #define CHANSEL_5G(_freq)	(((_freq) * 0x8000) / CHANSEL_DIV)
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| 
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| #define AR_PHY_BASE     0x9800
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| #define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))
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| 
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| #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX   0x0007E000
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| #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
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| #define AR_PHY_TX_GAIN_CLC       0x0000001E
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| #define AR_PHY_TX_GAIN_CLC_S     1
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| #define AR_PHY_TX_GAIN           0x0007F000
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| #define AR_PHY_TX_GAIN_S         12
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| 
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| #define AR_PHY_CLC_TBL1      0xa35c
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| #define AR_PHY_CLC_I0        0x07ff0000
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| #define AR_PHY_CLC_I0_S      16
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| #define AR_PHY_CLC_Q0        0x0000ffd0
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| #define AR_PHY_CLC_Q0_S      5
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| 
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| #define ANTSWAP_AB 0x0001
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| #define REDUCE_CHAIN_0 0x00000050
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| #define REDUCE_CHAIN_1 0x00000051
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| #define AR_PHY_CHIP_ID 0x9818
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| 
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| #define	AR_PHY_TIMING11_SPUR_FREQ_SD		0x3FF00000
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| #define	AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
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| 
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| #define AR_PHY_PLL_CONTROL 0x16180
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| #define AR_PHY_PLL_MODE 0x16184
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| 
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| enum ath9k_ant_div_comb_lna_conf {
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| 	ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
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| 	ATH_ANT_DIV_COMB_LNA2,
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| 	ATH_ANT_DIV_COMB_LNA1,
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| 	ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
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| };
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| 
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| #endif
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