297 lines
6.6 KiB
C
297 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
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*
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
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* Copyright (C) 2015 Wenyou Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#if !defined(CONFIG_AT91FAMILY)
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# error You need to define CONFIG_AT91FAMILY in your board config!
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static unsigned long at91_css_to_rate(unsigned long css)
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{
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switch (css) {
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case AT91_PMC_MCKR_CSS_SLOW:
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return CONFIG_SYS_AT91_SLOW_CLOCK;
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case AT91_PMC_MCKR_CSS_MAIN:
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return gd->arch.main_clk_rate_hz;
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case AT91_PMC_MCKR_CSS_PLLA:
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return gd->arch.plla_rate_hz;
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}
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return 0;
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}
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static u32 at91_pll_rate(u32 freq, u32 reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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mul = (reg >> 18) & 0x7f;
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if (div && mul) {
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freq /= div;
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freq *= mul + 1;
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} else {
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freq = 0;
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}
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return freq;
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}
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int at91_clock_init(unsigned long main_clock)
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{
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unsigned freq, mckr;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
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unsigned tmp;
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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* or when using oscillator bypass mode, we must be told the speed
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* of the main clock.
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*/
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if (!main_clock) {
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do {
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tmp = readl(&pmc->mcfr);
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} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
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tmp &= AT91_PMC_MCFR_MAINF_MASK;
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main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
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}
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#endif
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gd->arch.main_clk_rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = readl(&pmc->mckr);
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/* plla divisor by 2 */
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if (mckr & (1 << 12))
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gd->arch.plla_rate_hz >>= 1;
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gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
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freq = gd->arch.mck_rate_hz;
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/* prescale */
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freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
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switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
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case AT91_PMC_MCKR_MDIV_2:
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gd->arch.mck_rate_hz = freq / 2;
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break;
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case AT91_PMC_MCKR_MDIV_3:
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gd->arch.mck_rate_hz = freq / 3;
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break;
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case AT91_PMC_MCKR_MDIV_4:
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gd->arch.mck_rate_hz = freq / 4;
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break;
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default:
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break;
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}
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gd->arch.cpu_clk_rate_hz = freq;
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return 0;
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}
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void at91_plla_init(u32 pllar)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(pllar, &pmc->pllar);
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while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
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;
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}
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void at91_mck_init(u32 mckr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = readl(&pmc->mckr);
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tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
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AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_2);
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#ifdef CPU_HAS_H32MXDIV
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tmp &= ~AT91_PMC_MCKR_H32MXDIV;
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#endif
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tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
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AT91_PMC_MCKR_PRES_MASK |
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AT91_PMC_MCKR_MDIV_MASK |
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AT91_PMC_MCKR_PLLADIV_2);
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#ifdef CPU_HAS_H32MXDIV
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tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
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#endif
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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}
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/*
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* For the Master Clock Controller Register(MCKR), while switching
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* to a lower clock source, we must switch the clock source first
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* instead of last. Otherwise, we could end up with too high frequency
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* on the internal bus and peripherals.
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*/
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void at91_mck_init_down(u32 mckr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = readl(&pmc->mckr);
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tmp &= (~AT91_PMC_MCKR_CSS_MASK);
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tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK);
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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#ifdef CPU_HAS_H32MXDIV
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tmp = readl(&pmc->mckr);
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tmp &= (~AT91_PMC_MCKR_H32MXDIV);
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tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV);
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writel(tmp, &pmc->mckr);
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#endif
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tmp = readl(&pmc->mckr);
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tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK);
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tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK);
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writel(tmp, &pmc->mckr);
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tmp = readl(&pmc->mckr);
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tmp &= (~AT91_PMC_MCKR_MDIV_MASK);
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tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK);
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writel(tmp, &pmc->mckr);
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tmp = readl(&pmc->mckr);
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tmp &= (~AT91_PMC_MCKR_PRES_MASK);
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tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK);
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writel(tmp, &pmc->mckr);
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}
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int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 regval, status;
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u32 timeout = 1000;
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if (id > AT91_PMC_PCR_PID_MASK)
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return -EINVAL;
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if (div > 0xff)
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return -EINVAL;
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if (clk_source == GCK_CSS_UPLL_CLK) {
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if (at91_upll_clk_enable())
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return -ENODEV;
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}
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writel(id, &pmc->pcr);
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regval = readl(&pmc->pcr);
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regval &= ~AT91_PMC_PCR_GCKCSS;
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regval &= ~AT91_PMC_PCR_GCKDIV;
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switch (clk_source) {
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case GCK_CSS_SLOW_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK;
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break;
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case GCK_CSS_MAIN_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK;
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break;
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case GCK_CSS_PLLA_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK;
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break;
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case GCK_CSS_UPLL_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK;
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break;
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case GCK_CSS_MCK_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK;
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break;
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case GCK_CSS_AUDIO_CLK:
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regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK;
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break;
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default:
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printf("Error GCK clock source selection!\n");
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return -EINVAL;
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}
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regval |= AT91_PMC_PCR_CMD_WRITE |
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AT91_PMC_PCR_GCKDIV_(div) |
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AT91_PMC_PCR_GCKEN;
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writel(regval, &pmc->pcr);
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do {
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udelay(1);
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status = readl(&pmc->sr);
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} while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY)));
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if (!timeout)
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printf("Timeout waiting for GCK ready!\n");
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return 0;
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}
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u32 at91_get_periph_generated_clk(u32 id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 regval, clk_source, div;
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u32 freq;
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if (id > AT91_PMC_PCR_PID_MASK)
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return 0;
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writel(id, &pmc->pcr);
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regval = readl(&pmc->pcr);
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clk_source = regval & AT91_PMC_PCR_GCKCSS;
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switch (clk_source) {
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case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
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freq = CONFIG_SYS_AT91_SLOW_CLOCK;
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break;
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case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
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freq = gd->arch.main_clk_rate_hz;
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break;
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case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
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freq = gd->arch.plla_rate_hz;
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break;
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case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
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freq = AT91_UTMI_PLL_CLK_FREQ;
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break;
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case AT91_PMC_PCR_GCKCSS_MCK_CLK:
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freq = gd->arch.mck_rate_hz;
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break;
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default:
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printf("Improper GCK clock source selection!\n");
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freq = 0;
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break;
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}
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div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET);
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div += 1;
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return freq / div;
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}
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