174 lines
3.8 KiB
Plaintext
174 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Collabora Ltd.
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*
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* Based on dts[i] from Phytec barebox port:
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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/ {
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model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
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compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
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memory {
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reg = <0x80000000 0x20000000>;
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};
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chosen {
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stdout-path = &uart1;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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fsl,no-blockmark-swap;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "uboot";
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reg = <0x0 0x400000>;
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};
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partition@400000 {
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label = "uboot-env";
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reg = <0x400000 0x100000>;
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};
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partition@500000 {
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label = "root";
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reg = <0x500000 0x0>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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status = "okay";
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eeprom@52 {
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compatible = "cat,24c32";
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reg = <0x52>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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bus-width = <0x4>;
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pinctrl-0 = <&pinctrl_usdhc1>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
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>;
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};
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pinctrl_i2c1: i2cgrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp_gpio {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
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>;
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};
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};
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