370 lines
11 KiB
C
370 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*/
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#ifndef _MCD_API_H
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#define _MCD_API_H
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/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
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#undef MCD_INCLUDE_EU
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/* Number of DMA channels */
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#define NCHANNELS 16
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/* Total number of variants */
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#ifdef MCD_INCLUDE_EU
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#define NUMOFVARIANTS 6
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#else
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#define NUMOFVARIANTS 4
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#endif
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/* Define sizes of the various tables */
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#define TASK_TABLE_SIZE (NCHANNELS*32)
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#define VAR_TAB_SIZE (128)
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#define CONTEXT_SAVE_SIZE (128)
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#define FUNCDESC_TAB_SIZE (256)
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#ifdef MCD_INCLUDE_EU
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#define FUNCDESC_TAB_NUM 16
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#else
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#define FUNCDESC_TAB_NUM 1
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#endif
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#ifndef DEFINESONLY
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/* Portability typedefs */
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#if 1
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#include "common.h"
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#else
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#ifndef s32
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typedef int s32;
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#endif
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#ifndef u32
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typedef unsigned int u32;
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#endif
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#ifndef s16
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typedef short s16;
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#endif
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#ifndef u16
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typedef unsigned short u16;
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#endif
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#ifndef s8
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typedef char s8;
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#endif
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#ifndef u8
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typedef unsigned char u8;
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#endif
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#endif
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/*
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* These structures represent the internal registers of the
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* multi-channel DMA
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*/
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struct dmaRegs_s {
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u32 taskbar; /* task table base address */
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u32 currPtr;
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u32 endPtr;
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u32 varTablePtr;
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u16 dma_rsvd0;
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u16 ptdControl; /* ptd control */
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u32 intPending; /* interrupt pending */
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u32 intMask; /* interrupt mask */
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u16 taskControl[16]; /* task control */
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u8 priority[32]; /* priority */
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u32 initiatorMux; /* initiator mux control */
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u32 taskSize0; /* task size control 0. */
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u32 taskSize1; /* task size control 1. */
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u32 dma_rsvd1; /* reserved */
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u32 dma_rsvd2; /* reserved */
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u32 debugComp1; /* debug comparator 1 */
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u32 debugComp2; /* debug comparator 2 */
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u32 debugControl; /* debug control */
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u32 debugStatus; /* debug status */
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u32 ptdDebug; /* priority task decode debug */
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u32 dma_rsvd3[31]; /* reserved */
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};
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typedef volatile struct dmaRegs_s dmaRegs;
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#endif
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/* PTD contrl reg bits */
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#define PTD_CTL_TSK_PRI 0x8000
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#define PTD_CTL_COMM_PREFETCH 0x0001
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/* Task Control reg bits and field masks */
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#define TASK_CTL_EN 0x8000
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#define TASK_CTL_VALID 0x4000
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#define TASK_CTL_ALWAYS 0x2000
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#define TASK_CTL_INIT_MASK 0x1f00
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#define TASK_CTL_ASTRT 0x0080
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#define TASK_CTL_HIPRITSKEN 0x0040
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#define TASK_CTL_HLDINITNUM 0x0020
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#define TASK_CTL_ASTSKNUM_MASK 0x000f
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/* Priority reg bits and field masks */
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#define PRIORITY_HLD 0x80
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#define PRIORITY_PRI_MASK 0x07
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/* Debug Control reg bits and field masks */
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#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
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#define DBG_CTL_AUTO_ARM 0x00008000
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#define DBG_CTL_BREAK 0x00004000
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#define DBG_CTL_COMP1_TYP_MASK 0x00003800
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#define DBG_CTL_COMP2_TYP_MASK 0x00000070
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#define DBG_CTL_EXT_BREAK 0x00000004
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#define DBG_CTL_INT_BREAK 0x00000002
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/*
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* PTD Debug reg selector addresses
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* This reg must be written with a value to show the contents of
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* one of the desired internal register.
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*/
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#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
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#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
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have initiators asserted */
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/* General return values */
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#define MCD_OK 0
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#define MCD_ERROR -1
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#define MCD_TABLE_UNALIGNED -2
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#define MCD_CHANNEL_INVALID -3
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/* MCD_initDma input flags */
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#define MCD_RELOC_TASKS 0x00000001
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#define MCD_NO_RELOC_TASKS 0x00000000
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#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
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/*
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* MCD_dmaStatus Status Values for each channel:
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* MCD_NO_DMA - No DMA has been requested since reset
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* MCD_IDLE - DMA active, but the initiator is currently inactive
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* MCD_RUNNING - DMA active, and the initiator is currently active
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* MCD_PAUSED - DMA active but it is currently paused
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* MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
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* MCD_DONE - the most recent DMA has completed
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*/
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#define MCD_NO_DMA 1
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#define MCD_IDLE 2
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#define MCD_RUNNING 3
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#define MCD_PAUSED 4
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#define MCD_HALTED 5
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#define MCD_DONE 6
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/* MCD_startDma parameter defines */
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/* Constants for the funcDesc parameter */
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/*
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* MCD_NO_BYTE_SWAP - to disable byte swapping
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* MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
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* MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
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* value being DMAed
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* MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
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* each 32-bit data value DMAed
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* MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
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* MCD_BIT_REV - reverse the bits of each byte DMAed
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* MCD_CRC16 - to perform CRC-16 on DMAed data
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* MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
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* MCD_CRC32 - to perform CRC-32 on DMAed data
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* MCD_CSUMINET - to perform internet checksums on DMAed data
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* MCD_NO_CSUM - to perform no checksumming
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*/
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#define MCD_NO_BYTE_SWAP 0x00045670
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#define MCD_BYTE_REVERSE 0x00076540
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#define MCD_U16_REVERSE 0x00067450
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#define MCD_U16_BYTE_REVERSE 0x00054760
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#define MCD_NO_BIT_REV 0x00000000
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#define MCD_BIT_REV 0x00088880
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/* CRCing: */
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#define MCD_CRC16 0xc0100000
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#define MCD_CRCCCITT 0xc0200000
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#define MCD_CRC32 0xc0300000
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#define MCD_CSUMINET 0xc0400000
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#define MCD_NO_CSUM 0xa0000000
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#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
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MCD_NO_CSUM)
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#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
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/* Constants for the flags parameter */
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#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
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#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
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#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
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#define MCD_TT_FLAGS_MASK 0x000000ff
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#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
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#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
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#define MCD_CHAIN_DMA /* TBD */
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#define MCD_EU_DMA /* TBD */
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#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
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#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
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/* these flags are valid for MCD_startDma and the chained buffer descriptors */
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/*
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* MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
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* MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
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* MCD_INTERRUPT - to generate an interrupt after completion of the DMA
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* MCD_END_FRAME - tell the DMA to end the frame when transferring
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* last byte of data in buffer
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* MCD_CRC_RESTART - to empty out the accumulated checksum prior to
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* performing the DMA
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*/
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#define MCD_BUF_READY 0x80000000
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#define MCD_WRAP 0x20000000
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#define MCD_INTERRUPT 0x10000000
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#define MCD_END_FRAME 0x08000000
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#define MCD_CRC_RESTART 0x40000000
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/* Defines for the FEC buffer descriptor control/status word*/
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#define MCD_FEC_BUF_READY 0x8000
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#define MCD_FEC_WRAP 0x2000
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#define MCD_FEC_INTERRUPT 0x1000
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#define MCD_FEC_END_FRAME 0x0800
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/* Defines for general intuitiveness */
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#define MCD_TRUE 1
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#define MCD_FALSE 0
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/* Three different cases for destination and source. */
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#define MINUS1 -1
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#define ZERO 0
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#define PLUS1 1
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#ifndef DEFINESONLY
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/* Task Table Entry struct*/
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typedef struct {
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u32 TDTstart; /* task descriptor table start */
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u32 TDTend; /* task descriptor table end */
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u32 varTab; /* variable table start */
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u32 FDTandFlags; /* function descriptor table start & flags */
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volatile u32 descAddrAndStatus;
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volatile u32 modifiedVarTab;
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u32 contextSaveSpace; /* context save space start */
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u32 literalBases;
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} TaskTableEntry;
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/* Chained buffer descriptor:
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* flags - flags describing the DMA
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* csumResult - checksum performed since last checksum reset
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* srcAddr - the address to move data from
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* destAddr - the address to move data to
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* lastDestAddr - the last address written to
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* dmaSize - the no of bytes to xfer independent of the xfer sz
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* next - next buffer descriptor in chain
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* info - private info about this descriptor; DMA does not affect it
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*/
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typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
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struct MCD_bufDesc_struct {
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u32 flags;
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u32 csumResult;
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s8 *srcAddr;
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s8 *destAddr;
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s8 *lastDestAddr;
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u32 dmaSize;
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MCD_bufDesc *next;
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u32 info;
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};
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/* Progress Query struct:
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* lastSrcAddr - the most-recent or last, post-increment source address
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* lastDestAddr - the most-recent or last, post-increment destination address
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* dmaSize - the amount of data transferred for the current buffer
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* currBufDesc - pointer to the current buffer descriptor being DMAed
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*/
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typedef volatile struct MCD_XferProg_struct {
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s8 *lastSrcAddr;
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s8 *lastDestAddr;
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u32 dmaSize;
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MCD_bufDesc *currBufDesc;
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} MCD_XferProg;
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/* FEC buffer descriptor */
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typedef volatile struct MCD_bufDescFec_struct {
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u16 statCtrl;
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u16 length;
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u32 dataPointer;
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} MCD_bufDescFec;
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/*************************************************************************/
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/* API function Prototypes - see MCD_dmaApi.c for further notes */
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/* MCD_startDma starts a particular kind of DMA:
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* srcAddr - the channel on which to run the DMA
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* srcIncr - the address to move data from, or buffer-descriptor address
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* destAddr - the amount to increment the source address per transfer
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* destIncr - the address to move data to
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* dmaSize - the amount to increment the destination address per transfer
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* xferSize - the number bytes in of each data movement (1, 2, or 4)
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* initiator - what device initiates the DMA
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* priority - priority of the DMA
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* flags - flags describing the DMA
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* funcDesc - description of byte swapping, bit swapping, and CRC actions
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*/
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int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
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s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
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int priority, u32 flags, u32 funcDesc);
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/*
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* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
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* registers, relocating and creating the appropriate task structures, and
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* setting up some global settings
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*/
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int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
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/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
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int MCD_dmaStatus(int channel);
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/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
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int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
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/*
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* MCD_killDma() halts the DMA on the requested channel, without any
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* intention of resuming the DMA.
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*/
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int MCD_killDma(int channel);
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/*
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* MCD_continDma() continues a DMA which as stopped due to encountering an
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* unready buffer descriptor.
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*/
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int MCD_continDma(int channel);
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/*
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* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
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* running on that channel).
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*/
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int MCD_pauseDma(int channel);
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/*
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* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
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* running on that channel).
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*/
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int MCD_resumeDma(int channel);
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/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
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int MCD_csumQuery(int channel, u32 * csum);
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/*
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* MCD_getCodeSize provides the packed size required by the microcoded task
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* and structures.
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*/
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int MCD_getCodeSize(void);
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/*
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* MCD_getVersion provides a pointer to a version string and returns a
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* version number.
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*/
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int MCD_getVersion(char **longVersion);
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/* macro for setting a location in the variable table */
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#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
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/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
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so I'm avoiding surrounding it with "do {} while(0)" */
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#endif /* DEFINESONLY */
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#endif /* _MCD_API_H */
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