117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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#define RK3368_PULL_GRF_OFFSET 0x100
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#define RK3368_PULL_PMU_OFFSET 0x10
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static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK3368_PULL_PMU_OFFSET;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3368_PULL_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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}
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#define RK3368_DRV_PMU_OFFSET 0x20
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#define RK3368_DRV_GRF_OFFSET 0x200
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static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK3368_DRV_PMU_OFFSET;
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3368_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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}
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}
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static struct rockchip_pin_bank rk3368_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU
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),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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PIN_BANK(3, 32, "gpio3"),
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};
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static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
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.pin_banks = rk3368_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
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.label = "RK3368-GPIO",
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.type = RK3368,
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.grf_mux_offset = 0x0,
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.pmu_mux_offset = 0x0,
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.pull_calc_reg = rk3368_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
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};
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static const struct udevice_id rk3368_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3368-pinctrl",
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.data = (ulong)&rk3368_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3368) = {
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.name = "rockchip_rk3368_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3368_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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