377 lines
14 KiB
C
377 lines
14 KiB
C
/* -*- linux-c -*- *
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*
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* ALSA driver for the digigram lx6464es interface
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* adapted upstream headers
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*
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* Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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*
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*/
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#ifndef LX_DEFS_H
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#define LX_DEFS_H
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/* code adapted from ethersound.h */
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#define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */
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#define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M /
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* [ 44k - ( 44.1k + 48k ) / 2 ]
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* * 8 */
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#define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]
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* * 8 */
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#define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M /
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* [ 48k + ( 44.1k + 48k ) / 2 ]
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* * 8 */
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/* code adapted from LXES_registers.h */
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#define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the
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* ConfES register. */
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#define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the
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* ConfES register. */
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#define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the
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* ConfES register. */
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#define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
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* sample rate = frequency rate. */
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#define CONFES_READ_PART_MASK 0x00070000
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#define CONFES_WRITE_PART_MASK 0x00F80000
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/* code adapted from if_drv_mb.h */
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#define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if
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* not yet pending */
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#define MASK_SYS_STATUS_URUN (1L << 30)
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#define MASK_SYS_STATUS_ORUN (1L << 29)
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#define MASK_SYS_STATUS_EOBO (1L << 28)
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#define MASK_SYS_STATUS_EOBI (1L << 27)
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#define MASK_SYS_STATUS_FREQ (1L << 26)
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#define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the
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* XES */
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#define MASK_SYS_STATUS_TIMER (1L << 24)
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#define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \
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MASK_SYS_STATUS_URUN | \
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MASK_SYS_STATUS_ORUN | \
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MASK_SYS_STATUS_EOBO | \
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MASK_SYS_STATUS_EOBI | \
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MASK_SYS_STATUS_FREQ | \
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MASK_SYS_STATUS_ESA)
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#define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \
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MASK_SYS_STATUS_TIMER)
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#define MASK_SYS_TIMER_COUNT 0x0000FFFF
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#define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains
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* internal: reserved fo end
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* of plx dma */
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#define MASK_SYS_STATUS_XES (1L << 21) /* event that remains
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* internal: pending XES
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* IRQ */
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#define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command
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* management: notify driver
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* instead of polling */
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#define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
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#define MICROBLAZE_IBL_MIN 32
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#define MICROBLAZE_IBL_DEFAULT 128
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#define MICROBLAZE_IBL_MAX 512
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/* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
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/* command opcodes, see reference for details */
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/*
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the capture bit position in the object_id field in driver commands
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depends upon the number of managed channels. For now, 64 IN + 64 OUT are
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supported. HOwever, the communication protocol forsees 1024 channels, hence
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bit 10 indicates a capture (input) object).
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*/
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#define ID_IS_CAPTURE (1L << 10)
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#define ID_OFFSET 13 /* object ID is at the 13th bit in the
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* 1st command word.*/
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#define ID_CH_MASK 0x3F
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#define OPCODE_OFFSET 24 /* offset of the command opcode in the first
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* command word.*/
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enum cmd_mb_opcodes {
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CMD_00_INFO_DEBUG = 0x00,
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CMD_01_GET_SYS_CFG = 0x01,
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CMD_02_SET_GRANULARITY = 0x02,
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CMD_03_SET_TIMER_IRQ = 0x03,
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CMD_04_GET_EVENT = 0x04,
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CMD_05_GET_PIPES = 0x05,
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CMD_06_ALLOCATE_PIPE = 0x06,
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CMD_07_RELEASE_PIPE = 0x07,
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CMD_08_ASK_BUFFERS = 0x08,
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CMD_09_STOP_PIPE = 0x09,
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CMD_0A_GET_PIPE_SPL_COUNT = 0x0a,
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CMD_0B_TOGGLE_PIPE_STATE = 0x0b,
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CMD_0C_DEF_STREAM = 0x0c,
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CMD_0D_SET_MUTE = 0x0d,
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CMD_0E_GET_STREAM_SPL_COUNT = 0x0e,
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CMD_0F_UPDATE_BUFFER = 0x0f,
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CMD_10_GET_BUFFER = 0x10,
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CMD_11_CANCEL_BUFFER = 0x11,
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CMD_12_GET_PEAK = 0x12,
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CMD_13_SET_STREAM_STATE = 0x13,
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CMD_14_INVALID = 0x14,
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};
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/* pipe states */
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enum pipe_state_t {
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PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ
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* (free or stopped, or paused). */
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PSTATE_RUN = 1, /* sustained play/record state. */
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PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
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* not DMA, record pipe do a last DMA. */
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PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
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* not yet increase their sample count, record
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* pipes do not DMA. */
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PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet
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* receive an "alloc" command. */
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};
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/* stream states */
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enum stream_state_t {
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SSTATE_STOP = 0x00, /* setting to stop resets the stream spl
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* count.*/
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SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */
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SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */
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};
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/* buffer flags */
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enum buffer_flags {
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BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/
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BF_CURRENT = 0x40, /* set if this is the current buffer (there is
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* always a current buffer).*/
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BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event
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* when finished.*/
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BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
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* by the end of this buffer.*/
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BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/
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BF_xx = 0x04, /* future extension.*/
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BF_EOB = 0x02, /* set if finished, but not yet free.*/
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BF_PAUSE = 0x01, /* pause stream at buffer end.*/
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BF_ZERO = 0x00, /* no flags (init).*/
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};
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/*
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* Stream Flags definitions
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*/
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enum stream_flags {
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SF_ZERO = 0x00000000, /* no flags (stream invalid). */
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SF_VALID = 0x10000000, /* the stream has a valid DMA_conf
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* info (setstreamformat). */
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SF_XRUN = 0x20000000, /* the stream is un x-run state. */
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SF_START = 0x40000000, /* the DMA is running.*/
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SF_ASIO = 0x80000000, /* ASIO.*/
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};
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#define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */
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#define PSTATE_OFFSET 28 /* 4 MSBits are status bits */
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#define MASK_STREAM_HAS_MAPPING (1L << 12)
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#define MASK_STREAM_IS_ASIO (1L << 9)
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#define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th
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* bit in the command word. */
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#define STREAM_FMT_16b 0x02
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#define STREAM_FMT_intel 0x01
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#define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response
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* word */
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#define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the
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* response word. */
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#define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of
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* datasize in the buffer_t structure. */
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#define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,
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* may be 0xFF for "current". */
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/* code adapted from PcxErr_e.h */
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/* Bits masks */
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#define ERROR_MASK 0x8000
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#define SOURCE_MASK 0x7800
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#define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */
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#define E_SOURCE_DRV 0x2000 /* 4 >> 1 */
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#define E_SOURCE_API 0x1000 /* 2 >> 1 */
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/* Error tools */
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#define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */
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/* Error pcxaudio */
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#define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */
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/* Error virtual pcx */
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#define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */
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/* Error dispatcher */
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#define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */
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/* Error from CobraNet firmware */
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#define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */
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#define E_SOURCE_USER 0x7800
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#define CLASS_MASK 0x0700
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#define CODE_MASK 0x00FF
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/* Bits values */
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/* Values for the error/warning bit */
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#define ERROR_VALUE 0x8000
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#define WARNING_VALUE 0x0000
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/* Class values */
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#define E_CLASS_GENERAL 0x0000
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#define E_CLASS_INVALID_CMD 0x0100
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#define E_CLASS_INVALID_STD_OBJECT 0x0200
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#define E_CLASS_RSRC_IMPOSSIBLE 0x0300
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#define E_CLASS_WRONG_CONTEXT 0x0400
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#define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500
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#define E_CLASS_REAL_TIME_ERROR 0x0600
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#define E_CLASS_DIRECTSHOW 0x0700
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#define E_CLASS_FREE 0x0700
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/* Complete DRV error code for the general class */
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#define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)
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#define ED_CONCURRENCY (ED_GN | 0x01)
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#define ED_DSP_CRASHED (ED_GN | 0x02)
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#define ED_UNKNOWN_BOARD (ED_GN | 0x03)
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#define ED_NOT_INSTALLED (ED_GN | 0x04)
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#define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05)
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#define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06)
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#define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07)
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#define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08)
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#define ED_CANCELLED (ED_GN | 0x09)
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#define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10)
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#define ED_INVALID_ADDRESS (ED_GN | 0x11)
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#define ED_DSP_CORRUPTED (ED_GN | 0x12)
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#define ED_PENDING_OPERATION (ED_GN | 0x13)
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#define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14)
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#define ED_NET_REGISTER_ERROR (ED_GN | 0x15)
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#define ED_NET_THREAD_ERROR (ED_GN | 0x16)
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#define ED_NET_OPEN_ERROR (ED_GN | 0x17)
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#define ED_NET_CLOSE_ERROR (ED_GN | 0x18)
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#define ED_NET_NO_MORE_PACKET (ED_GN | 0x19)
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#define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A)
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#define ED_NET_SEND_ERROR (ED_GN | 0x1B)
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#define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C)
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#define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D)
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#define ED_NET_WAIT_ERROR (ED_GN | 0x1E)
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#define ED_NET_EEPROM_ERROR (ED_GN | 0x1F)
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#define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20)
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#define ED_INVALID_RS232_INIT (ED_GN | 0x21)
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#define ED_FILE_ERROR (ED_GN | 0x22)
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#define ED_INVALID_GPIO_CMD (ED_GN | 0x23)
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#define ED_RS232_ALREADY_OPENED (ED_GN | 0x24)
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#define ED_RS232_NOT_OPENED (ED_GN | 0x25)
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#define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26)
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#define ED_GPIO_NOT_OPENED (ED_GN | 0x27)
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#define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
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#define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
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#define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage
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* pour RCX
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* (old 0x28)
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* */
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#define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */
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#define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */
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#define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */
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#define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */
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#define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */
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#define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */
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#define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */
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#define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour
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* PCX (old 0x14) */
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#define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */
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#define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */
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#define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */
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#define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */
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#define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37)
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#define ED_NO_CURRENT_CLOCK (ED_GN | 0x38)
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/* Complete DRV error code for real time class */
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#define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)
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#define ED_DSP_TIMED_OUT (ED_RT | 0x01)
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#define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02)
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#define ED_STREAM_OVERRUN (ED_RT | 0x03)
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#define ED_DSP_BUSY (ED_RT | 0x04)
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#define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05)
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#define ED_BOARD_TIME_OUT (ED_RT | 0x06)
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#define ED_XILINX_ERROR (ED_RT | 0x07)
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#define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08)
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/* Complete BOARD error code for the invaid standard object class */
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#define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \
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E_CLASS_INVALID_STD_OBJECT)
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#define EB_INVALID_EFFECT (EB_ISO | 0x00)
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#define EB_INVALID_PIPE (EB_ISO | 0x40)
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#define EB_INVALID_STREAM (EB_ISO | 0x80)
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#define EB_INVALID_AUDIO (EB_ISO | 0xC0)
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/* Complete BOARD error code for impossible resource allocation class */
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#define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)
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#define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)
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#define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02)
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#define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \
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EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE
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#define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \
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EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE
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#define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03)
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#define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04)
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#define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05)
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#define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08)
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#define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09)
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#define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A)
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#define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B)
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#define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D)
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#define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E)
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#define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F)
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#define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40)
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#define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80)
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#define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0)
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/* Complete BOARD error code for wrong call context class */
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#define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)
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#define EB_CMD_REFUSED (EB_WCC | 0x00)
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#define EB_START_STREAM_REFUSED (EB_WCC | 0xFC)
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#define EB_SPC_REFUSED (EB_WCC | 0xFD)
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#define EB_CSN_REFUSED (EB_WCC | 0xFE)
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#define EB_CSE_REFUSED (EB_WCC | 0xFF)
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#endif /* LX_DEFS_H */
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