159 lines
4.2 KiB
C
Executable File
159 lines
4.2 KiB
C
Executable File
/*
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* Faraday FTIIC010 I2C Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FTIIC010_H
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#define __FTIIC010_H
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#define I2C_FTI2C010_COUNT 6
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#define FTIIC010_OFFSET_CR 0x00
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#define FTIIC010_OFFSET_SR 0x04
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#define FTIIC010_OFFSET_CDR 0x08
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#define FTIIC010_OFFSET_DR 0x0c
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#define FTIIC010_OFFSET_SAR 0x10
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#define FTIIC010_OFFSET_TGSR 0x14
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#define FTIIC010_OFFSET_BMR 0x18
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#define FTIIC010_OFFSET_SMCR 0x1c
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#define FTIIC010_OFFSET_MAXTR 0x20
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#define FTIIC010_OFFSET_MINTR 0x24
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#define FTIIC010_OFFSET_METR 0x28
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#define FTIIC010_OFFSET_SETR 0x2c
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#define FTIIC010_OFFSET_REV 0x30
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#define FTIIC010_OFFSET_FEAT 0x34
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/*
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* Control Register
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*/
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#define FTIIC010_CR_I2C_RST (1 << 0)
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#define FTIIC010_CR_I2C_EN (1 << 1)
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#define FTIIC010_CR_SCL_EN (1 << 2)
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#define FTIIC010_CR_GC_EN (1 << 3)
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#define FTIIC010_CR_START (1 << 4)
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#define FTIIC010_CR_STOP (1 << 5)
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#define FTIIC010_CR_NAK (1 << 6)
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#define FTIIC010_CR_TB_EN (1 << 7)
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#define FTIIC010_CR_DTI_EN (1 << 8)
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#define FTIIC010_CR_DRI_EN (1 << 9)
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#define FTIIC010_CR_BERRI_EN (1 << 10)
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#define FTIIC010_CR_STOPI_EN (1 << 11)
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#define FTIIC010_CR_SAMI_EN (1 << 12)
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#define FTIIC010_CR_ALI_EN (1 << 13) /* arbitration lost */
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#define FTIIC010_CR_STARTI_EN (1 << 14)
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#define FTIIC010_CR_SCL_LOW (1 << 15)
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#define FTIIC010_CR_SDA_LOW (1 << 16)
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#define FTIIC010_CR_TESTMODE (1 << 17)
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#define FTIIC010_CR_ARB_OFF (1 << 18)
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/*
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* Status Register
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*/
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#define FTIIC010_SR_RW (1 << 0)
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#define FTIIC010_SR_ACK (1 << 1)
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#define FTIIC010_SR_I2CBUSY (1 << 2)
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#define FTIIC010_SR_BUSBUSY (1 << 3)
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#define FTIIC010_SR_DT (1 << 4)
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#define FTIIC010_SR_DR (1 << 5)
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#define FTIIC010_SR_BERR (1 << 6)
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#define FTIIC010_SR_STOP (1 << 7)
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#define FTIIC010_SR_SAM (1 << 8)
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#define FTIIC010_SR_GC (1 << 9)
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#define FTIIC010_SR_AL (1 << 10)
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#define FTIIC010_SR_START (1 << 11)
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#define FTIIC010_SR_SEXT (1 << 12)
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#define FTIIC010_SR_MEXT (1 << 13)
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#define FTIIC010_SR_MINTIMEOUT (1 << 14)
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#define FTIIC010_SR_MAXTIMEOUT (1 << 15)
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#define FTIIC010_SR_ALERT (1 << 16)
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#define FTIIC010_SR_SUSPEND (1 << 17)
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#define FTIIC010_SR_RESUME (1 << 18)
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#define FTIIC010_SR_ARA (1 << 19)
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#define FTIIC010_SR_DDA (1 << 20)
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#define FTIIC010_SR_SAL (1 << 21)
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/*
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* Clock Division Register
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*/
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#define FTIIC010_CDR_MASK 0x3ffff
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/*
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* Data Register
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*/
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#define FTIIC010_DR_MASK 0xff
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/*
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* Slave Address Register
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*/
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#define FTIIC010_SAR_MASK 0x3ff
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#define FTIIC010_SAR_EN10 (1 << 31)
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/*
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* Set/Hold Time Glitch Suppression Setting Register
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*/
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#define FTIIC010_TGSR_TSR(x) ((x) & 0x3ff) /* should not be zero */
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#define FTIIC010_TGSR_GSR(x) (((x) & 0x7) << 10)
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/*
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* Bus Monitor Register
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*/
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#define FTIIC010_BMR_SDA_IN (1 << 0)
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#define FTIIC010_BMR_SCL_IN (1 << 1)
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/*
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* SM Control Register
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*/
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#define FTIIC010_SMCR_SEXT_EN (1 << 0)
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#define FTIIC010_SMCR_MEXT_EN (1 << 1)
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#define FTIIC010_SMCR_TOUT_EN (1 << 2)
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#define FTIIC010_SMCR_ALERT_EN (1 << 3)
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#define FTIIC010_SMCR_SUS_EN (1 << 4)
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#define FTIIC010_SMCR_RSM_EN (1 << 5)
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#define FTIIC010_SMCR_SAL_EN (1 << 8)
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#define FTIIC010_SMCR_ALERT_LOW (1 << 9)
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#define FTIIC010_SMCR_SUS_LOW (1 << 10)
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#define FTIIC010_SMCR_SUSOUT_EN (1 << 11)
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/*
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* SM Maximum Timeout Register
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*/
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#define FTIIC010_MAXTR_MASK 0x3fffff
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/*
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* SM Minimum Timeout Register
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*/
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#define FTIIC010_MINTR_MASK 0x3fffff
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/*
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* SM Master Extend Time Register
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*/
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#define FTIIC010_METR_MASK 0xfffff
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/*
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* SM Slave Extend Time Register
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*/
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#define FTIIC010_SETR_MASK 0x1fffff
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/*
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* Feature Register
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*/
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#define FTIIC010_FEAT_SMBUS (1 << 0)
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#endif /* __FTIIC010_H */
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