50 lines
1.7 KiB
Plaintext
50 lines
1.7 KiB
Plaintext
* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
|
|
|
|
Required properties:
|
|
- compatible :
|
|
- "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC
|
|
- "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC
|
|
- "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
|
|
- reg : Should contain I2C/HS-I2C registers location and length
|
|
- interrupts : Should contain I2C/HS-I2C interrupt
|
|
- clocks : Should contain the I2C/HS-I2C clock specifier
|
|
|
|
Optional properties:
|
|
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
|
|
The absence of the property indicates the default frequency 100 kHz.
|
|
- dmas: A list of two dma specifiers, one for each entry in dma-names.
|
|
- dma-names: should contain "tx" and "rx".
|
|
- scl-gpios: specify the gpio related to SCL pin
|
|
- sda-gpios: specify the gpio related to SDA pin
|
|
- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
|
|
bus recovery, call it "gpio" state
|
|
|
|
Examples:
|
|
|
|
i2c@83fc4000 { /* I2C2 on i.MX51 */
|
|
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
|
reg = <0x83fc4000 0x4000>;
|
|
interrupts = <63>;
|
|
};
|
|
|
|
i2c@70038000 { /* HS-I2C on i.MX51 */
|
|
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
|
|
reg = <0x70038000 0x4000>;
|
|
interrupts = <64>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
i2c0: i2c@40066000 { /* i2c0 on vf610 */
|
|
compatible = "fsl,vf610-i2c";
|
|
reg = <0x40066000 0x1000>;
|
|
interrupts =<0 71 0x04>;
|
|
dmas = <&edma0 0 50>,
|
|
<&edma0 0 51>;
|
|
dma-names = "rx","tx";
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
|
scl-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
|
|
sda-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
|
|
};
|