281 lines
6.1 KiB
C
281 lines
6.1 KiB
C
/*
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* VFIO PCI Intel Graphics support
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*
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* Copyright (C) 2016 Red Hat, Inc. All rights reserved.
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* Author: Alex Williamson <alex.williamson@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Register a device specific region through which to provide read-only
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* access to the Intel IGD opregion. The register defining the opregion
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* address is also virtualized to prevent user modification.
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*/
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/uaccess.h>
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#include <linux/vfio.h>
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#include "vfio_pci_private.h"
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#define OPREGION_SIGNATURE "IntelGraphicsMem"
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#define OPREGION_SIZE (8 * 1024)
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#define OPREGION_PCI_ADDR 0xfc
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static size_t vfio_pci_igd_rw(struct vfio_pci_device *vdev, char __user *buf,
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size_t count, loff_t *ppos, bool iswrite)
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{
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unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
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void *base = vdev->region[i].data;
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loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
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if (pos >= vdev->region[i].size || iswrite)
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return -EINVAL;
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count = min(count, (size_t)(vdev->region[i].size - pos));
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if (copy_to_user(buf, base + pos, count))
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return -EFAULT;
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*ppos += count;
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return count;
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}
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static void vfio_pci_igd_release(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region)
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{
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memunmap(region->data);
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}
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static const struct vfio_pci_regops vfio_pci_igd_regops = {
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.rw = vfio_pci_igd_rw,
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.release = vfio_pci_igd_release,
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};
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static int vfio_pci_igd_opregion_init(struct vfio_pci_device *vdev)
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{
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__le32 *dwordp = (__le32 *)(vdev->vconfig + OPREGION_PCI_ADDR);
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u32 addr, size;
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void *base;
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int ret;
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ret = pci_read_config_dword(vdev->pdev, OPREGION_PCI_ADDR, &addr);
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if (ret)
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return ret;
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if (!addr || !(~addr))
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return -ENODEV;
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base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
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if (!base)
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return -ENOMEM;
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if (memcmp(base, OPREGION_SIGNATURE, 16)) {
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memunmap(base);
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return -EINVAL;
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}
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size = le32_to_cpu(*(__le32 *)(base + 16));
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if (!size) {
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memunmap(base);
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return -EINVAL;
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}
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size *= 1024; /* In KB */
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if (size != OPREGION_SIZE) {
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memunmap(base);
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base = memremap(addr, size, MEMREMAP_WB);
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if (!base)
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return -ENOMEM;
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}
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ret = vfio_pci_register_dev_region(vdev,
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PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
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VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
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&vfio_pci_igd_regops, size, VFIO_REGION_INFO_FLAG_READ, base);
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if (ret) {
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memunmap(base);
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return ret;
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}
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/* Fill vconfig with the hw value and virtualize register */
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*dwordp = cpu_to_le32(addr);
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memset(vdev->pci_config_map + OPREGION_PCI_ADDR,
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PCI_CAP_ID_INVALID_VIRT, 4);
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return ret;
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}
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static size_t vfio_pci_igd_cfg_rw(struct vfio_pci_device *vdev,
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char __user *buf, size_t count, loff_t *ppos,
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bool iswrite)
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{
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unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
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struct pci_dev *pdev = vdev->region[i].data;
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loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
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size_t size;
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int ret;
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if (pos >= vdev->region[i].size || iswrite)
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return -EINVAL;
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size = count = min(count, (size_t)(vdev->region[i].size - pos));
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if ((pos & 1) && size) {
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u8 val;
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ret = pci_user_read_config_byte(pdev, pos, &val);
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if (ret)
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return pcibios_err_to_errno(ret);
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if (copy_to_user(buf + count - size, &val, 1))
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return -EFAULT;
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pos++;
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size--;
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}
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if ((pos & 3) && size > 2) {
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u16 val;
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ret = pci_user_read_config_word(pdev, pos, &val);
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if (ret)
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return pcibios_err_to_errno(ret);
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val = cpu_to_le16(val);
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if (copy_to_user(buf + count - size, &val, 2))
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return -EFAULT;
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pos += 2;
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size -= 2;
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}
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while (size > 3) {
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u32 val;
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ret = pci_user_read_config_dword(pdev, pos, &val);
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if (ret)
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return pcibios_err_to_errno(ret);
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val = cpu_to_le32(val);
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if (copy_to_user(buf + count - size, &val, 4))
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return -EFAULT;
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pos += 4;
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size -= 4;
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}
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while (size >= 2) {
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u16 val;
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ret = pci_user_read_config_word(pdev, pos, &val);
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if (ret)
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return pcibios_err_to_errno(ret);
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val = cpu_to_le16(val);
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if (copy_to_user(buf + count - size, &val, 2))
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return -EFAULT;
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pos += 2;
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size -= 2;
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}
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while (size) {
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u8 val;
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ret = pci_user_read_config_byte(pdev, pos, &val);
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if (ret)
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return pcibios_err_to_errno(ret);
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if (copy_to_user(buf + count - size, &val, 1))
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return -EFAULT;
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pos++;
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size--;
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}
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*ppos += count;
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return count;
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}
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static void vfio_pci_igd_cfg_release(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region)
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{
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struct pci_dev *pdev = region->data;
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pci_dev_put(pdev);
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}
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static const struct vfio_pci_regops vfio_pci_igd_cfg_regops = {
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.rw = vfio_pci_igd_cfg_rw,
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.release = vfio_pci_igd_cfg_release,
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};
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static int vfio_pci_igd_cfg_init(struct vfio_pci_device *vdev)
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{
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struct pci_dev *host_bridge, *lpc_bridge;
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int ret;
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host_bridge = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!host_bridge)
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return -ENODEV;
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if (host_bridge->vendor != PCI_VENDOR_ID_INTEL ||
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host_bridge->class != (PCI_CLASS_BRIDGE_HOST << 8)) {
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pci_dev_put(host_bridge);
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return -EINVAL;
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}
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ret = vfio_pci_register_dev_region(vdev,
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PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
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VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG,
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&vfio_pci_igd_cfg_regops, host_bridge->cfg_size,
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VFIO_REGION_INFO_FLAG_READ, host_bridge);
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if (ret) {
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pci_dev_put(host_bridge);
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return ret;
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}
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lpc_bridge = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x1f, 0));
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if (!lpc_bridge)
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return -ENODEV;
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if (lpc_bridge->vendor != PCI_VENDOR_ID_INTEL ||
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lpc_bridge->class != (PCI_CLASS_BRIDGE_ISA << 8)) {
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pci_dev_put(lpc_bridge);
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return -EINVAL;
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}
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ret = vfio_pci_register_dev_region(vdev,
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PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
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VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG,
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&vfio_pci_igd_cfg_regops, lpc_bridge->cfg_size,
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VFIO_REGION_INFO_FLAG_READ, lpc_bridge);
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if (ret) {
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pci_dev_put(lpc_bridge);
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return ret;
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}
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return 0;
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}
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int vfio_pci_igd_init(struct vfio_pci_device *vdev)
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{
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int ret;
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ret = vfio_pci_igd_opregion_init(vdev);
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if (ret)
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return ret;
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ret = vfio_pci_igd_cfg_init(vdev);
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if (ret)
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return ret;
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return 0;
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}
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