302 lines
7.3 KiB
C
Executable File
302 lines
7.3 KiB
C
Executable File
/**
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NVT evb board file
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To handle na510xx HW init.
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@file na510xx_hw_init.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/mach-types.h>
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#include <asm/nvt-common/nvt_common.h>
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#include <asm/nvt-common/rcw_macro.h>
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#include <asm/arch/IOAddress.h>
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#include <asm/arch/efuse_protected.h>
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#ifdef CONFIG_NVT_IVOT_DDR_RANGE_SCAN_SUPPORT
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#include <asm/arch/raw_scanMP.h>
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#include <asm/arch/hardware.h>
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#endif
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#include <linux/libfdt.h>
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#define WDT_REG_ADDR(ofs) (IOADDR_WDT_REG_BASE+(ofs))
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#define WDT_GETREG(ofs) INW(WDT_REG_ADDR(ofs))
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#define WDT_SETREG(ofs,value) OUTW(WDT_REG_ADDR(ofs), (value))
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#define CG_REG_ADDR(ofs) (IOADDR_CG_REG_BASE+(ofs))
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#define CG_GETREG(ofs) INW(CG_REG_ADDR(ofs))
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#define CG_SETREG(ofs,value) OUTW(CG_REG_ADDR(ofs), (value))
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#define PAD_REG_ADDR(ofs) (IOADDR_PAD_REG_BASE+(ofs))
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#define PAD_GETREG(ofs) INW(PAD_REG_ADDR(ofs))
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#define PAD_SETREG(ofs,value) OUTW(PAD_REG_ADDR(ofs), (value))
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#define TOP_REG_ADDR(ofs) (IOADDR_TOP_REG_BASE+(ofs))
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#define TOP_GETREG(ofs) INW(TOP_REG_ADDR(ofs))
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#define TOP_SETREG(ofs,value) OUTW(TOP_REG_ADDR(ofs), (value))
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#define CG_PLL_ENABLE_OFS 0x0
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#define CG_ENABLE_OFS 0x74
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#define CG_RESET_OFS 0x84
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#define CG_PLL4_DIV0_OFS 0x1318
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#define CG_PLL4_DIV1_OFS 0x131C
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#define CG_PLL4_DIV2_OFS 0x1320
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#define WDT_POS (1 << 17)
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#define WDT_CTRL_OFS 0x0
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#if defined(CONFIG_SD_CARD1_POWER_PIN) || defined(CONFIG_SD_CARD2_POWER_PIN) || defined(ETH_PHY_HW_RESET)
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static void gpio_set_output(u32 pin)
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{
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u32 reg_data;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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reg_data = INW(IOADDR_GPIO_REG_BASE + 0x20 + ofs);
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reg_data |= (1 << pin); //output
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OUTW(IOADDR_GPIO_REG_BASE + 0x20 + ofs, reg_data);
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}
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static void gpio_set_pin(u32 pin)
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{
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u32 tmp;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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tmp = (1 << pin);
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OUTW(IOADDR_GPIO_REG_BASE + 0x40 + ofs, tmp);
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}
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static void gpio_clear_pin(u32 pin)
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{
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u32 tmp;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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tmp = (1 << pin);
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OUTW(IOADDR_GPIO_REG_BASE + 0x60 + ofs, tmp);
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}
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#endif
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void nvt_pllen(u32 id, u32 b_enable)
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{
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u32 reg_data;
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reg_data = CG_GETREG(CG_PLL_ENABLE_OFS);
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if(b_enable){
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reg_data |= (1 <<id);
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}
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else
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{
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reg_data &= ~(1 << id);
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}
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CG_SETREG(CG_PLL_ENABLE_OFS, reg_data);
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}
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void nvt_ivot_reset_cpu(void)
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{
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u32 reg_value;
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reg_value = CG_GETREG(CG_ENABLE_OFS);
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CG_SETREG(CG_ENABLE_OFS, reg_value | WDT_POS);
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reg_value = CG_GETREG(CG_RESET_OFS);
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CG_SETREG(CG_RESET_OFS, reg_value | WDT_POS);
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WDT_SETREG(WDT_CTRL_OFS, 0x5A960112);
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udelay(80);
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WDT_SETREG(WDT_CTRL_OFS, 0x5A960113);
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}
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static void ethernet_init(void)
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{
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#if 0
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ulong fdt_addr = nvt_readl((ulong)nvt_shminfo_boot_fdt_addr);
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int nodeoffset, len;
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u32 *cell = NULL;
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char path[20] = {0};
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u32 sensor_cfg = 0x0, eth_cfg = 0x0, reg_val = 0x0;
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sprintf(path,"/top@%x/sensor",IOADDR_TOP_REG_BASE);
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nodeoffset = fdt_path_offset((const void*)fdt_addr, path);
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if (nodeoffset < 0) {
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printf("%s(%d) nodeoffset < 0\n",__func__, __LINE__);
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return ;
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}
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cell = (u32*)fdt_getprop((const void*)fdt_addr, nodeoffset, "pinmux", &len);
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if (len == 0) {
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printf("%s(%d) len = 0\n",__func__, __LINE__);
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return ;
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}
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sensor_cfg = __be32_to_cpu(cell[0]);
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debug("%s(%d) sensor_cfg = 0x%x\n", __func__, __LINE__, sensor_cfg);
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sprintf(path,"/eth@%x",IOADDR_ETH_REG_BASE);
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nodeoffset = fdt_path_offset((const void*)fdt_addr, path);
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if (nodeoffset < 0) {
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printf("%s(%d) nodeoffset < 0\n", __func__, __LINE__);
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return ;
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}
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cell = (u32*)fdt_getprop((const void*)fdt_addr, nodeoffset, "sp-clk", &len);
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if (len == 0) {
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printf("%s(%d) len = 0\n", __func__, __LINE__);
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return ;
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}
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eth_cfg = __be32_to_cpu(cell[0]);
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debug("%s(%d) eth_cfg = 0x%x\n", __func__, __LINE__, eth_cfg);
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if ((sensor_cfg & 0x20000) || (eth_cfg == 1)) {
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/* Disable PLL4 */
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reg_val = CG_GETREG(CG_PLL_ENABLE_OFS);
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reg_val &= ~(0x1 << 4);
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CG_SETREG(CG_PLL_ENABLE_OFS, reg_val);
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CG_SETREG(CG_PLL4_DIV0_OFS, 0x0);
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CG_SETREG(CG_PLL4_DIV1_OFS, 0x0);
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CG_SETREG(CG_PLL4_DIV2_OFS, 0x32);
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/* spclk_sel: pll4 */
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reg_val = CG_GETREG(0x24);
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reg_val &= ~0x4300;
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reg_val |= (0x1 << 8);
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CG_SETREG(0x24, reg_val);
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reg_val = CG_GETREG(0x3C);
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reg_val &= ~0xFF000000;
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reg_val |= (0xB << 24);
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CG_SETREG(0x3C, reg_val);
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/* Enable PLL4 */
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reg_val = CG_GETREG(CG_PLL_ENABLE_OFS);
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reg_val |= (0x1 << 4);
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CG_SETREG(CG_PLL_ENABLE_OFS, reg_val);
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/* Enable SP_CLK */
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reg_val = CG_GETREG(0x70);
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reg_val |= (0x1 << 12);
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CG_SETREG(0x70, reg_val);
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/* Pinmux SP_CLK1 */
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reg_val = TOP_GETREG(0xC);
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reg_val &= ~(0x3 << 18);
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reg_val |= (0x1 << 18);
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TOP_SETREG(0xC, reg_val);
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/* Pinmux P_GPIO17 */
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reg_val = TOP_GETREG(0xA8);
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reg_val &= ~(0x1 << 17);
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TOP_SETREG(0xA8, reg_val);
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}
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#endif
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#ifdef ETH_PHY_HW_RESET
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gpio_set_output(NVT_PHY_RST_PIN);
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gpio_clear_pin(NVT_PHY_RST_PIN);
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mdelay(20);
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gpio_set_pin(NVT_PHY_RST_PIN);
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mdelay(50);
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#endif
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}
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static void usbphy_init(void)
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{
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if (TOP_GETREG(0xF0) == 0x50210000) {
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//printf("********************%s(%d) Add USB528 INIT********************************************\n",__func__, __LINE__);
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OUTW(0xFF600400, (INW(0xFF600400))|(0x1 << 21));
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OUTW(0xFF6001C8, (INW(0xFF6001C8))|(0x1 << 31));
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} else {
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//printf("********************%s(%d) Add USB520 INIT********************************************\n",__func__, __LINE__);
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OUTW(0xF0600310, (INW(0xF0600310))|(0x1 << 1));
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OUTW(0xF06001C8, (INW(0xF06001C8))|(0x1 << 5));
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}
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}
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static void axi_bridge_timeout_en(void)
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{
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OUTW(0xF0012018, 0x7c);
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OUTW(0xF0013018, 0x7c);
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}
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int nvt_ivot_hw_init(void)
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{
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if (nvt_ivot_set_cpuclk() != 0) {
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printf("Set CPU clock fail, use default clock frequency\n");
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}
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ethernet_init();
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axi_bridge_timeout_en();
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usbphy_init();
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return 0;
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}
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int nvt_ivot_hw_init_early(void)
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{
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otp_init();
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return 0;
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}
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#ifdef CONFIG_NVT_IVOT_DDR_RANGE_SCAN_SUPPORT
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typedef void (*LDR_GENERIC_CB)(void);
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#define JUMP_ADDR 0xf07C0000
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void nvt_ddr_scan(void)
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{
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u32 iLibVersion;
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u32 iLibDRAMVersion;
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int YY,MM,DD,VER;
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int LD_MJ, LD_MIN, VER_Fix;
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iLibVersion = *(UINT32 *)(ddr_scan + (0x74/4)); //0x74
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iLibDRAMVersion = *(UINT32 *)(ddr_scan + (0x78/4)); //0x78
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YY = 2020 + (iLibDRAMVersion & 0x7);
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MM = ((iLibDRAMVersion >> 3) & 0xF);
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DD = ((iLibDRAMVersion >> 7) & 0x1F);
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VER= ((iLibDRAMVersion >> 12) & 0xF);
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VER_Fix = ((iLibVersion >> 16) & 0xFF);
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LD_MIN = ((iLibVersion >> 24) & 0xF);
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LD_MJ = ((iLibVersion >> 28) & 0xF);
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printf("\r\n");
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printf("DR[%d-%d-%d-%d]:", YY, MM, DD, VER);
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printf("LD[%d.%d.%d]", LD_MJ, LD_MIN, VER_Fix);
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void (*image_entry)(void) = NULL;
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printf("memcpy->[0x%08x]", (int)JUMP_ADDR);
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if (nvt_get_chip_id() == CHIP_NA51089) {
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memcpy((void *)JUMP_ADDR, ddr_scan, sizeof(ddr_scan));
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printf("->done\n");
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flush_dcache_range(JUMP_ADDR, JUMP_ADDR + sizeof(ddr_scan));
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printf("flush->");
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invalidate_dcache_range(JUMP_ADDR, JUMP_ADDR + roundup(sizeof(ddr_scan), ARCH_DMA_MINALIGN));
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} else {
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printf("Not support\n");
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}
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printf("done\r\n");
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printf("Jump into sram\n");
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image_entry = (LDR_GENERIC_CB)(*((unsigned long*)JUMP_ADDR));
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image_entry();
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}
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#endif
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