156 lines
3.2 KiB
C
156 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
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{
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.num = 2,
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.pin = 20,
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.reg = 0xe8,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 21,
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.reg = 0xe8,
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.bit = 4,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 22,
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.reg = 0xe8,
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.bit = 8,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 23,
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.reg = 0xe8,
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.bit = 12,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 24,
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.reg = 0xd4,
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.bit = 12,
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.mask = 0x7
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},
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};
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static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
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{
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/* spi-0 */
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.bank_num = 1,
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.pin = 10,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4),
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}, {
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/* spi-1 */
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.bank_num = 1,
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.pin = 27,
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.func = 3,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
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}, {
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/* spi-2 */
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.bank_num = 0,
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.pin = 13,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
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}, {
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/* i2s-0 */
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.bank_num = 1,
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.pin = 5,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 5),
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}, {
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/* i2s-1 */
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.bank_num = 0,
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.pin = 14,
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.func = 1,
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.route_offset = 0x144,
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.route_val = BIT(16 + 5) | BIT(5),
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}, {
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/* emmc-0 */
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.bank_num = 1,
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.pin = 22,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 6),
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}, {
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/* emmc-1 */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.route_offset = 0x144,
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.route_val = BIT(16 + 6) | BIT(6),
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},
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};
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#define RK3128_PULL_OFFSET 0x118
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#define RK3128_PULL_PINS_PER_REG 16
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#define RK3128_PULL_BANK_STRIDE 8
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static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3128_PULL_OFFSET;
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*reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
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*reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3128_PULL_PINS_PER_REG;
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}
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static struct rockchip_pin_bank rk3128_pin_banks[] = {
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PIN_BANK(0, 32, "gpio0"),
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PIN_BANK(1, 32, "gpio1"),
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PIN_BANK(2, 32, "gpio2"),
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PIN_BANK(3, 32, "gpio3"),
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};
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static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
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.pin_banks = rk3128_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
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.label = "RK3128-GPIO",
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.type = RK3128,
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.grf_mux_offset = 0xa8,
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.iomux_recalced = rk3128_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
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.iomux_routes = rk3128_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
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.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
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};
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static const struct udevice_id rk3128_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk3128-pinctrl",
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.data = (ulong)&rk3128_pin_ctrl },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3128) = {
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.name = "pinctrl_rk3128",
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.id = UCLASS_PINCTRL,
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.of_match = rk3128_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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