508 lines
18 KiB
C
Executable File
508 lines
18 KiB
C
Executable File
/**
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@file pwm.h
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@ingroup mIDrvIO_PWM
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@brief Header file for PWM module
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This file is the header file that define the API for PWM module
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Copyright Novatek Microelectronics Corp. 2012. All rights reserved.
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*/
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#ifndef _PWM_H
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#define _PWM_H
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#ifdef __KERNEL__
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#include "kwrap/type.h"
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#elif defined(__FREERTOS)
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#include "kwrap/type.h"
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#else
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#include "type.h"
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#endif
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/**
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@addtogroup mIDrvIO_PWM
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*/
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//@{
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/**
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PWM micro step direction
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Micro step direction configuration
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@note for pwm_mstep_config() pwm_mstep_config_set()
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*/
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typedef enum {
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MS_DIR_INCREASE = 0x0, ///< CounterClockwise
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MS_DIR_DECREASE, ///< Clockwise
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MS_DIR_CNT,
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ENUM_DUMMY4WORD(PWM_MS_DIR)
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} PWM_MS_DIR;
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/**
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PWM type (PWM or Micro step)
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*/
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typedef enum {
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PWM_TYPE_PWM = 0x0, ///< PWM
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PWM_TYPE_MICROSTEP, ///< Micro step
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PWM_TYPE_CCNT, ///< CCNT
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PWM_TYPE_CNT,
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ENUM_DUMMY4WORD(PWM_TYPE)
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} PWM_TYPE;
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/**
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PWM clock divid
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@note for pwm_pwm_config_clock_div()
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*/
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typedef enum {
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PWM0_3_CLKDIV = 0x0, ///< PWM0~PWM3 clock divid
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PWM4_7_CLKDIV, ///< PWM4~PWM7 clock divid
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PWM8_CLKDIV = 8, ///< PWM8 clock divid
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PWM9_CLKDIV, ///< PWM9 clock divid
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PWM10_CLKDIV, ///< PWM10 clock divid
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PWM11_CLKDIV, ///< PWM11 clock divid
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ENUM_DUMMY4WORD(PWM_CLOCK_DIV)
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} PWM_CLOCK_DIV;
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/**
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PWM micro step phase type (1-2 or 2-2 phase)
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@note for pwm_mstep_config() pwm_mstep_config_set()
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*/
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typedef enum {
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PWM_MS_1_2_PHASE_TYPE = 0x0, ///< 1 unit each operation
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PWM_MS_2_2_PHASE_TYPE, ///< 2 unit each operation
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PWM_MS_PHASE_TYPE_CNT,
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ENUM_DUMMY4WORD(PWM_MS_PHASE_TYPE)
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} PWM_MS_PHASE_TYPE;
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/**
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PWM Micro step step per phase
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PWM Micro step step per phase configuration
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@note for pwm_mstep_config() pwm_mstep_config_set()
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*/
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typedef enum {
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TOTAL_08_STEP_PER_PHASE = 8, ///< 8 steps each phase
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TOTAL_16_STEP_PER_PHASE = 16, ///< 16 steps each phase
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TOTAL_32_STEP_PER_PHASE = 32, ///< 32 steps each phase
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TOTAL_64_STEP_PER_PHASE = 64, ///< 64 steps each phase
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ENUM_DUMMY4WORD(PWM_MS_STEP_PER_PHASE)
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} PWM_MS_STEP_PER_PHASE;
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/**
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PWM Micro step channel level
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PWM Micro step channel level configuation
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*/
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typedef enum {
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PWM_MS_CHANNEL_LEVEL_LOW = 0x0, ///< PWM MS channel level low
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PWM_MS_CHANNEL_LEVEL_HIGH, ///< PWM MS channel level high
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ENUM_DUMMY4WORD(PWM_MS_CHANNEL_LEVEL)
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} PWM_MS_CHANNEL_LEVEL;
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/**
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PWM Micro step channel set
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PWM Micro step channel set definition
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@note for pwm_open_set, pwm_close_set, pwm_wait_set(), pwm_configClockDivSet(), pwm_mstep_config_set(),\n
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pwm_pwm_enable_set(), pwm_pwm_disable_set(), pwm_mstep_enable_set(), pwm_mstep_disable_set()
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*/
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typedef enum {
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PWM_MS_SET_0 = 0x0, ///< PWM MS channel set 0, including PWM0-3
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PWM_MS_SET_1, ///< PWM MS channel set 1, including PWM4-7
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PWM_MS_SET_TOTAL,
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ENUM_DUMMY4WORD(PWM_MS_CHANNEL_SET)
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} PWM_MS_CHANNEL_SET;
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/**
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Micro step target count set(s)
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@note for pwm_mstep_config_target_count_enable()
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*/
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typedef enum {
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PWM_00_03_TGT_CNT = 0x0, ///< PWM0~PWM3 target count
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PWM_04_07_TGT_CNT, ///< PWM4~PWM7 target count
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PWM_TGT_CNT_NUM,
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ENUM_DUMMY4WORD(PWM_TGT_COUNT)
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} PWM_TGT_COUNT;
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/**
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PWM CCNT count down policy
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@note for pwm_ccnt_config()
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*/
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typedef enum {
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PWM_CCNT_COUNT_INCREASE = 0x0, ///< PWM cycle count increase
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PWM_CCNT_COUNT_DECREASE, ///< PWM cycle count decrease
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PWM_CCNT_COUNT_POLICY_CNT,
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ENUM_DUMMY4WORD(PWM_CCNT_COUNTDOWN)
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} PWM_CCNT_COUNTDOWN;
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/**
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PWM CCNT signal source
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@note for pwm_ccnt_config()
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*/
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typedef enum {
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PWM_CCNT_SIGNAL_GPIO = 0x0, ///< Signal from GPIO (default value)
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PWM_CCNT_SIGNAL_ADC, ///< Signal from ADC channel( CCNT0 & 2 from ADC ch1 / CCNT1 & 3 from ADC ch2)
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PWM_CCNT_SIGNAL_CNT,
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ENUM_DUMMY4WORD(PWM_CCNT_SIGNAL_SOURCE)
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} PWM_CCNT_SIGNAL_SOURCE;
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/**
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PWM CCNT interrupt trigger event
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@note for pwm_ccnt_config()
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*/
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typedef enum {
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PWM_CCNT_EDGE_TRIG_INTEN = 0x1, ///< CCNT target value arrived interrupt
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PWM_CCNT_TAGT_TRIG_INTEN = 0x2, ///< CCNT edge triggerd interrupt\n
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///< (depend on ui_count_mode set PWM_CCNT_MODE_PULSE or PWM_CCNT_MODE_EDGE)
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///< @note PWM_CCNT_MODE_PULSE, PWM_CCNT_MODE_EDGE
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PWM_CCNT_TRIG_INTEN_CNT,
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ENUM_DUMMY4WORD(PWM_CCNT_TRIG_INTERRUPT)
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} PWM_CCNT_TRIG_INTERRUPT;
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/**
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PWM CCNT interrupt trigger event
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@note for pwm_ccnt_config()
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*/
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typedef enum {
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PWM_CCNT_EDGE_TRIG = 0x1, ///< CCNT target value arrived trigger
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PWM_CCNT_TAGT_TRIG = 0x2, ///< CCNT edge trigger
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///< @note PWM_CCNT_MODE_PULSE,PWM_CCNT_MODE_EDGE
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PWM_CCNT_TOUT_TRIG = 0x4, ///< CCNT time out trigger
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PWM_CCNT_TRIG_CNT,
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ENUM_DUMMY4WORD(PWM_CCNT_TRIG_TYPE)
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} PWM_CCNT_TRIG_TYPE;
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/**
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PWM destination
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@note for pwm_set_destination()
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*/
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typedef enum {
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PWM_DEST_TO_CPU1 = 0x1, ///< PWM interrupt destination to CPU1
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PWM_DEST_TO_CPU2 = 0x2, ///< PWM interrupt destination to CPU2
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ENUM_DUMMY4WORD(PWM_DEST)
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} PWM_DEST;
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/**
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PWM configuration identifier
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@note For pwm_set_config()
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*/
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typedef enum {
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PWM_CONFIG_ID_AUTOPINMUX, ///< Context can be one of the following:
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///< - @b TRUE : disable pinmux when pwm driver close
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///< - @b FALSE : not disable pinmux when pwm driver close
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PWM_CONFIG_ID_PWM_DEBUG, ///< Enable/Disable pwm debug messages
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PWM_CONFIG_ID_PWM_OPEN_DESTINATION, ///< The pwm channel will set this destination when pwm_open;
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///< PWM_DEST_TO_CPU1 : destination to CPU1 (defalut)
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///< PWM_DEST_TO_CPU2 : destination to CPU2
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PWM_CONFIG_ID_DISABLE_CCNT_AFTER_TARGET, ///< Disable ccnt after target value trigger
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#if defined(__FREERTOS)
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PWM_CONFIG_ID_PWM_REQUEST_IRQ, ///< Force to request_irq;
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///< PWM_DEST_TO_CPU1 : request pwm_isr
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///< PWM_DEST_TO_CPU2 : request pwm_isr2
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PWM_CONFIG_ID_PWM_FREE_IRQ, ///< Force to free_irq;
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///< PWM_DEST_TO_CPU1 : free pwm_isr
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///< PWM_DEST_TO_CPU2 : free pwm_isr2
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#endif
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ENUM_DUMMY4WORD(PWM_CONFIG_ID)
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} PWM_CONFIG_ID;
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/**
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PWM configuration structure
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@note for pwm_set()
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*/
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typedef struct {
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#if 0
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UINT32 ui_div; ///< Clock divider, PWM clock = 120MHZ / (ui_div + 1), ui_div = 3 ~ 16383, min value = 3
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///< @note 1. ui_div MUST >= 3, if ui_div < 3, driver will force set as 3
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///< \n2. PWM0-3, PWM4-7 and PWM8-11 are use same clock source respectively
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///< \n3. Others(PWM12-19) use dedicate clock source respectively
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#endif
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UINT32 ui_prd; ///< Base period, how many PWM clock per period, 2 ~ 255
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///< @note ui_rise <= ui_fall <= ui_prd
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UINT32 ui_rise; ///< Rising at which clock
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///< @note ui_rise <= ui_fall <= ui_prd
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UINT32 ui_fall; ///< Falling at which clock
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///< @note ui_rise <= ui_fall <= ui_prd
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UINT32 ui_on_cycle; ///< Output cycle, 0 ~ 65535
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///< - @b PWM_FREE_RUN: Free Run
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///< - @b Others: How many cycles (PWM will stop after output the cycle counts)
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UINT32 ui_inv; ///< Invert PWM output signal or not
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///< - @b PWM_SIGNAL_NORMAL: Don't invert PWM output signal
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///< - @b PWM_SIGNAL_INVERT: Invert PWM output signal
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} PWM_CFG, *PPWM_CFG;
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/**
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PWM CCNT configuration structure
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*/
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typedef struct {
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UINT32 ui_start_value; ///< CCNT start count value, 0 ~ 0xFFFF (Starting count value)
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UINT32 ui_trigger_value; ///< CCNT target trigger value, 0 ~ 0xFFFF (trigger count value)
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UINT32 ui_filter; ///< Filter glitch of input signal, value is 0 ~ 255. If the glitch width is smaller than (CCNTx_FILTER * 8) + 1 cycles, then the glitch will be filtered out.
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UINT32 ui_inv; ///< Invert CCNT input signal or not
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///< - @b PWM_CCNT_SIGNAL_NORMAL: Don't invert CCNT input signal
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///< - @b PWM_CCNT_SIGNAL_INVERT: Invert CCNT input signal
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UINT32 ui_mode; ///< CCNT mode
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///< - @b PWM_CCNT_MODE_PULSE: Counting pulse only
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///< - @b PWM_CCNT_MODE_EDGE: Counting edge, both rising and falling edges
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PWM_CCNT_SIGNAL_SOURCE ui_sig_src; ///< CCNT signal source
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///< - @b PWM_CCNT_SIGNAL_GPIO : Signal from GPIO (default value)
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///< - @b PWM_CCNT_SIGNAL_ADC : Signal from ADC channel( CCNT0 & 3 from ADC ch1 / CCNT1 from ADC ch2 / CCNT2 from ADC ch6)
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PWM_CCNT_COUNTDOWN ui_count_mode; ///< CCNT count mode
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///< - @b PWM_CCNT_COUNT_INCREASE: The value of CCNT0_CURRENT_VAL will be increased by one when detecting one pulse or edge( by CCNT0_MODE)
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///< - @b PWM_CCNT_COUNT_DECREASE: The value of CCNT0_CURRENT_VAL will be decreased by one when detecting one pulse or edge( by CCNT0_MODE)
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PWM_CCNT_TRIG_INTERRUPT ui_trig_int_en; ///< CCNT interrupt issue condition (can occurred mutiple condition at the same time)
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///< @note PWM_CCNT_TRIG_INTERRUPT
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///< - @b TRUE : Trigger at each edge(rising or both rasing & faling depend on ui_mode configuration
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///< - @b FALSE : Trigger at target value arrived.
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} PWM_CCNT_CFG, *PPWM_CCNT_CFG;
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/**
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PWM CCNT time out configuration structure
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@note for pwm_ccnt_enable()
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*/
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typedef struct {
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BOOL ub_tout_en; ///< CCNT timeout enable
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UINT32 ui_tout_value; ///< CCNT timeout value
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} PWM_CCNT_TOUT_CFG, *PPWM_CCNT_TOUT_CFG;
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/**
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MSTP configuration structure
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@note for pwm_mstep_config()
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*/
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typedef struct {
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UINT32 ui_ph; ///< Micro step starting phase, phase 0 ~ 7
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UINT32 ui_dir; ///< Micro step moving direction ,
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///< - @b MS_DIR_INCREASE
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///< - @b MS_DIR_DECREASE
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UINT32 ui_on_cycle; ///< Number of phase for Micro step mode
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UINT32 ui_step_per_phase; ///< Step per phase
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///< - @b TOTAL_08_STEP_PER_PHASE (8 steps each phase)
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///< - @b TOTAL_16_STEP_PER_PHASE (16 steps each phase)
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///< - @b TOTAL_32_STEP_PER_PHASE (32 steps each phase)
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///< - @b TOTAL_64_STEP_PER_PHASE (64 steps each phase)
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UINT32 ui_phase_type; ///< 1-2 or 2-2 phase
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///< - @b PWM_MS_1_2_PHASE_TYPE (1 unit each operation)
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///< - @b PWM_MS_2_2_PHASE_TYPE (2 unit each operation)
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BOOL ui_threshold_en; ///< Enable threshold filter(always set as FALSE), TRUE for test only
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UINT32 ui_threshold; ///< Max 0x63
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BOOL is_square_wave; ///< square wave or micro stepping
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///< - @b TRUE (square)
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///< - @b FALSE (micro-stepping)
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} MSTP_CFG, *PMSTP_CFG;
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/**
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Micro step channels (within a set) phase configuration
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@note for pwm_mstep_config_set()
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*/
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typedef struct {
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UINT32 ui_ch0_phase; ///< Specific MS set channel 0 start phase
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UINT32 ui_ch1_phase; ///< Specific MS set channel 1 start phase
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UINT32 ui_ch2_phase; ///< Specific MS set channel 2 start phase
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UINT32 ui_ch3_phase; ///< Specific MS set channel 3 start phase
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} MS_CH_PHASE_CFG, *PMS_CH_PHASE_CFG;
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/**
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Micro step channels (within a set) level configuration
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@note for PWM_MS_CHANNEL_LEVEL_LOW or PWM_MS_CHANNEL_LEVEL_HIGH,
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*/
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typedef struct {
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UINT32 ui_ch0_level; ///< Specific MS channel 0 level
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UINT32 ui_ch1_level; ///< Specific MS channel 1 level
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UINT32 ui_ch2_level; ///< Specific MS channel 2 level
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UINT32 ui_ch3_level; ///< Specific MS channel 3 level
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} MS_CH_LEVEL_CFG, *PMS_CH_LEVEL_CFG;
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/**
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MSTP configuration structure
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@note for pwm_mstep_config_set()
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*/
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typedef struct {
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UINT32 ui_dir; ///< Micro step moving direction ,
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///< - @b MS_DIR_INCREASE
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///< - @b MS_DIR_DECREASE
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UINT32 ui_on_cycle; ///< Number of phase for Micro step mode
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UINT32 ui_step_per_phase; ///< Step per phase
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///< - @b TOTAL_08_STEP_PER_PHASE (8 steps each phase)
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///< - @b TOTAL_16_STEP_PER_PHASE (16 steps each phase)
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///< - @b TOTAL_32_STEP_PER_PHASE (32 steps each phase)
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///< - @b TOTAL_64_STEP_PER_PHASE (64 steps each phase)
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UINT32 ui_phase_type; ///< 1-2 or 2-2 phase
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///< - @b PWM_MS_1_2_PHASE_TYPE (1 unit each operation)
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///< - @b PWM_MS_2_2_PHASE_TYPE (2 unit each operation)
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BOOL ui_threshold_en; ///< Enable threshold filter
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UINT32 ui_threshold; ///< Max 0x63
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BOOL is_square_wave; ///< square wave or micro stepping
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///< - @b TRUE (square)
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///< - @b FALSE (micro-stepping)
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} MSCOMMON_CFG, *PMSCOMMON_CFG;
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/**
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@name PWM cycle type free run configuratopn
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@note pwm_set(), pwm_ms_set()
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*/
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//@{
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#define PWM_FREE_RUN 0 ///< For pwm_set() API, output cycle is free run
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//@}
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/**
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@name PWM output signal mode
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Invert PWM output signal or not for pwm_set() API
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*/
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//@{
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#define PWM_SIGNAL_NORMAL 0 ///< Don't invert PWM output signal
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#define PWM_SIGNAL_INVERT 1 ///< Invert PWM output signal
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//@}
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/**
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@name CCNT input signal mode
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Invert CCNT input signal or not for pwm_setCCNT() API
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*/
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//@{
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#define PWM_CCNT_SIGNAL_NORMAL 0 ///< Don't invert CCNT input signal
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#define PWM_CCNT_SIGNAL_INVERT 1 ///< Invert CCNT input signal
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//@}
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/**
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@name PWM CCNT mode
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PWM CCNT mode for pwm_ccnt_config() API
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*/
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//@{
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#define PWM_CCNT_MODE_PULSE 0 ///< Counting pulse only
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///< Example:
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///< @code
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/// {
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/// ____
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/// ___| |___
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/// ==> count only raising edge => result is 1
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/// }
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/// @endcode
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#define PWM_CCNT_MODE_EDGE 1 ///< Counting edge, both rising and falling edges
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///< Example:
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///< @code
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/// {
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/// ____
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/// ___| |___
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/// ==> count both raising & faling edge => result is 2
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/// }
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/// @endcode
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//@}
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/**
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@name PWM ID
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PWM ID for PWM driver API
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@note for pwm_open(), pwm_set(), pwm_setCCNT(), pwm_setCCNTToutEN(), pwm_wait(), pwm_stop(), pwm_en(), pwm_reload(),\n
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pwm_ms_set(), pwm_ms_stop(), pwm_ms_en(), pwm_getCycleNumber(), pwm_ccnt_get_current_val(), pwm_ccnt_get_current_val(),\n
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pwm_ccnt_enable()
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*/
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//@{
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#define PWMID_0 0x00000001 ///< PWM ID 0
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#define PWMID_1 0x00000002 ///< PWM ID 1
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#define PWMID_2 0x00000004 ///< PWM ID 2
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#define PWMID_3 0x00000008 ///< PWM ID 3
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#define PWMID_4 0x00000010 ///< PWM ID 4
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#define PWMID_5 0x00000020 ///< PWM ID 5
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#define PWMID_6 0x00000040 ///< PWM ID 6
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#define PWMID_7 0x00000080 ///< PWM ID 7
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#define PWMID_8 0x00000100 ///< PWM ID 8
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#define PWMID_9 0x00000200 ///< PWM ID 9
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#define PWMID_10 0x00000400 ///< PWM ID 10
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#define PWMID_11 0x00000800 ///< PWM ID 11
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#define PWMID_CCNT0 0x00001000 ///< PWM ID CCNT0
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#define PWMID_CCNT1 0x00002000 ///< PWM ID CCNT1
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#define PWMID_CCNT2 0x00004000 ///< PWM ID CCNT2
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//@}
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// PWM Driver API
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extern ER pwm_open(UINT32 ui_pwm_id);
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extern ER pwm_open_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern UINT32 pwm_pwm_get_cycle_number(UINT32 ui_pwm_id);
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extern ER pwm_close(UINT32 ui_pwm_id, BOOL b_wait_auto_disable_done);
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extern ER pwm_close_set(PWM_MS_CHANNEL_SET ui_ms_set, BOOL b_wait_auto_disable_done);
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extern ER pwm_wait(UINT32 ui_pwm_id, PWM_TYPE ui_pwm_type);
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extern ER pwm_wait_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern ER pwm_pwm_reload(UINT32 ui_pwm_id);
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extern ER pwm_pwm_enable(UINT32 ui_pwm_id);
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extern ER pwm_pwm_disable(UINT32 ui_pwm_id);
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extern ER pwm_pwm_enable_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern ER pwm_pwm_disable_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern ER pwm_pwm_config(UINT32 ui_pwm_id, PPWM_CFG p_pwm_cfg);
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extern ER pwm_pwm_config_clock_div(PWM_CLOCK_DIV ui_clk_src, UINT32 ui_div);
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extern ER pwm_pwm_reload_config(UINT32 ui_pwm_id, INT32 i_rise, INT32 i_fall, INT32 i_base_period);
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extern ER pwm_mstep_enable(UINT32 ui_pwm_id);
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extern ER pwm_mstep_disable(UINT32 ui_pwm_id, BOOL b_wait);
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extern ER pwm_mstep_enable_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern ER pwm_mstep_disable_set(PWM_MS_CHANNEL_SET ui_ms_set);
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extern ER pwm_mstep_clock_div_reload(PWM_CLOCK_DIV ui_pwm_clk_div, BOOL b_wait_done);
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extern ER pwm_mstep_config(UINT32 ui_pwm_id, PMSTP_CFG p_mstp_cfg);
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extern ER pwm_mstep_target_count_wait_done(PWM_TGT_COUNT ui_target_cnt);
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extern ER pwm_mstep_clk_div_wait_load_done(PWM_CLOCK_DIV ui_pwm_clk_div_src);
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extern ER pwm_mstep_config_clock_div(PWM_MS_CHANNEL_SET ui_ms_set, UINT32 ui_div);
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extern ER pwm_mstep_config_target_count_enable(PWM_TGT_COUNT ui_target_cnt_set, UINT32 ui_target_cnt, BOOL b_enable_target_cnt);
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extern ER pwm_mstep_config_set(PWM_MS_CHANNEL_SET ui_ms_set, PMS_CH_PHASE_CFG p_ms_set_ch_ph_cfg, PMSCOMMON_CFG p_ms_common_cfg);
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extern ER pwm_ccnt_enable(UINT32 ui_pwm_id);
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extern ER pwm_ccnt_reload(UINT32 ui_pwm_id);
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extern UINT32 pwm_ccnt_get_current_val(UINT32 ui_pwm_id);
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extern UINT32 pwm_ccnt_get_start_value(UINT32 ui_pwm_id);
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extern UINT32 pwm_ccnt_get_edge_interval(UINT32 ui_pwm_id);
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extern ER pwm_ccnt_config(UINT32 ui_pwm_id, PPWM_CCNT_CFG p_ccnt_cfg);
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extern ER pwm_set_config(PWM_CONFIG_ID config_id, UINT32 ui_config);
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extern ER pwm_ccnt_config_timeout_enable(UINT32 ui_pwm_id, PPWM_CCNT_TOUT_CFG p_ccnt_tout_cfg);
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//@}
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#endif
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