494 lines
23 KiB
C
Executable File
494 lines
23 KiB
C
Executable File
/*
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* Faraday USB 2.0 OTG Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _NVT_UDC_H
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#define _NVT_UDC_H
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struct nvt_udc_regs {
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/* USB Host Controller */
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struct {
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uint32_t data[4];
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} hccr; /* 0x00 - 0x0f: hccr */
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struct {
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uint32_t data[9];
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} hcor; /* 0x10 - 0x33: hcor */
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uint32_t rsvd1[3];
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uint32_t miscr; /* 0x40: Miscellaneous Register */
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uint32_t rsvd2[15];
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/* USB OTG Controller */
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uint32_t otgcsr;/* 0x80: OTG Control Status Register */
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uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
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uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
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uint32_t rsvd3[13];
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uint32_t isr; /* 0xC0: Global Interrupt Status Register */
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uint32_t imr; /* 0xC4: Global Interrupt Mask Register */
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uint32_t rsvd4[14];
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/* USB Device Controller */
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uint32_t dev_ctrl;/* 0x100: Device Control Register */
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uint32_t dev_addr;/* 0x104: Device Address Register */
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uint32_t dev_test;/* 0x108: Device Test Register */
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uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
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uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
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uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
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uint32_t rsvd5[2];
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uint32_t cxfifo;/* 0x120: CX FIFO Register */
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uint32_t idle; /* 0x124: IDLE Counter Register */
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uint32_t ep0_data; /* 0x128: EP0 Setup Packet PIO Register */
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uint32_t rsvd6[1];
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uint32_t gimr; /* 0x130: Group Interrupt Mask Register */
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uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
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uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
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uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
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uint32_t gisr; /* 0x140: Group Interrupt Status Register */
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uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
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uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
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uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
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uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
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uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
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uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
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uint32_t rsvd7[1];
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uint32_t ep[15]; /* 0x160 - 0x19B: Endpoint Register */
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uint32_t rsvd8[3];
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uint32_t fifocfg0; /* 0x1a8: Buffer Configuration 0 Register */
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uint32_t fifocfg1; /* 0x1aC: Buffer Configuration 1 Register */
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uint32_t fifocsr[4]; /* 0x1b0 - 0x1bf: FIFO Control Status Register */
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uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
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uint32_t rsvd9[1];
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uint32_t dma_ctrl; /* 0x1c8: DMA0 Control Register */
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uint32_t dma_addr; /* 0x1cc: DMA0 Address Register */
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uint32_t rsvd10[1];
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uint32_t dma0_status; /* 0x1d4: DMA0 Controller Status Register */
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uint32_t dma1_status; /* 0x1d8: DMA1 Controller Status Register */
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uint32_t dma2_status; /* 0x1dc: DMA2 Controller Status Register */
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uint32_t dma3_status; /* 0x1e0: DMA3 Controller Status Register */
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uint32_t dma4_status; /* 0x1e4: DMA4 Controller Status Register */
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uint32_t rsvd11[6];
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uint32_t dma0_ctrl; /* 0x200: DMA1 Control Register */
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uint32_t dma0_addr; /* 0x204: DMA1 Address Register */
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uint32_t dma1_ctrl; /* 0x208: DMA2 Control Register */
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uint32_t dma1_addr; /* 0x20C: DMA2 Address Register */
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uint32_t dma2_ctrl; /* 0x210: DMA3 Control Register */
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uint32_t dma2_addr; /* 0x214: DMA3 Address Register */
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uint32_t dma3_ctrl; /* 0x218: DMA4 Control Register */
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uint32_t dma3_addr; /* 0x21C: DMA4 Address Register */
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};
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struct nvt_udc_ext_regs {
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/* USB Host Controller */
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struct {
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uint32_t data[4];
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} hccr; /* 0x00 - 0x0f: hccr */
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struct {
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uint32_t data[9];
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} hcor; /* 0x10 - 0x33: hcor */
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uint32_t rsvd1[3];
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uint32_t miscr; /* 0x40: Miscellaneous Register */
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uint32_t rsvd2[15];
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/* USB OTG Controller */
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uint32_t otgcsr;/* 0x80: OTG Control Status Register */
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uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
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uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
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uint32_t rsvd3[13];
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uint32_t isr; /* 0xC0: Global Interrupt Status Register */
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uint32_t imr; /* 0xC4: Global Interrupt Mask Register */
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uint32_t rsvd4[14];
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/* USB Device Controller */
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uint32_t dev_ctrl;/* 0x100: Device Control Register */
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uint32_t dev_addr;/* 0x104: Device Address Register */
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uint32_t dev_test;/* 0x108: Device Test Register */
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uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
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uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
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uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
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uint32_t rsvd5[2];
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uint32_t cxfifo;/* 0x120: CX FIFO Register */
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uint32_t idle; /* 0x124: IDLE Counter Register */
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uint32_t ep0_data; /* 0x128: EP0 Setup Packet PIO Register */
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uint32_t rsvd6[1];
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uint32_t gimr; /* 0x130: Group Interrupt Mask Register */
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uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
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uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
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uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
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uint32_t gisr; /* 0x140: Group Interrupt Status Register */
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uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
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uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
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uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
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uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
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uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
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uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
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uint32_t rsvd7[1];
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uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
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uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
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uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
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uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
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uint32_t fifomap;/* 0x1a8: FIFO Map Register */
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uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
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uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
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uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
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uint32_t rsvd8[1];
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uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
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uint32_t dma_addr; /* 0x1cc: DMA Address Register */
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#ifdef CONFIG_USB_GADGET_CXSETUP_DMA
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uint32_t ep0_setup_data; /* 0x1d0: EP0 Setup Packet PIO Register */
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#endif
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};
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/* Miscellaneous Register */
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#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */
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#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */
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#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */
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#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
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/* OTG Control Status Register */
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#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */
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#define OTGCSR_SPD_LOW (1 << 22)
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#define OTGCSR_SPD_FULL (0 << 22)
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#define OTGCSR_SPD_MASK (3 << 22)
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#define OTGCSR_SPD_SHIFT 22
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#define OTGCSR_SPD(x) (((x) >> 22) & 0x03)
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#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */
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#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */
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#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */
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#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */
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#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */
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#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */
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#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */
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#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */
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#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/
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#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/
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#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/
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#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/
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#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/
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#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/
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#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */
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#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */
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#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */
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#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */
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#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */
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#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */
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#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */
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#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */
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#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */
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/* OTG Interrupt Status Register */
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#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */
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#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */
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#define OTGISR_OVD (1 << 10) /* over-current detected */
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#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */
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#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */
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#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */
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#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */
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#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */
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#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */
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/* OTG Interrupt Enable Register */
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#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */
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#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */
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#define OTGIER_OVD (1 << 10) /* over-current detected */
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#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */
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#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */
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#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */
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#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */
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#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */
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#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */
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/* Global Interrupt Status Register (W1C) */
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#define ISR_HOST (1 << 2) /* USB Host interrupt */
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#define ISR_OTG (1 << 1) /* USB OTG interrupt */
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#define ISR_DEV (1 << 0) /* USB Device interrupt */
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#define ISR_MASK 0x07
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/* Global Interrupt Mask Register */
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#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */
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#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */
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#define IMR_HOST (1 << 2) /* USB Host interrupt */
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#define IMR_OTG (1 << 1) /* USB OTG interrupt */
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#define IMR_DEV (1 << 0) /* USB Device interrupt */
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#define IMR_MASK 0x0f
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/* Device Control Register */
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#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */
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#define DEVCTRL_HS (1 << 6) /* High Speed Mode */
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#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */
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#define DEVCTRL_EN (1 << 5) /* Chip Enable */
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#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */
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#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */
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#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */
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#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */
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#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */
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/* Device Address Register */
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#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */
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#define DEVADDR_ADDR(x) ((x) & 0x7f)
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#define DEVADDR_ADDR_MASK 0x7f
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/* Device Test Register */
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#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */
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#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */
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#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */
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#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */
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#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */
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#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */
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#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */
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/* SOF Frame Number Register */
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#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
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#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */
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/* SOF Mask Timer Register */
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#define SOFMTR_TMR(x) ((x) & 0xffff)
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/* PHY Test Mode Selector Register */
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#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */
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#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */
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#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */
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#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */
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#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */
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/* CX FIFO Register */
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#define CXFIFO_DATA_EN (1 << 31) /* CX_DATAPORT_EN */
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#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */
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#define CXFIFO_FIFOE(x) (1 << (((x) & 0xff) + 8)) /* EPx FIFO empty */
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#define CXFIFO_FIFOE_FIFO0 (1 << 8)
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#define CXFIFO_FIFOE_FIFO1 (1 << 9)
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#define CXFIFO_FIFOE_FIFO2 (1 << 10)
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#define CXFIFO_FIFOE_FIFO3 (1 << 11)
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#define CXFIFO_FIFOE_MASK (0xff << 8)
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#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */
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#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */
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#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */
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#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */
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#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */
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#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */
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#define EP0_PACKET_SIZE 64
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#define CXFIFO_EXT_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */
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#define CXFIFO_EXT_FIFOE_MASK (0x0f << 8)
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/* IDLE Counter Register */
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#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */
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/* Group Interrupt Mask(Disable) Register */
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#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */
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#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */
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#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */
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#define GIMR_MASK 0x07
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/* Group Interrupt Mask(Disable) Register 0 (CX) */
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#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */
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#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */
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#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */
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#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
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#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
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#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
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#define GIMR0_MASK 0x3f
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/* Group Interrupt Mask(Disable) Register 1 (FIFO) */
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#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */
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#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x)
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#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */
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#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */
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#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x))
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#define GIMR1_MASK 0xffffff
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#define GIMR1_EXT_MASK 0xf00ff
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/* Group Interrupt Mask(Disable) Register 2 (Device) */
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#define GIMR2_WAKEUP (1 << 14) /* Device waked up */
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#define GIMR2_IDLE (1 << 13) /* Device idle */
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#define GIMR2_DMA5FIN (1 << 12) /* DMA 5 finished */
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#define GIMR2_DMA4FIN (1 << 11) /* DMA 4 finished */
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#define GIMR2_DMA3FIN (1 << 10) /* DMA 3 finished */
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#define GIMR2_DMA2FIN (1 << 9) /* DMA 2 finished */
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#define GIMR2_DMA1FIN (1 << 8) /* DMA 1 finished */
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#define GIMR2_DMA0FIN (1 << 7) /* DMA 0 finished */
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#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
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#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
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#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
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#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
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#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */
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#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
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#define GIMR2_RESET (1 << 0) /* Reset Interrupt */
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#define GIMR2_MASK 0x3ffff
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#define GIMR2_EXT_WAKEUP (1 << 10) /* Device waked up */
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#define GIMR2_EXT_IDLE (1 << 9) /* Device idle */
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#define GIMR2_EXT_DMAERR (1 << 8) /* DMA error */
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#define GIMR2_EXT_DMAFIN (1 << 7) /* DMA finished */
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#define GIMR2_EXT_MASK 0x7ff
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/* Group Interrupt Status Register */
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#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */
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#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */
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#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */
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/* Group Interrupt Status Register 0 (CX) */
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#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */
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#define GISR0_CXERR (1 << 4) /* CX command error interrupt */
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#define GISR0_CXEND (1 << 3) /* CX command end interrupt */
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#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
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#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
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#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
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/* Group Interrupt Status Register 1 (FIFO) */
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#define GISR1_IN_FIFO(x) (1 << (((x) & 0x0f) + 16)) /* FIFOx IN */
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#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x0f) * 2)) /* FIFOx OUT */
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#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x0f) * 2 + 1)) /* FIFOx SPK */
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#define GISR1_RX_FIFO(x) (3 << (((x) & 0x0f) * 2)) /* FIFOx OUT/SPK */
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#define GISR1_EXT_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */
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#define GISR1_EXT_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */
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#define GISR1_EXT_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */
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#define GISR1_EXT_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */
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/* Group Interrupt Status Register 2 (Device) */
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#define GISR2_WAKEUP (1 << 14) /* Device waked up */
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#define GISR2_IDLE (1 << 13) /* Device idle */
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#define GISR2_DMA5FIN (1 << 12) /* DMA finished */
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#define GISR2_DMA4FIN (1 << 11) /* DMA finished */
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#define GISR2_DMA3FIN (1 << 10) /* DMA finished */
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#define GISR2_DMA2FIN (1 << 9) /* DMA finished */
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#define GISR2_DMAERR (1 << 8) /* DMA error */
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#define GISR2_DMA0FIN (1 << 7) /* DMA finished */
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#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
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#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
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#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
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#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
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#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */
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#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
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#define GISR2_RESET (1 << 0) /* Reset Interrupt */
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#define GISR2_EXT_WAKEUP (1 << 10) /* Device waked up */
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#define GISR2_EXT_IDLE (1 << 9) /* Device idle */
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#define GISR2_EXT_DMAERR (1 << 8) /* DMA error */
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#define GISR2_EXT_DMAFIN (1 << 7) /* DMA finished */
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/* Receive Zero-Length-Packet Register */
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#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
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/* Transfer Zero-Length-Packet Register */
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#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
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/* ISOC Error/Abort Status Register */
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#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
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/* Endpoint Register */
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#define EP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */
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#define EP_TNRHB(x) (((x) & 0x03) << 13) \
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/* Transaction Number for High-Bandwidth EP(ISOC) */
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#define EP_RESET (1 << 12) /* Reset Toggle Sequence */
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#define EP_STALL (1 << 11) /* Stall */
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#define EP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
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/* IN Endpoint Register */
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#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */
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#define IEP_TNRHB(x) (((x) & 0x03) << 13) \
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/* Transaction Number for High-Bandwidth EP(ISOC) */
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#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */
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#define IEP_STALL (1 << 11) /* Stall */
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#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
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/* OUT Endpoint Register */
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#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */
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#define OEP_STALL (1 << 11) /* Stall */
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#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
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/* Endpoint Map Register (EP1 ~ EP4) */
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#define EPMAP14_SET_IN(ep, fifo) \
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((fifo) & 3) << (((ep) - 1) << 3 + 0)
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#define EPMAP14_SET_OUT(ep, fifo) \
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((fifo) & 3) << (((ep) - 1) << 3 + 4)
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#define EPMAP14_SET(ep, in, out) \
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do { \
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EPMAP14_SET_IN(ep, in); \
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EPMAP14_SET_OUT(ep, out); \
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} while (0)
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#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
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/* Endpoint Map Register (EP5 ~ EP8) */
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#define EPMAP58_SET_IN(ep, fifo) \
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((fifo) & 3) << (((ep) - 5) << 3 + 0)
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#define EPMAP58_SET_OUT(ep, fifo) \
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((fifo) & 3) << (((ep) - 5) << 3 + 4)
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#define EPMAP58_SET(ep, in, out) \
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do { \
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EPMAP58_SET_IN(ep, in); \
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EPMAP58_SET_OUT(ep, out); \
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} while (0)
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#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */
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/* FIFO Map Register */
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#define FIFOMAP_BIDIR (2 << 4)
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#define FIFOMAP_IN (1 << 4)
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#define FIFOMAP_OUT (0 << 4)
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#define FIFOMAP_DIR_MASK 0x30
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#define FIFOMAP_EP(x) ((x) & 0x0f)
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#define FIFOMAP_EP_MASK 0x0f
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#define FIFOMAP_CFG_MASK 0x3f
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#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
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#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
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#define FIFOCFG_EXT_EN (1 << 5)
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#define FIFOCFG_EXT_CFG_MASK 0x3f
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#define FIFOCFG_EXT(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
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/* Buffer Map Register */
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#define BUFFERMAP_BIDIR (2 << 5)
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#define BUFFERMAP_IN (1 << 5)
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#define BUFFERMAP_OUT (0 << 5)
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#define BUFFERMAP_DIR_MASK 0x60
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/* FIFO Configuration Register */
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#define FIFOCFG_EN (1 << 7)
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#define FIFOCFG_BLKSZ_1024 (1 << 4)
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#define FIFOCFG_BLKSZ_512 (0 << 4)
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#define FIFOCFG_3BLK (2 << 2)
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#define FIFOCFG_2BLK (1 << 2)
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#define FIFOCFG_1BLK (0 << 2)
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#define FIFOCFG_NBLK_MASK 3
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#define FIFOCFG_NBLK_SHIFT 2
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#define FIFOCFG_INTR (3 << 0)
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#define FIFOCFG_BULK (2 << 0)
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#define FIFOCFG_ISOC (1 << 0)
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#define FIFOCFG_RSVD (0 << 0) /* Reserved */
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#define FIFOCFG_TYPE_MASK 3
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#define FIFOCFG_TYPE_SHIFT 0
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#define FIFOCFG_CFG_MASK 0xff
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#define FIFOCFG(fifo, cfg) (((cfg) & 0xff) << (((fifo) & 3) << 3))
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#define FIFOCFG_DIR(fifo, dir) (((dir) & 0x3f) << (fifo*8 + 5))
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/* FIFO Control Status Register */
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#define FIFOCSR_RESET ((1 << 12) | (1 << 28)) /* FIFO Reset */
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#define FIFOCSR_EVEN_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for EVEN OUT-EP/FIFO */
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#define FIFOCSR_ODD_BYTES(x) (((x) >> 16) & 0x7ff) /* Length(bytes) for ODD OUT-EP/FIFO */
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#define FIFOCSR_EXT_RESET (1 << 12) /* FIFO Reset */
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#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */
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/* DMA Target FIFO Register */
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#ifdef CONFIG_USB_GADGET_CXSETUP_DMA
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#define DMAFIFO_CX_NO 0x10
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#define DMAFIFO_CX (1 << 16) /* DMA FIFO = CX FIFO */
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#define DMAFIFO_FIFO(x) (1 << ((x) & 0x1f)) /* DMA FIFO = FIFOx */
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#else
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#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */
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#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */
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#endif
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/* DMA Control Register */
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#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */
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#define DMACTRL_LEN_SHIFT 8
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#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */
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#define DMACTRL_ABORT (1 << 3) /* DMA abort */
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#define DMACTRL_IO2IO (1 << 2) /* IO to IO */
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#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */
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#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */
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#define DMACTRL_START (1 << 0) /* DMA start */
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#endif
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