418 lines
11 KiB
C
Executable File
418 lines
11 KiB
C
Executable File
/**
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Clock info
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@file clock.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/IOAddress.h>
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#include <asm/arch/hardware.h>
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#include <asm/nvt-common/nvt_types.h>
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#include <asm/nvt-common/nvt_common.h>
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#include <asm/nvt-common/rcw_macro.h>
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#define SYSTEM_CLOCK_RATE_OFS 0x10
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#define CPU_CLOCK_RATE_RATIO0_OFS (0x4000 + 0x400 + 0x20)
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#define CPU_CLOCK_RATE_RATIO1_OFS (0x4000 + 0x400 + 0x24)
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#define CPU_CLOCK_RATE_RATIO2_OFS (0x4000 + 0x400 + 0x28)
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#define DMA_CLOCK_RATE_RATIO0_OFS (0x4000 + 0x480 + 0x20)
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#define DMA_CLOCK_RATE_RATIO1_OFS (0x4000 + 0x480 + 0x24)
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#define DMA_CLOCK_RATE_RATIO2_OFS (0x4000 + 0x480 + 0x28)
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#define PLL_CPU_NO 8 //No. of CPU's PLL = 8
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#define PLL_CLKSEL_CPU 0
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#define PLL_CLKSEL_CPU_80 (0x00 << PLL_CLKSEL_CPU) //< Select CPU clock 80MHz
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#define PLL_CLKSEL_CPU_PLL8 (0x01 << PLL_CLKSEL_CPU) //< Select CPU clock PLL8 (for CPU)
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#define PLL_CLKSEL_CPU_480 (0x02 << PLL_CLKSEL_CPU) //< Select CPU clock 480MHz
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#define PLL_CLKSEL_CPUMASK 0x3
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inline void apll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (APLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 apll_get_data(u8 offset)
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{
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return 0;
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}
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#if 0
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inline void apll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(APLL_PAGE_0_EN, (APLL_PAGE_EN_ADDR));
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}
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else if (PLL_PAGE_B == page) {
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writel(APLL_PAGE_B_EN, (APLL_PAGE_EN_ADDR));
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}
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else {
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/* ignore */
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}
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}
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#endif
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inline void mpll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 mpll_get_data(u8 offset)
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{
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return 0;
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#if 0
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return readl((MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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#if 0
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inline void mpll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(MPLL_PAGE_0_EN, (MPLL_PAGE_EN_ADDR));
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}
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else if (PLL_PAGE_B == page) {
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writel(MPLL_PAGE_B_EN, (MPLL_PAGE_EN_ADDR));
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}
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else {
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/* ignore */
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}
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}
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#endif
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void set_sys_mpll(unsigned long off, unsigned long val)
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{
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#if 0
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val <<= 17; val /= 12;
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mpll_enable(PLL_PAGE_B);
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mpll_set_data((off + 0), ((val >> 0) & 0xff));
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mpll_set_data((off + 1), ((val >> 8) & 0xff));
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mpll_set_data((off + 2), ((val >> 16) & 0xff));
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#endif
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}
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unsigned long get_sys_mpll(unsigned long off)
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{
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#if 0
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unsigned long val;
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mpll_enable(PLL_PAGE_B);
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val = mpll_get_data(off);
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val |= (mpll_get_data((off + 1)) << 8);
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val |= (mpll_get_data((off + 2)) << 16);
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val *= 12;val += ((1UL << 17) - 1); val >>= 17;
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return val;
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#endif
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return 0;
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}
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void set_cpu_clk(unsigned long freq)
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{
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/* no implement */
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}
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unsigned long get_cpu_clk(void)
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{
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unsigned int cpu_clk_sel = 0;
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#ifndef CONFIG_NVT_FPGA_EMULATION
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unsigned int cpu_freq_ratio;
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unsigned int cpu_freq_ratio0, cpu_freq_ratio1, cpu_freq_ratio2;
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#endif
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cpu_clk_sel = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS) & 0x3;
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if (cpu_clk_sel == 1) {
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#ifdef CONFIG_NVT_FPGA_EMULATION
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return 24000;
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#else
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// 0xF0020000 + (0x4000 + 0x400 + 0x20) = 0xF0024400 + 0x20
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cpu_freq_ratio0 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO0_OFS);
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// 0xF0020000 + (0x4000 + 0x400 + 0x24) = 0xF0024400 + 0x24
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cpu_freq_ratio1 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO1_OFS);
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// 0xF0020000 + (0x4000 + 0x400 + 0x28) = 0xF0024400 + 0x28
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cpu_freq_ratio2 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO2_OFS);
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cpu_freq_ratio = cpu_freq_ratio0 | (cpu_freq_ratio1 << 8) | \
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(cpu_freq_ratio2 << 16);
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return (12*cpu_freq_ratio / 131072) * 1000;
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#endif
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} else if (cpu_clk_sel == 2)
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return 480000;
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else
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return 80000;
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}
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#ifdef CONFIG_NVT_FPGA_EMULATION
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#define CALCULATE_CPU_FREQ_UNIT_US 100000
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#define timer_gettick() readl(IOADDR_TIMER_REG_BASE + 0x108) * (10)
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#else
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#define CALCULATE_CPU_FREQ_UNIT_US 100000
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#define timer_gettick() readl(IOADDR_TIMER_REG_BASE + 0x108)
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#endif
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#define read_PMCR() \
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({ \
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unsigned long cfg; \
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__asm__ __volatile__(\
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"mrc p15, 0, %0, c9, c12, 0\n\t" \
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: "=r"(cfg) \
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);\
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cfg;\
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})
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#define write_PMCR(m)\
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({\
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__asm__ __volatile__("mcr p15, 0, %0, c9, c12, 0" : : "r" (m));\
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})
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static BOOL cpu_count_open = FALSE;
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void timer2_delay(u32 us)
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{
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u32 start, end;
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start = timer_gettick();
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/*check timer count to target level*/
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while (1) {
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end = timer_gettick();
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if((end - start) > us)
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break;
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}
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}
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void ca53_cycle_count_start(BOOL do_reset, BOOL enable_divider)
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{
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/* in general enable all counters (including cycle counter)*/
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int value = 1;
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if (cpu_count_open == TRUE) {
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printf("cpu count start already\r\n");
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return;
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}
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cpu_count_open = TRUE;
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if (do_reset) {
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value |= 2; /* reset all counters to zero.*/
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value |= 4; /* reset cycle counter to zero.*/
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}
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if (enable_divider) {
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value |= 8; /* enable "by 64" divider for CCNT.*/
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}
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value |= 16;
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/* program the performance-counter control-register: */
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asm volatile("MCR p15, 0, %0, c9, c12, 0\t\n" :: "r"(value));
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/* enable all counters: */
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asm volatile("MCR p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f));
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/* clear overflows: */
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asm volatile("MCR p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f));
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return;
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}
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/**
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CA53 get CPU clock cycle count
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get CPU clock cycle count
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@param[out] type
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@return success or not
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- @b UINT64: clock cycle of CPU
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*/
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u32 ca53_get_cycle_count(void)
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{
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unsigned int value;
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__asm__ __volatile__("mrc p15, 0, %0, c9, c13, 0\n\t"
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: "=r"(value)
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);
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return value;
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}
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void ca53_cycle_count_stop(void)
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{
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u32 pmcr_reg;
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if (cpu_count_open == FALSE) {
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printf("cpu count not start yet\r\n");
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return;
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}
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cpu_count_open = FALSE;
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pmcr_reg = read_PMCR();
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pmcr_reg &= ~(0x1 << 0); /*E*/
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pmcr_reg &= ~(0x1 << 5); /*DP increase each clock cycle*/
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write_PMCR(pmcr_reg);
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return;
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}
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int do_nvt_cpu_get_freq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 /*test, */freq;
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u32 time_1, time_2, temp, time_interval;
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ca53_cycle_count_start(TRUE, FALSE);
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//for (test = 1; test <= 1; test ++) {
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time_1 = ca53_get_cycle_count();
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timer2_delay(CALCULATE_CPU_FREQ_UNIT_US);
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time_2 = ca53_get_cycle_count();
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if (time_2 > time_1) {
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time_interval = (time_2 - time_1);
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} else {
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temp = 0xFFFFFFFF - time_1;
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time_interval = temp + time_2;
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}
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freq = (time_interval) /(CALCULATE_CPU_FREQ_UNIT_US);
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//}
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ca53_cycle_count_stop();
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if(nvt_get_chip_id() == CHIP_NA51089) {
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printf("CHIP[NA51089] =>");
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} else {
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printf("CHIP[un-know] =>");
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}
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printf("CPU Freq %d MHz\n", freq);
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return 0;
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}
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U_BOOT_CMD(
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nvt_get_cpu_freq, 2, 1, do_nvt_cpu_get_freq,
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"get cpu freq",
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"[MHz]\n"
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);
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int do_nvt_cpu_freq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 uiReg;
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u32 value = simple_strtoul(argv[1], NULL, 10);
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switch (argc) {
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case 2:
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switch (value) {
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case 480:
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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if((uiReg & PLL_CLKSEL_CPUMASK) == PLL_CLKSEL_CPU_480) {
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printf("Already 480MHz\n");
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break;
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} else if((uiReg & PLL_CLKSEL_CPUMASK) == PLL_CLKSEL_CPU_PLL8) {
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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uiReg &= ~PLL_CLKSEL_CPUMASK;
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uiReg |= PLL_CLKSEL_CPU_480;
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writel(uiReg, (IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS));
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writel(0x34, (IOADDR_CG_REG_BASE + 0xA0));
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while (!(readl(IOADDR_CG_REG_BASE + 0xA0) & (1 << 3)));
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writel(0x28, (IOADDR_CG_REG_BASE + 0xA0));
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printf("Set CPU clk 480MHz\n");
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//CPU original = PLL8 => disable it
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uiReg = readl(IOADDR_CG_REG_BASE);
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if((uiReg & (1<<PLL_CPU_NO))==(1<<PLL_CPU_NO)) {
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printf("PLL8 = Enabled => Disable it\n");
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uiReg &= ~(1<<PLL_CPU_NO);
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writel(uiReg, IOADDR_CG_REG_BASE); // B0
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uiReg = readl(IOADDR_CG_REG_BASE);
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printf("PLL8 = 0x%08x \n", uiReg);
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}
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}
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break;
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default:
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printf("Not define this CPU Freq %d, use defualt value 960!\n", value);
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case 960:
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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if((uiReg & PLL_CLKSEL_CPUMASK) != PLL_CLKSEL_CPU_PLL8) {
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uiReg = readl(IOADDR_CG_REG_BASE);
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if((uiReg & (1<<PLL_CPU_NO))!=(1<<PLL_CPU_NO)) {
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printf("PLL8 = Disabled => Enable it\n");
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uiReg |= (1<<PLL_CPU_NO);
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writel(uiReg, IOADDR_CG_REG_BASE); // B0
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uiReg = readl(IOADDR_CG_REG_BASE);
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//Polling PLL8
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while (!(readl(IOADDR_CG_REG_BASE + 0x04) & (1 << 8)));
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printf("PLL8 enable done= 0x%08x 0x%08x\n", readl(IOADDR_CG_REG_BASE + 0x00), readl(IOADDR_CG_REG_BASE + 0x04));
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}
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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uiReg &= ~PLL_CLKSEL_CPUMASK;
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uiReg |= PLL_CLKSEL_CPU_PLL8;
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writel(uiReg, (IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS));
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writel(0x34, (IOADDR_CG_REG_BASE + 0xA0));
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while (!(readl(IOADDR_CG_REG_BASE + 0xA0) & (1 << 3)));
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writel(0x28, (IOADDR_CG_REG_BASE + 0xA0));
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}
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//CPU 960 MHz -> 0xA00000
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writel(0x00, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO0_OFS); // B0
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writel(0x00, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO1_OFS); // B1
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writel(0xA0, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO2_OFS); // B2
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printf("Set CPU clk 960MHz\n");
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break;
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}
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break;
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default:
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printf("CPU:%d => type nvt_cpu_freq <freq>\n", (int)get_cpu_clk());
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(
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nvt_cpu_freq, 2, 1, do_nvt_cpu_freq,
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"change cpu freq",
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"[MHz]\n"
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"nvt_cpu_freq 480/960(56x)\n"
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);
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int do_nvt_ddr_freq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int freq_ratio;
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unsigned int freq_ratio0, freq_ratio1, freq_ratio2;
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freq_ratio0 = readl(IOADDR_CG_REG_BASE + \
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DMA_CLOCK_RATE_RATIO0_OFS);
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freq_ratio1 = readl(IOADDR_CG_REG_BASE + \
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DMA_CLOCK_RATE_RATIO1_OFS);
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freq_ratio2 = readl(IOADDR_CG_REG_BASE + \
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DMA_CLOCK_RATE_RATIO2_OFS);
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freq_ratio = freq_ratio0 | (freq_ratio1 << 8) | \
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(freq_ratio2 << 16);
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printf("DMA clock rate = %d => [%d]MHz\r\n", ((12*freq_ratio / 131072)<<2), ((12*freq_ratio / 131072)<<1));
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return 0;
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}
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U_BOOT_CMD(
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nvt_get_ddr_freq, 2, 1, do_nvt_ddr_freq,
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"get ddr freq/type\n",
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"\n"
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); |