155 lines
3.0 KiB
C
Executable File
155 lines
3.0 KiB
C
Executable File
/**
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Clock info
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@file clock.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/IOAddress.h>
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#define CG_CPU_CKCTRL_REG_OFFSET 0x100
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#define CPU_CLK_SEL_CPU_APLL 0x80000000
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#define CPU_CLOCK_RATE_RATIO0_OFS 0x107E0
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#define CPU_CLOCK_RATE_RATIO1_OFS 0x107E4
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#define CPU_CLOCK_RATE_RATIO2_OFS 0x107E8
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inline void apll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (APLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 apll_get_data(u8 offset)
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{
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return 0;
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}
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#if 0
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inline void apll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(APLL_PAGE_0_EN, (APLL_PAGE_EN_ADDR));
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}
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else if (PLL_PAGE_B == page) {
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writel(APLL_PAGE_B_EN, (APLL_PAGE_EN_ADDR));
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}
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else {
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/* ignore */
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}
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}
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#endif
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inline void mpll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 mpll_get_data(u8 offset)
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{
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return 0;
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#if 0
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return readl((MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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#if 0
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inline void mpll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(MPLL_PAGE_0_EN, (MPLL_PAGE_EN_ADDR));
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}
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else if (PLL_PAGE_B == page) {
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writel(MPLL_PAGE_B_EN, (MPLL_PAGE_EN_ADDR));
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}
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else {
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/* ignore */
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}
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}
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#endif
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void set_sys_mpll(unsigned long off, unsigned long val)
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{
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#if 0
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val <<= 17; val /= 12;
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mpll_enable(PLL_PAGE_B);
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mpll_set_data((off + 0), ((val >> 0) & 0xff));
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mpll_set_data((off + 1), ((val >> 8) & 0xff));
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mpll_set_data((off + 2), ((val >> 16) & 0xff));
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#endif
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}
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unsigned long get_sys_mpll(unsigned long off)
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{
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#if 0
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unsigned long val;
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mpll_enable(PLL_PAGE_B);
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val = mpll_get_data(off);
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val |= (mpll_get_data((off + 1)) << 8);
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val |= (mpll_get_data((off + 2)) << 16);
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val *= 12;val += ((1UL << 17) - 1); val >>= 17;
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return val;
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#endif
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return 0;
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}
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void set_cpu_clk(unsigned long freq)
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{
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/* no implement */
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}
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unsigned long get_cpu_clk(void)
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{
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#ifdef CONFIG_NVT_FPGA_EMULATION_CA9
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return 24000000;
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#else
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u32 cpu_clk_sel, cpu_clk = 0, pll16_clk;
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unsigned int cpu_freq_ratio0, cpu_freq_ratio1, cpu_freq_ratio2;
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cpu_clk_sel = readl(IOADDR_CG_REG_BASE + CG_CPU_CKCTRL_REG_OFFSET) & 0x80000000;
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switch (cpu_clk_sel) {
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case CPU_CLK_SEL_CPU_APLL: {
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cpu_freq_ratio0 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO0_OFS);
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cpu_freq_ratio1 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO1_OFS);
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cpu_freq_ratio2 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO2_OFS);
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pll16_clk = (cpu_freq_ratio0 & 0xFF) | ((cpu_freq_ratio1 && 0xFF) << 8) | \
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((cpu_freq_ratio2 & 0xFF) << 16);
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pll16_clk = (12 * pll16_clk / 131072) * 1000;
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cpu_clk = pll16_clk * 8;
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break;
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}
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default:
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cpu_clk = 80000000;
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break;
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}
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return cpu_clk;
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#endif
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}
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