309 lines
11 KiB
C
Executable File
309 lines
11 KiB
C
Executable File
/*
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* Copyright (C) 2016 Novatek Microelectronics Corp. All rights reserved.
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* Author: iVoT-IM <iVoT_MailGrp@novatek.com.tw>
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*
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* Configuration settings for the Novatek NA51055 SOC.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_NA51055_H
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#define __CONFIG_NA51055_H
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#include <linux/sizes.h>
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/*#define CONFIG_DEBUG 1 */
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#ifdef CONFIG_DEBUG
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#define DEBUG 1
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#endif
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/*#define CONFIG_NVT_FW_UPDATE_LED*/
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/*#define CONFIG_NVT_PWM*/
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_SYS_NAND_BASE 0xF0400000
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#define CONFIG_SYS_HZ 1000
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//#define CONFIG_USE_ARCH_MEMCPY
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//#define CONFIG_USE_ARCH_MEMSET
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/*RTC Default Date*/
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#define RTC_YEAR 2000
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#define RTC_MONTH 1
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#define RTC_DAY 1
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/*-----------------------------------------------------------------------
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* IP address configuration
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*/
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#ifdef CONFIG_NOVATEK_MAC_ENET
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#define CONFIG_ETHNET
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#endif
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#define FIXED_ETH_PARAMETER
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#ifdef FIXED_ETH_PARAMETER
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#ifdef CONFIG_ETHNET
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#define CONFIG_ETHADDR {0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x01}
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#define CONFIG_IPADDR 192.168.1.99 /* Target IP address */
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.1.11 /* Server IP address */
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#define CONFIG_GATEWAYIP 192.168.1.254
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#define CONFIG_HOSTNAME "soclnx"
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#endif
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#endif
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#define ETH_PHY_HW_RESET
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#define NVT_PHY_RST_PIN D_GPIO(1)
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/*-----------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------
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* NVT LED CONFIG
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*
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* LED GPIO selection
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* C_GPIO(x)
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* P_GPIO(x)
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* S_GPIO(x)
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* L_GPIO(x)
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* D_GPIO(x)
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* Duration Unit: ms
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*/
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#ifdef CONFIG_NVT_FW_UPDATE_LED
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#ifdef CONFIG_NVT_PWM
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#define PWM_SIGNAL_NORMAL 0
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#define PWM_SIGNAL_INVERT 1
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#define NVT_PWMLED (PWMID_0 | PWMID_1)
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#define PWM_SIGNAL_TYPE PWM_SIGNAL_INVERT
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#define PWM_LED_ERASE 50
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#define PWM_LED_PROGRAM 5
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#else
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#define NVT_LED_PIN P_GPIO(12)
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#define NVT_LED_ERASE_DURATION 30
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#define NVT_LED_PROGRAM_DURATION 10
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#endif
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#endif
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#ifdef CONFIG_USB_GADGET_NVTIVOT
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#define CONFIG_USBD_HS
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#endif
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/*
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* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
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* we say (for simplicity) that we have 1 bank, always, even when
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* we have more. We always start at 0x80000000, and we place the
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* initial stack pointer in our SRAM. Otherwise, we can define
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* CONFIG_NR_DRAM_BANKS before including this file.
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE CONFIG_MEM_SIZE /* DDR size 512MB */
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/*
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* To include nvt memory layout
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*/
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#include "novatek/na51055_ca9.h"
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#define CONFIG_SYS_SDRAM_BASE CONFIG_UBOOT_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE CONFIG_UBOOT_SDRAM_SIZE
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#define NVT_LINUX_BOOT_PARAM_ADDR (CONFIG_LINUX_SDRAM_BASE + 0x100)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_UBOOT_SDRAM_BASE + CONFIG_UBOOT_SDRAM_SIZE - 0x1000)
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/*
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* Our DDR memory always starts at 0x00000000 and U-Boot shall have
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* relocated itself to higher in memory by the time this value is used.
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* However, set this to a 32MB offset to allow for easier Linux kernel
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* booting as the default is often used as the kernel load address.
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*/
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LINUX_SDRAM_START
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#define CONFIG_STANDALONE_LOAD_ADDR 0x1A000000
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_CMD_MEMORY 1
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/* We set the max number of command args high to avoid HUSH bugs. */
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#define CONFIG_SYS_MAXARGS 64
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 1024
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* even with bootdelay=0 */
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/*#define CONFIG_AUTOBOOT_KEYED 1*/
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#define CONFIG_AUTOBOOT_STOP_STR "~"
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/* MMC */
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#define CONFIG_SUPPORT_EMMC_BOOT /* Support emmc boot partition */
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/* MTD */
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#define CONFIG_CMD_MTDPARTS 1
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#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
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#define CONFIG_LZMA /* required by uitron decompress */
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#define CONFIG_MTD_DEVICE
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#define CONFIG_SYS_BOOTM_LEN (25 << 20)
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/* ENV related config options */
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#if defined(_NVT_UBOOT_ENV_IN_STORG_SUPPORT_NAND_)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x002C0000 /* Defined by configs\cfg_gen\nvt-na51055-storage-partition.dtsi */
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#define CONFIG_ENV_SIZE (128 << 10) /* Unit: Block size: 128 KiB */
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#define CONFIG_ENV_RANGE 2 * CONFIG_ENV_SIZE /* Defined by configs\cfg_gen\nvt-na51055-storage-partition.dtsi */
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#elif defined(_NVT_UBOOT_ENV_IN_STORG_SUPPORT_NOR_)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x000B0000 /* It must be aligned to an erase secrote boundary */
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#define CONFIG_ENV_SIZE 0x00010000 /* Sync to configs\cfg_gen\nvt-na51055-storage-partition.dtsi */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* Define the SPI flash's sector size */
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#elif defined(_NVT_UBOOT_ENV_IN_STORG_SUPPORT_MMC_)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_OFFSET 0x002C0000
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#define CONFIG_ENV_SIZE 0x00040000
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#define CONFIG_SYS_MMC_ENV_DEV 2
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#else
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE (8 << 10)
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#endif
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#if (defined(CONFIG_CMD_DFU) && defined(_EMBMEM_EMMC_))
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#define CONFIG_DFU_MMC 1
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#define CONFIG_FS_EXT4 1
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#define CONFIG_EXT4_WRITE 1
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#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_LINUX_SDRAM_SIZE
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/* EMMC partition */
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#define DFU_ALT_INFO \
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"rootfs ext4 2 1;" \
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"rootfs1 fat 2 2;" \
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"rootfs2 ext4 2 3;" \
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"mbr1 mbr 2 4;" \
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"rootfsl1 part 2 5"
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#endif
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#if (defined(CONFIG_CMD_DFU) && defined(CONFIG_NVT_SPI_NAND))
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#define CONFIG_DFU_NAND 1
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#define CONFIG_DFU_NAND_TRIMFFS 1
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/* NAND partition */
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#define DFU_ALT_INFO \
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"fdt part 0 1;" \
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"uboot part 0 2;" \
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"uenv part 0 3;" \
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"linux part 0 4;" \
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"rootfs0 partubi 0 5;" \
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"rootfs1 partubi 0 6;" \
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"app partubi 0 7"
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#endif
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#if (defined(CONFIG_CMD_DFU) && defined(CONFIG_NVT_SPI_NOR))
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#define CONFIG_DFU_SF 1
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/* NOR partition */
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#define DFU_ALT_INFO \
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"fdt part 0 1;" \
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"uboot part 0 2;" \
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"uenv part 0 3;" \
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"linux part 0 4;" \
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"rootfs part 0 5;" \
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"app part 0 6"
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#endif
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#ifdef CONFIG_CMD_DFU
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#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x100000
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#define CONFIG_SET_DFU_ALT_INFO
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#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K)
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#define DFU_DEFAULT_POLL_TIMEOUT 3000
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#define CONFIG_USB_FUNCTION_DFU
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#define CONFIG_USB_CABLE_CHECK
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#define CONFIG_CMD_THOR_DOWNLOAD
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#define CONFIG_USB_FUNCTION_THOR
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#define CONFIG_THOR_RESET_OFF
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#if !defined(DFU_ALT_INFO)
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# define DFU_ALT_INFO
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#endif
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#endif
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_USE_BOOTARGS
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#define CONFIG_BOOTARGS_COMMON "earlyprintk console=ttyS0,115200 rootwait nprofile_irq_duration=on "
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/* NVT boot related setting */
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#ifdef CONFIG_NVT_IVOT_SOC_FW_UPDATE_SUPPORT
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#define CONFIG_NVT_LINUX_AUTODETECT /* Support for detect FW96680A.bin/FW96680T.bin automatically. (Only working on mtd device boot method) */
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#define CONFIG_NVT_BIN_CHKSUM_SUPPORT /* This option will check rootfs/uboot checksum info. during update image flow */
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#if defined(_NVT_ROOTFS_TYPE_RAMDISK_)
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/* the ramdisk dram base/size will be defined in itron modelext info. */
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "root=/dev/ram0 rootfstype=ramfs rdinit=/linuxrc "
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#if defined(_EMBMEM_EMMC_)
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/* For emmc device */
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#define CONFIG_NVT_LINUX_EMMC_BOOT
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#elif defined(_EMBMEM_SPI_NAND_)
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#define CONFIG_NVT_LINUX_SPINAND_BOOT
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/* For flash */
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#elif defined(_EMBMEM_SPI_NOR_)
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/* For spi nor device */
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#define CONFIG_NVT_LINUX_SPINOR_BOOT
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#endif
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#define CONFIG_NVT_LINUX_RAMDISK_SUPPORT
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#elif defined(_NVT_ROOTFS_TYPE_NAND_UBI_) /* UBIFS rootfs boot */
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#define CONFIG_NVT_LINUX_SPINAND_BOOT
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#define CONFIG_NVT_UBIFS_SUPPORT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "root=ubi0:rootfs rootfstype=ubifs ubi.fm_autoconvert=1 init=/linuxrc "
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#elif defined(_NVT_ROOTFS_TYPE_NAND_JFFS2_) /* JFFS2 rootfs boot */
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#define CONFIG_NVT_LINUX_SPINAND_BOOT /* Boot from spinand or spinor (Support FW96680A.bin update all-in-one) */
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#define CONFIG_NVT_JFFS2_SUPPORT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=jffs2 rw "
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#elif defined(_NVT_ROOTFS_TYPE_SQUASH_) /* Squashfs rootfs boot */
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#if defined(_EMBMEM_EMMC_)
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/* For emmc device */
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#define CONFIG_NVT_LINUX_EMMC_BOOT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=squashfs ro "
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#elif defined(_EMBMEM_SPI_NAND_)
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/* For spi nand device */
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#define CONFIG_NVT_LINUX_SPINAND_BOOT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "ubi.block=0,0 root=/dev/ubiblock0_0 rootfstype=squashfs init=/linuxrc "
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#else
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/* For spi nor device */
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#define CONFIG_NVT_LINUX_SPINOR_BOOT /* Boot from spinand or spinor (Support FW96680A.bin update all-in-one) */
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=squashfs ro "
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#endif
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#define CONFIG_NVT_SQUASH_SUPPORT
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#elif defined(_NVT_ROOTFS_TYPE_NOR_JFFS2_) /* JFFS2 rootfs boot */
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#define CONFIG_NVT_LINUX_SPINOR_BOOT /* Boot from spinand or spinor (Support FW96680A.bin update all-in-one) */
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#define CONFIG_NVT_JFFS2_SUPPORT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=jffs2 rw "
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#elif defined(_NVT_ROOTFS_TYPE_EXT4_)
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#define CONFIG_NVT_LINUX_EMMC_BOOT /* Boot from emmc (Support FW96680A.bin update all-in-one) */
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#define CONFIG_NVT_EXT4_SUPPORT
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "rootfstype=ext4 rw "
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#else
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#define CONFIG_NVT_LINUX_SD_BOOT /* To handle RAW SD boot (e.g. itron.bin, uImage.bin, uboot.bin...) itron.bin u-boot.bin dsp.bin dsp2.bin must be not compressed.*/
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON "root=/dev/mmcblk0p2 noinitrd rootfstype=ext3 init=/linuxrc "
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#endif /* _NVT_ROOTFS_TYPE_ */
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#else /* !CONFIG_NVT_IVOT_SOC_FW_UPDATE_SUPPORT */
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#define CONFIG_BOOTARGS CONFIG_BOOTARGS_COMMON
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#endif /* !CONFIG_NVT_IVOT_SOC_FW_UPDATE_SUPPORT */
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#define CONFIG_BOOTCOMMAND "nvt_boot"
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#endif /* __CONFIG_NA51055_H */
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