102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0] = {NONE, NONE, NONE, NONE},
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[1] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[2] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[3] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[4] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[5] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
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[12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[22] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[23] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[24] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[25] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[26] = {PCIE1, PCIE2, CPRI2, CPRI1},
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[27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
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[32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
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[33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
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[38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
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[43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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[47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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if (!(serdes1_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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if (serdes1_prtcl_map & (1 << NONE))
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return;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes1_prtcl_map |= (1 << NONE);
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}
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