401 lines
9.4 KiB
C
401 lines
9.4 KiB
C
/*
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MT7601U_H
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#define MT7601U_H
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/usb.h>
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#include <linux/completion.h>
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#include <net/mac80211.h>
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#include <linux/debugfs.h>
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#include <linux/average.h>
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#include "regs.h"
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#define MT_CALIBRATE_INTERVAL (4 * HZ)
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#define MT_FREQ_CAL_INIT_DELAY (30 * HZ)
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#define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ)
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#define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2)
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#define MT_BBP_REG_VERSION 0x00
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#define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */
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#define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */
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#define MT_RX_ORDER 3
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#define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER)
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struct mt7601u_dma_buf {
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struct urb *urb;
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void *buf;
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dma_addr_t dma;
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size_t len;
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};
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struct mt7601u_mcu {
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struct mutex mutex;
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u8 msg_seq;
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struct mt7601u_dma_buf resp;
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struct completion resp_cmpl;
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};
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struct mt7601u_freq_cal {
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struct delayed_work work;
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u8 freq;
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bool enabled;
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bool adjusting;
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};
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struct mac_stats {
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u64 rx_stat[6];
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u64 tx_stat[6];
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u64 aggr_stat[2];
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u64 aggr_n[32];
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u64 zero_len_del[2];
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};
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#define N_RX_ENTRIES 16
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struct mt7601u_rx_queue {
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struct mt7601u_dev *dev;
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struct mt7601u_dma_buf_rx {
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struct urb *urb;
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struct page *p;
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} e[N_RX_ENTRIES];
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unsigned int start;
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unsigned int end;
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unsigned int entries;
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unsigned int pending;
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};
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#define N_TX_ENTRIES 64
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struct mt7601u_tx_queue {
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struct mt7601u_dev *dev;
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struct mt7601u_dma_buf_tx {
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struct urb *urb;
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struct sk_buff *skb;
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} e[N_TX_ENTRIES];
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unsigned int start;
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unsigned int end;
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unsigned int entries;
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unsigned int used;
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unsigned int fifo_seq;
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};
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/* WCID allocation:
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* 0: mcast wcid
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* 1: bssid wcid
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* 1...: STAs
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* ...7e: group wcids
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* 7f: reserved
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*/
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#define N_WCIDS 128
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#define GROUP_WCID(idx) (N_WCIDS - 2 - idx)
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struct mt7601u_eeprom_params;
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#define MT_EE_TEMPERATURE_SLOPE 39
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#define MT_FREQ_OFFSET_INVALID -128
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enum mt_temp_mode {
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MT_TEMP_MODE_NORMAL,
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MT_TEMP_MODE_HIGH,
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MT_TEMP_MODE_LOW,
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};
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enum mt_bw {
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MT_BW_20,
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MT_BW_40,
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};
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enum {
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MT7601U_STATE_INITIALIZED,
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MT7601U_STATE_REMOVED,
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MT7601U_STATE_WLAN_RUNNING,
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MT7601U_STATE_MCU_RUNNING,
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MT7601U_STATE_SCANNING,
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MT7601U_STATE_READING_STATS,
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MT7601U_STATE_MORE_STATS,
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};
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DECLARE_EWMA(rssi, 10, 4);
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/**
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* struct mt7601u_dev - adapter structure
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* @lock: protects @wcid->tx_rate.
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* @mac_lock: locks out mac80211's tx status and rx paths.
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* @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS
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* flags in @state.
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* @rx_lock: protects @rx_q.
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* @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi.
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* @mutex: ensures exclusive access from mac80211 callbacks.
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* @vendor_req_mutex: protects @vend_buf, ensures atomicity of read/write
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* accesses
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* @reg_atomic_mutex: ensures atomicity of indirect register accesses
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* (accesses to RF and BBP).
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* @hw_atomic_mutex: ensures exclusive access to HW during critical
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* operations (power management, channel switch).
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*/
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struct mt7601u_dev {
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struct ieee80211_hw *hw;
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struct device *dev;
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unsigned long state;
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struct mutex mutex;
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unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG];
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struct cfg80211_chan_def chandef;
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struct ieee80211_supported_band *sband_2g;
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struct mt7601u_mcu mcu;
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struct delayed_work cal_work;
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struct delayed_work mac_work;
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struct workqueue_struct *stat_wq;
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struct delayed_work stat_work;
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struct mt76_wcid *mon_wcid;
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struct mt76_wcid __rcu *wcid[N_WCIDS];
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spinlock_t lock;
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spinlock_t mac_lock;
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const u16 *beacon_offsets;
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u8 macaddr[ETH_ALEN];
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struct mt7601u_eeprom_params *ee;
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struct mutex vendor_req_mutex;
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void *vend_buf;
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struct mutex reg_atomic_mutex;
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struct mutex hw_atomic_mutex;
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u32 rxfilter;
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u32 debugfs_reg;
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u8 out_eps[8];
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u8 in_eps[8];
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u16 out_max_packet;
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u16 in_max_packet;
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/* TX */
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spinlock_t tx_lock;
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struct tasklet_struct tx_tasklet;
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struct mt7601u_tx_queue *tx_q;
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struct sk_buff_head tx_skb_done;
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atomic_t avg_ampdu_len;
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/* RX */
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spinlock_t rx_lock;
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struct tasklet_struct rx_tasklet;
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struct mt7601u_rx_queue rx_q;
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/* Connection monitoring things */
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spinlock_t con_mon_lock;
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u8 ap_bssid[ETH_ALEN];
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s8 bcn_freq_off;
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u8 bcn_phy_mode;
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struct ewma_rssi avg_rssi;
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u8 agc_save;
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struct mt7601u_freq_cal freq_cal;
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bool tssi_read_trig;
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s8 tssi_init;
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s8 tssi_init_hvga;
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s16 tssi_init_hvga_offset_db;
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int prev_pwr_diff;
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enum mt_temp_mode temp_mode;
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int curr_temp;
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int dpd_temp;
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s8 raw_temp;
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bool pll_lock_protect;
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u8 bw;
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bool chan_ext_below;
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/* PA mode */
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u32 rf_pa_mode[2];
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struct mac_stats stats;
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};
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struct mt7601u_tssi_params {
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char tssi0;
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int trgt_power;
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};
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struct mt76_wcid {
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u8 idx;
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u8 hw_key_idx;
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u16 tx_rate;
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bool tx_rate_set;
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u8 tx_rate_nss;
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};
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struct mt76_vif {
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u8 idx;
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struct mt76_wcid group_wcid;
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};
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struct mt76_sta {
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struct mt76_wcid wcid;
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u16 agg_ssn[IEEE80211_NUM_TIDS];
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};
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struct mt76_reg_pair {
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u32 reg;
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u32 value;
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};
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struct mt7601u_rxwi;
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extern const struct ieee80211_ops mt7601u_ops;
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void mt7601u_init_debugfs(struct mt7601u_dev *dev);
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u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
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void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val);
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u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
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u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
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void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset,
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const void *data, int len);
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int mt7601u_wait_asic_ready(struct mt7601u_dev *dev);
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bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout);
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bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
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int timeout);
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/* Compatibility with mt76 */
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#define mt76_rmw_field(_dev, _reg, _field, _val) \
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mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
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static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset)
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{
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return mt7601u_rr(dev, offset);
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}
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static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val)
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{
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return mt7601u_wr(dev, offset, val);
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}
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static inline u32
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mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val)
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{
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return mt7601u_rmw(dev, offset, mask, val);
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}
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static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val)
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{
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return mt76_rmw(dev, offset, 0, val);
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}
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static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val)
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{
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return mt76_rmw(dev, offset, val, 0);
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}
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int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base,
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const struct mt76_reg_pair *data, int len);
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int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset,
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const u32 *data, int n);
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void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr);
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/* Init */
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struct mt7601u_dev *mt7601u_alloc_device(struct device *dev);
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int mt7601u_init_hardware(struct mt7601u_dev *dev);
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int mt7601u_register_device(struct mt7601u_dev *dev);
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void mt7601u_cleanup(struct mt7601u_dev *dev);
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int mt7601u_mac_start(struct mt7601u_dev *dev);
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void mt7601u_mac_stop(struct mt7601u_dev *dev);
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/* PHY */
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int mt7601u_phy_init(struct mt7601u_dev *dev);
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int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev);
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void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path);
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void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path);
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int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw);
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void mt7601u_agc_save(struct mt7601u_dev *dev);
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void mt7601u_agc_restore(struct mt7601u_dev *dev);
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int mt7601u_phy_set_channel(struct mt7601u_dev *dev,
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struct cfg80211_chan_def *chandef);
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void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev);
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int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,
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struct mt7601u_rxwi *rxwi, u16 rate);
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void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,
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struct ieee80211_bss_conf *info);
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/* MAC */
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void mt7601u_mac_work(struct work_struct *work);
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void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot,
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int ht_mode);
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void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb);
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void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval);
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void
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mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
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void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev);
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/* TX */
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void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
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struct sk_buff *skb);
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int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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u16 queue, const struct ieee80211_tx_queue_params *params);
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void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb);
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void mt7601u_tx_stat(struct work_struct *work);
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/* util */
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void mt76_remove_hdr_pad(struct sk_buff *skb);
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int mt76_insert_hdr_pad(struct sk_buff *skb);
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u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below);
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static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below)
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{
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return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below);
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}
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int mt7601u_dma_init(struct mt7601u_dev *dev);
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void mt7601u_dma_cleanup(struct mt7601u_dev *dev);
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int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb,
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struct mt76_wcid *wcid, int hw_q);
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#endif
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