572 lines
15 KiB
C
572 lines
15 KiB
C
/*
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* Serverworks AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/agp_backend.h>
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#include <asm/set_memory.h>
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#include "agp.h"
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#define SVWRKS_COMMAND 0x04
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#define SVWRKS_APSIZE 0x10
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#define SVWRKS_MMBASE 0x14
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#define SVWRKS_CACHING 0x4b
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#define SVWRKS_AGP_ENABLE 0x60
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#define SVWRKS_FEATURE 0x68
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#define SVWRKS_SIZE_MASK 0xfe000000
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/* Memory mapped registers */
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#define SVWRKS_GART_CACHE 0x02
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#define SVWRKS_GATTBASE 0x04
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#define SVWRKS_TLBFLUSH 0x10
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#define SVWRKS_POSTFLUSH 0x14
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#define SVWRKS_DIRFLUSH 0x0c
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struct serverworks_page_map {
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unsigned long *real;
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unsigned long __iomem *remapped;
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};
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static struct _serverworks_private {
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struct pci_dev *svrwrks_dev; /* device one */
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volatile u8 __iomem *registers;
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struct serverworks_page_map **gatt_pages;
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int num_tables;
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struct serverworks_page_map scratch_dir;
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int gart_addr_ofs;
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int mm_addr_ofs;
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} serverworks_private;
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static int serverworks_create_page_map(struct serverworks_page_map *page_map)
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{
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int i;
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page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
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if (page_map->real == NULL) {
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return -ENOMEM;
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}
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set_memory_uc((unsigned long)page_map->real, 1);
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page_map->remapped = page_map->real;
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for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
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writel(agp_bridge->scratch_page, page_map->remapped+i);
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/* Red Pen: Everyone else does pci posting flush here */
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return 0;
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}
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static void serverworks_free_page_map(struct serverworks_page_map *page_map)
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{
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set_memory_wb((unsigned long)page_map->real, 1);
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free_page((unsigned long) page_map->real);
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}
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static void serverworks_free_gatt_pages(void)
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{
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int i;
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struct serverworks_page_map **tables;
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struct serverworks_page_map *entry;
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tables = serverworks_private.gatt_pages;
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for (i = 0; i < serverworks_private.num_tables; i++) {
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entry = tables[i];
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if (entry != NULL) {
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if (entry->real != NULL) {
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serverworks_free_page_map(entry);
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}
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kfree(entry);
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}
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}
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kfree(tables);
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}
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static int serverworks_create_gatt_pages(int nr_tables)
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{
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struct serverworks_page_map **tables;
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struct serverworks_page_map *entry;
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int retval = 0;
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int i;
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tables = kcalloc(nr_tables + 1, sizeof(struct serverworks_page_map *),
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GFP_KERNEL);
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if (tables == NULL)
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return -ENOMEM;
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for (i = 0; i < nr_tables; i++) {
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entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
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if (entry == NULL) {
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retval = -ENOMEM;
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break;
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}
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tables[i] = entry;
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retval = serverworks_create_page_map(entry);
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if (retval != 0) break;
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}
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serverworks_private.num_tables = nr_tables;
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serverworks_private.gatt_pages = tables;
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if (retval != 0) serverworks_free_gatt_pages();
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return retval;
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}
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#define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
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GET_PAGE_DIR_IDX(addr)]->remapped)
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#ifndef GET_PAGE_DIR_OFF
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#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
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#endif
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#ifndef GET_PAGE_DIR_IDX
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#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
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GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
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#endif
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#ifndef GET_GATT_OFF
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#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
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#endif
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static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
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{
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struct aper_size_info_lvl2 *value;
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struct serverworks_page_map page_dir;
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int retval;
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u32 temp;
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int i;
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value = A_SIZE_LVL2(agp_bridge->current_size);
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retval = serverworks_create_page_map(&page_dir);
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if (retval != 0) {
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return retval;
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}
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retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
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if (retval != 0) {
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serverworks_free_page_map(&page_dir);
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return retval;
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}
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/* Create a fake scratch directory */
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for (i = 0; i < 1024; i++) {
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writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
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writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
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}
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retval = serverworks_create_gatt_pages(value->num_entries / 1024);
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if (retval != 0) {
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serverworks_free_page_map(&page_dir);
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serverworks_free_page_map(&serverworks_private.scratch_dir);
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return retval;
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}
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agp_bridge->gatt_table_real = (u32 *)page_dir.real;
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agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
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agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
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/* Get the address for the gart region.
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* This is a bus address even on the alpha, b/c its
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* used to program the agp master not the cpu
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*/
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pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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/* Calculate the agp offset */
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for (i = 0; i < value->num_entries / 1024; i++)
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writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
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return 0;
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}
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static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
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{
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struct serverworks_page_map page_dir;
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page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
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page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
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serverworks_free_gatt_pages();
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serverworks_free_page_map(&page_dir);
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serverworks_free_page_map(&serverworks_private.scratch_dir);
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return 0;
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}
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static int serverworks_fetch_size(void)
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{
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int i;
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u32 temp;
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u32 temp2;
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struct aper_size_info_lvl2 *values;
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values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
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pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
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pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
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SVWRKS_SIZE_MASK);
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pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
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pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
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temp2 &= SVWRKS_SIZE_MASK;
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp2 == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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/*
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* This routine could be implemented by taking the addresses
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* written to the GATT, and flushing them individually. However
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* currently it just flushes the whole table. Which is probably
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* more efficient, since agp_memory blocks can be a large number of
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* entries.
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*/
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static void serverworks_tlbflush(struct agp_memory *temp)
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{
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unsigned long timeout;
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writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
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timeout = jiffies + 3*HZ;
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while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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dev_err(&serverworks_private.svrwrks_dev->dev,
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"TLB post flush took more than 3 seconds\n");
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break;
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}
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}
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writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
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timeout = jiffies + 3*HZ;
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while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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dev_err(&serverworks_private.svrwrks_dev->dev,
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"TLB Dir flush took more than 3 seconds\n");
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break;
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}
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}
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}
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static int serverworks_configure(void)
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{
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struct aper_size_info_lvl2 *current_size;
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u32 temp;
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u8 enable_reg;
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u16 cap_reg;
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current_size = A_SIZE_LVL2(agp_bridge->current_size);
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/* Get the memory mapped registers */
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pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
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temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
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if (!serverworks_private.registers) {
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dev_err(&agp_bridge->dev->dev, "can't ioremap(%#x)\n", temp);
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return -ENOMEM;
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}
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writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
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readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
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writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
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readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */
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cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
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cap_reg &= ~0x0007;
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cap_reg |= 0x4;
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writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
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readw(serverworks_private.registers+SVWRKS_COMMAND);
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pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
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enable_reg |= 0x1; /* Agp Enable bit */
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pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
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serverworks_tlbflush(NULL);
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agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
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/* Fill in the mode register */
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pci_read_config_dword(serverworks_private.svrwrks_dev,
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agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
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pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
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enable_reg &= ~0x3;
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pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
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pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
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enable_reg |= (1<<6);
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pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
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return 0;
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}
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static void serverworks_cleanup(void)
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{
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iounmap((void __iomem *) serverworks_private.registers);
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}
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static int serverworks_insert_memory(struct agp_memory *mem,
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off_t pg_start, int type)
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{
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int i, j, num_entries;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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if ((pg_start + mem->page_count) > num_entries) {
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return -EINVAL;
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}
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j = pg_start;
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while (j < (pg_start + mem->page_count)) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = SVRWRKS_GET_GATT(addr);
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if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
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return -EBUSY;
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j++;
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}
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if (!mem->is_flushed) {
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global_cache_flush();
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mem->is_flushed = true;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = SVRWRKS_GET_GATT(addr);
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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page_to_phys(mem->pages[i]), mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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}
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serverworks_tlbflush(mem);
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return 0;
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}
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static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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int i;
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unsigned long __iomem *cur_gatt;
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unsigned long addr;
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if (type != 0 || mem->type != 0) {
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return -EINVAL;
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}
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global_cache_flush();
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serverworks_tlbflush(mem);
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = SVRWRKS_GET_GATT(addr);
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writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
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}
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serverworks_tlbflush(mem);
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return 0;
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}
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static const struct gatt_mask serverworks_masks[] =
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{
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{.mask = 1, .type = 0}
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};
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static const struct aper_size_info_lvl2 serverworks_sizes[7] =
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{
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{2048, 524288, 0x80000000},
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{1024, 262144, 0xc0000000},
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{512, 131072, 0xe0000000},
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{256, 65536, 0xf0000000},
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{128, 32768, 0xf8000000},
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{64, 16384, 0xfc000000},
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{32, 8192, 0xfe000000}
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};
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static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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u32 command;
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pci_read_config_dword(serverworks_private.svrwrks_dev,
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bridge->capndx + PCI_AGP_STATUS,
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&command);
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command = agp_collect_device_status(bridge, mode, command);
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command &= ~0x10; /* disable FW */
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command &= ~0x08;
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command |= 0x100;
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pci_write_config_dword(serverworks_private.svrwrks_dev,
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bridge->capndx + PCI_AGP_COMMAND,
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command);
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agp_device_command(command, false);
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}
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static const struct agp_bridge_driver sworks_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = serverworks_sizes,
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.size_type = LVL2_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = serverworks_configure,
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.fetch_size = serverworks_fetch_size,
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.cleanup = serverworks_cleanup,
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.tlb_flush = serverworks_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = serverworks_masks,
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.agp_enable = serverworks_agp_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = serverworks_create_gatt_table,
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.free_gatt_table = serverworks_free_gatt_table,
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.insert_memory = serverworks_insert_memory,
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.remove_memory = serverworks_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_alloc_pages = agp_generic_alloc_pages,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static int agp_serverworks_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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struct pci_dev *bridge_dev;
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u32 temp, temp2;
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u8 cap_ptr = 0;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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switch (pdev->device) {
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case 0x0006:
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dev_err(&pdev->dev, "ServerWorks CNB20HE is unsupported due to lack of documentation\n");
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return -ENODEV;
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case PCI_DEVICE_ID_SERVERWORKS_HE:
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case PCI_DEVICE_ID_SERVERWORKS_LE:
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case 0x0007:
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break;
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default:
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if (cap_ptr)
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dev_err(&pdev->dev, "unsupported Serverworks chipset "
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"[%04x/%04x]\n", pdev->vendor, pdev->device);
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return -ENODEV;
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}
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/* Everything is on func 1 here so we are hardcoding function one */
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bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
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(unsigned int)pdev->bus->number,
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PCI_DEVFN(0, 1));
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if (!bridge_dev) {
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dev_info(&pdev->dev, "can't find secondary device\n");
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return -ENODEV;
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|
}
|
|
|
|
serverworks_private.svrwrks_dev = bridge_dev;
|
|
serverworks_private.gart_addr_ofs = 0x10;
|
|
|
|
pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
|
|
if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
|
pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
|
|
if (temp2 != 0) {
|
|
dev_info(&pdev->dev, "64 bit aperture address, "
|
|
"but top bits are not zero; disabling AGP\n");
|
|
return -ENODEV;
|
|
}
|
|
serverworks_private.mm_addr_ofs = 0x18;
|
|
} else
|
|
serverworks_private.mm_addr_ofs = 0x14;
|
|
|
|
pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
|
|
if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
|
pci_read_config_dword(pdev,
|
|
serverworks_private.mm_addr_ofs + 4, &temp2);
|
|
if (temp2 != 0) {
|
|
dev_info(&pdev->dev, "64 bit MMIO address, but top "
|
|
"bits are not zero; disabling AGP\n");
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
bridge = agp_alloc_bridge();
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
bridge->driver = &sworks_driver;
|
|
bridge->dev_private_data = &serverworks_private,
|
|
bridge->dev = pci_dev_get(pdev);
|
|
|
|
pci_set_drvdata(pdev, bridge);
|
|
return agp_add_bridge(bridge);
|
|
}
|
|
|
|
static void agp_serverworks_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
pci_dev_put(bridge->dev);
|
|
agp_remove_bridge(bridge);
|
|
agp_put_bridge(bridge);
|
|
pci_dev_put(serverworks_private.svrwrks_dev);
|
|
serverworks_private.svrwrks_dev = NULL;
|
|
}
|
|
|
|
static struct pci_device_id agp_serverworks_pci_table[] = {
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_SERVERWORKS,
|
|
.device = PCI_ANY_ID,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
|
|
|
|
static struct pci_driver agp_serverworks_pci_driver = {
|
|
.name = "agpgart-serverworks",
|
|
.id_table = agp_serverworks_pci_table,
|
|
.probe = agp_serverworks_probe,
|
|
.remove = agp_serverworks_remove,
|
|
};
|
|
|
|
static int __init agp_serverworks_init(void)
|
|
{
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
return pci_register_driver(&agp_serverworks_pci_driver);
|
|
}
|
|
|
|
static void __exit agp_serverworks_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&agp_serverworks_pci_driver);
|
|
}
|
|
|
|
module_init(agp_serverworks_init);
|
|
module_exit(agp_serverworks_cleanup);
|
|
|
|
MODULE_LICENSE("GPL and additional rights");
|
|
|