348 lines
13 KiB
C
Executable File
348 lines
13 KiB
C
Executable File
/**
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Public header file for arbiter module.
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This file is the header file that define the API and data type for arbiter
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module.
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@file ddr_arb.h
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@ingroup miDrvComm_Arb
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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*/
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#ifndef _DRAM_ARB_H
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#define _DRAM_ARB_H
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#if defined __UITRON || defined __ECOS
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#include "Driver.h"
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#else
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#include "comm/driver.h"
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#endif
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/**
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@addtogroup miDrvComm_Arb
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*/
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//@{
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/*
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DMA channel mask
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Indicate which DMA channels are required to protect/detect
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@note For DMA_WRITEPROT_ATTR
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*/
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typedef struct _DMA_CH_MSK {
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// ch 0
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UINT32 reserved0: 1; //< bit0: reserved (auto refresh)
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UINT32 CPU_NS: 1; //< CPU_NS
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UINT32 IP_USB_ETH: 1; //< USB_0
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UINT32 DCE_0: 1; //< DCE_0 (in)
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UINT32 DCE_1: 1; //< DCE_1 (in)
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UINT32 DCE_2: 1; //< DCE_2 (out)
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UINT32 DCE_3: 1; //< DCE_3 (out)
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UINT32 DCE_4: 1; //< DCE_4 (out)
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UINT32 DCE_5: 1; //< DCE_5 (in)
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UINT32 DCE_6: 1; //< DCE_6 (out)
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UINT32 DCE_7: 1; //< DCE_6 (out)
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UINT32 GRA_0: 1; //< GRA_0 (in)
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UINT32 GRA_1: 1; //< GRA_1 (in)
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UINT32 GRA_2: 1; //< GRA_2 (in)
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UINT32 GRA_3: 1; //< GRA_3 (out)
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UINT32 GRA_4: 1; //< GRA_4 (out)
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// ch 16
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UINT32 GRA2_0: 1; //< GRA2_0 (in)
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UINT32 GRA2_1: 1; //< GRA2_1 (in)
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UINT32 GRA2_2: 1; //< GRA2_2 (out)
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UINT32 JPG_0: 1; //< JPG IMG
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UINT32 JPG_1: 1; //< JPG BS
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UINT32 JPG_2: 1; //< JPG Enc DC out
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UINT32 JPG_3: 1; //< JPG Enc DC out
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UINT32 IPE_0: 1; //< IPE_0 (in)
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UINT32 IPE_1: 1; //< IPE_1 (in)
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UINT32 IPE_2: 1; //< IPE_2 (out)
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UINT32 IPE_3: 1; //< IPE_3 (out)
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UINT32 IPE_4: 1; //< IPE_4 (out)
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UINT32 IPE_5: 1; //< IPE_5 (out)
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UINT32 IPE_6: 1; //< IPE_6 (in)
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UINT32 SIE_0: 1; //< SIE_0 (out)
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UINT32 SIE_1: 1; //< SIE_1 (out)
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// ch 32
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UINT32 SIE_2: 1; //< SIE_2 (in)
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UINT32 SIE_3: 1; //< SIE_3 (in)
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UINT32 SIE2_0: 1; //< SIE2_0 (out)
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UINT32 SIE2_1: 1; //< SIE2_1 (out)
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UINT32 SIE2_2: 1; //< SIE2_2 (in)
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UINT32 SIE2_3: 1; //< SIE2_3 (in)
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UINT32 SIE3_0: 1; //< SIE3_0 (out)
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UINT32 SIE3_1: 1; //< SIE3_1 (out)
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UINT32 bDIS_0: 1; //< DIS_0 (in/out)
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UINT32 DIS_1: 1; //< DIS_1 (in)
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UINT32 LARB: 1; //< Local arbiter (SIF/BMC/I2C/UART/SPI)
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UINT32 DAI: 1; //< DAI
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UINT32 IFE_0: 1; //< IFE_0 (in)
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UINT32 IFE_1: 1; //< IFE_1 (in)
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UINT32 IFE_2: 1; //< IFE_2 (out)
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UINT32 IME_0: 1; //< IME_0 (in)
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// ch 48
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UINT32 IME_1: 1; //< IME_1 (in)
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UINT32 IME_2: 1; //< IME_2 (in)
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UINT32 IME_3: 1; //< IME_3 (out)
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UINT32 IME_4: 1; //< IME_4 (out)
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UINT32 IME_5: 1; //< IME_5 (out)
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UINT32 IME_6: 1; //< IME_6 (out)
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UINT32 IME_7: 1; //< IME_7 (out)
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UINT32 IME_8: 1; //< IME_8 (out)
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UINT32 IME_9: 1; //< IME_9 (out)
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UINT32 IME_A: 1; //< IME_A (out)
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UINT32 IME_B: 1; //< IME_B (out)
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UINT32 IME_C: 1; //< IME_C (in)
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UINT32 IME_D: 1; //< IME_D (out)
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UINT32 IME_E: 1; //< IME_E (in)
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UINT32 IME_F: 1; //< IME_F (in)
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UINT32 IME_10: 1; //< IME_10 (in)
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// ch 64
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UINT32 IME_11: 1; //< IME_11 (in)
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UINT32 IME_12: 1; //< IME_12 (out)
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UINT32 IME_13: 1; //< IME_13 (out)
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UINT32 IME_14: 1; //< IME_14 (in)
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UINT32 IME_15: 1; //< IME_15 (out)
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UINT32 IME_16: 1; //< IME_16 (in/out)
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UINT32 IME_17: 1; //< IME_17 (out)
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UINT32 ISE_0: 1; //< ISE_0 (in)
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UINT32 ISE_1: 1; //< ISE_1 (out)
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UINT32 ISE_2: 1;
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UINT32 IDE_0: 1; //< IDE_0 (in)
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UINT32 IDE_1: 1; //< IDE_1 (in)
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UINT32 IDE_2: 1; //< IDE_2 (in/out)
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UINT32 IDE_3: 1; //< IDE_3 (in/out)
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UINT32 IDE_4: 1; //< IDE_4 (in)
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UINT32 IDE_5: 1; //< IDE_5 (in)
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// ch 80
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UINT32 SDIO: 1; //< SDIO
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UINT32 SDIO2: 1; //< SDIO2
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UINT32 SDIO3: 1; //< SDIO3
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UINT32 NAND: 1; //< NAND
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UINT32 H264_0: 1; //< H.264_0
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UINT32 H264_1: 1; //< H.264_1
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UINT32 H264_3: 1; //< H.264_3
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UINT32 H264_4: 1; //< H.264_4
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UINT32 H264_5: 1; //< H.264_5
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UINT32 H264_6: 1; //< H.264_6
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UINT32 H264_8: 1; //< H.264_8
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UINT32 H264_9: 1; //< H.264_9 (COE)
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UINT32 IFE2_0: 1; //< IFE2_0 (in)
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UINT32 IFE2_1: 1; //< IFE2_1 (out)
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UINT32 TSE: 1; //< TSE input
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UINT32 TSE_1: 1; //< TSE output
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// ch 96
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UINT32 CRYPTO: 1; //< CRYPTO (in/out)
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UINT32 HASH: 1; //< Hash (in/out)
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UINT32 CNN_0: 1; //< CNN_0 (in)
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UINT32 CNN_1: 1; //< CNN_1 (in)
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UINT32 CNN_2: 1; //< CNN_2 (in)
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UINT32 CNN_3: 1; //< CNN_3 (in)
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UINT32 CNN_4: 1; //< CNN_4 (out)
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UINT32 CNN_5: 1; //< CNN_5 (out)
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UINT32 CNN_6: 1; //< CNN_5 (out)
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UINT32 NUE2_0: 1; //< NUE2_0 (in)
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UINT32 NUE2_1: 1; //< NUE2_1 (in)
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UINT32 NUE2_2: 1; //< NUE2_2 (in)
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UINT32 NUE2_3: 1; //< NUE2_3 (out)
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UINT32 NUE2_4: 1; //< NUE2_4 (out)
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UINT32 NUE2_5: 1; //< NUE2_5 (out)
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UINT32 NUE2_6: 1; //< NUE2_5 (out)
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// ch 112
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UINT32 MDBC_0: 1; //< MDBC_0 (in)
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UINT32 MDBC_1: 1; //< MDBC_1 (in)
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UINT32 MDBC_2: 1; //< MDBC_2 (in)
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UINT32 MDBC_3: 1; //< MDBC_3 (in)
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UINT32 MDBC_4: 1; //< MDBC_4 (in)
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UINT32 MDBC_5: 1; //< MDBC_5 (in)
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UINT32 MDBC_6: 1; //< MDBC_6 (out)
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UINT32 MDBC_7: 1; //< MDBC_7 (out)
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UINT32 MDBC_8: 1; //< MDBC_8 (in)
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UINT32 MDBC_9: 1; //< MDBC_9 (out)
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UINT32 HLOAD_0: 1; //< Heavy load
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UINT32 HLOAD_1: 1; //< Heavy load
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UINT32 HLOAD_2: 1; //< Heavy load
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UINT32 AFN_0: 1;
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UINT32 AFN_1: 1;
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UINT32 IVE_0: 1;
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// ch 128
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UINT32 IVE_1: 1;
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UINT32 UVC_0: 1;
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UINT32 UVC_1: 1;
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UINT32 reserved1: 29;
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// ch 160
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UINT32 CPU: 1;
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UINT32 reserved2: 31;
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} DMA_CH_MSK, *PDMA_CH_MSK;
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/**
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DDR Arbiter ID
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*/
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typedef enum _DDR_ARB {
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DDR_ARB_1, ///< DDR Arbiter
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DDR_ARB_COUNT, //< Arbiter count
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ENUM_DUMMY4WORD(DDR_ARB)
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} DDR_ARB;
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typedef enum _DMA_WRITEPROT_SET {
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WPSET_0, // Write protect function set 0
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WPSET_1, // Write protect function set 1
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WPSET_2, // Write protect function set 2
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WPSET_3, // Write protect function set 3
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WPSET_4, // Write protect function set 4
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WPSET_5, // Write protect function set 5
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WPSET_COUNT,
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ENUM_DUMMY4WORD(DMA_WRITEPROT_SET)
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} DMA_WRITEPROT_SET;
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typedef enum _DMA_PROT_REGION {
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DMA_PROT_RGN0,
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DMA_PROT_RGN1,
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DMA_PROT_RGN2,
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DMA_PROT_RGN3,
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DMA_PROT_RGN_TOTAL,
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ENUM_DUMMY4WORD(DMA_PROT_REGION)
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} DMA_PROT_REGION;
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typedef enum _DMA_WRITEPROT_LEVEL {
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DMA_WPLEL_UNWRITE, // Not only detect write action but also denial access.
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DMA_WPLEL_DETECT, // Only detect write action but allow write access.
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DMA_RPLEL_UNREAD, // Not only detect read action but also denial access.
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DMA_RWPLEL_UNRW, // Not only detect read write action but also denial access.
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ENUM_DUMMY4WORD(DMA_WRITEPROT_LEVEL)
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} DMA_WRITEPROT_LEVEL;
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typedef enum _DMA_PROT_MODE {
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DMA_PROT_IN,
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DMA_PROT_OUT,
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ENUM_DUMMY4WORD(DMA_PROT_MODE)
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} DMA_PROT_MODE;
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typedef struct _DMA_PROT_RGN_ATTR {
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BOOL en; // enable this region
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UINT32 starting_addr; // DDR3:must be 4 words alignment
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UINT32 size; // DDR3:must be 4 words alignment
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} DMA_PROT_RGN_ATTR, *PDMA_PROT_RGN_ATTR;
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typedef struct _DMA_WRITEPROT_ATTR {
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DMA_CH_MSK mask; // DMA channel masks to be protected/detected
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DMA_WRITEPROT_LEVEL level; // protect level
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DMA_PROT_MODE protect_mode; // in or out region
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DMA_PROT_RGN_ATTR protect_rgn_attr[DMA_PROT_RGN_TOTAL];
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} DMA_WRITEPROT_ATTR, *PDMA_WRITEPROT_ATTR;
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/*
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@name DMA outstanding
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DMA outstanding setting
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@note Used in dma_set_channel_outstanding()
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*/
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typedef enum {
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DMA_CH_OUTSTANDING_CNN_0, // CNN input
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DMA_CH_OUTSTANDING_CNN_1, // CNN input
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DMA_CH_OUTSTANDING_CNN_2, // CNN input
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DMA_CH_OUTSTANDING_CNN_3, // CNN input
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DMA_CH_OUTSTANDING_CNN_4, // CNN output
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DMA_CH_OUTSTANDING_CNN_5, // CNN output
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DMA_CH_OUTSTANDING_CNN2_0,
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DMA_CH_OUTSTANDING_CNN2_1,
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DMA_CH_OUTSTANDING_CNN2_2,
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DMA_CH_OUTSTANDING_CNN2_3,
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DMA_CH_OUTSTANDING_CNN2_4,
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DMA_CH_OUTSTANDING_CNN2_5,
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DMA_CH_OUTSTANDING_NUE_0, // NUE input
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DMA_CH_OUTSTANDING_NUE_1, // NUE input
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DMA_CH_OUTSTANDING_NUE_2, // NUE output
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DMA_CH_OUTSTANDING_CNN_ALL,
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DMA_CH_OUTSTANDING_CNN2_ALL,
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DMA_CH_OUTSTANDING_NUE_ALL,
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ENUM_DUMMY4WORD(DMA_CH_OUTSTANDING)
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} DMA_CH_OUTSTANDING;
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#define DRAM_CONSUMETSK_CHANNEL_SET_OPERATION_BIT(ch, chGroup) ((chGroup).channel_group[((ch)>>5)] |= (1<<(ch&0x1F)))
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typedef enum _DRAM_CONSUME_BW_DEGREE {
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DRAM_CONSUME_EASY_LOADING = 0x0,
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DRAM_CONSUME_NORMAL_LOADING,
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DRAM_CONSUME_HEAVY_LOADING,
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DRAM_CONSUME_CH_DISABLE,
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ENUM_DUMMY4WORD(DRAM_CONSUME_BW_DEGREE)
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} DRAM_CONSUME_BW_DEGREE;
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typedef struct {
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UINT32 channel_group[6]; // Description
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} DMA_CHANNEL, *PDMA_CHANNEL;
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typedef struct _DRAM_CONSUME_ATTR {
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DRAM_CONSUME_BW_DEGREE load_degree;
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UINT32 addr;
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UINT32 size;
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DMA_CHANNEL dma_channel;
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BOOL is_start;
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} DRAM_CONSUME_ATTR, *PDRAM_CONSUME_ATTR;
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// Arbiter Driver API
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extern void arb_enable_wp(DDR_ARB id, DMA_WRITEPROT_SET set,
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DMA_WRITEPROT_ATTR *p_attr);
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extern void arb_disable_wp(DDR_ARB id, DMA_WRITEPROT_SET set);
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extern ER arb_init(void);
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extern void arb_set_priority(BOOL is_direct);
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extern ER dma_get_channel_outstanding(DMA_CH_OUTSTANDING channel, BOOL *enable);
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extern ER dma_set_channel_outstanding(DMA_CH_OUTSTANDING channel, BOOL enable);
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extern int dram_consume_cfg(PDRAM_CONSUME_ATTR attr);
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extern int dram_consume_start(void);
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extern int dram_consume_stop(void);
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extern int dram2_consume_cfg(PDRAM_CONSUME_ATTR attr);
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extern int dram2_consume_start(void);
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extern int dram2_consume_stop(void);
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extern int ddr_data_monitor_start(DDR_ARB id);
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extern int ddr_data_monitor_stop(DDR_ARB id);
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extern void ddr_data_monitor_reset(DDR_ARB id);
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extern void ddr_data_monitor_get(DDR_ARB id, UINT64 *cnt, UINT64 *byte);
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/* @this function is used to perform hardware checksum
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* @parm: id:
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* memory address on which ddr
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* @parm: phy_addr:
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* memory physical address (must be word alignment)
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* @parm: len:
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* memory length (must be word alignment)
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* @return:
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* checksum value
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*
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*/
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extern unsigned short arb_chksum(DDR_ARB id, unsigned int phy_addr, unsigned int len);
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//@}
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//ch: 0: CPU, 1: CNN, 2: CNN2, 3: NUE, 4: NUE2, 5: ISE
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//rw: 0: write, 1: read, 2: both
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//dram: 0: DRAM1, 1: DRAM2
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extern int mau_ch_mon_start(int ch, int rw, int dram);
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extern UINT64 mau_ch_mon_stop(int ch, int dram);
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#endif
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