49 lines
		
	
	
		
			798 B
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			49 lines
		
	
	
		
			798 B
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * (C) Copyright 2017
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|  * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
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|  */
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| 
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| #include <common.h>
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| #include <asm/processor.h>
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| #include <asm/ppc.h>
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| #include <asm/io.h>
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| #include <asm/mmu.h>
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| 
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| int icache_status(void)
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| {
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| 	return !!(mfspr(IC_CST) & IDC_ENABLED);
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| }
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| 
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| void icache_enable(void)
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| {
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| 	sync();
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| 	mtspr(IC_CST, IDC_INVALL);
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| 	mtspr(IC_CST, IDC_ENABLE);
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| }
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| 
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| void icache_disable(void)
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| {
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| 	sync();
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| 	mtspr(IC_CST, IDC_DISABLE);
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| }
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| 
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| int dcache_status(void)
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| {
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| 	return !!(mfspr(IC_CST) & IDC_ENABLED);
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| }
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| 
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| void dcache_enable(void)
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| {
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| 	mtspr(MD_CTR, MD_RESETVAL);	/* Set cache mode with MMU off */
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| 	mtspr(DC_CST, IDC_INVALL);
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| 	mtspr(DC_CST, IDC_ENABLE);
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| }
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| 
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| void dcache_disable(void)
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| {
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| 	sync();
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| 	mtspr(DC_CST, IDC_DISABLE);
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| 	mtspr(DC_CST, IDC_INVALL);
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| }
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