329 lines
12 KiB
C
Executable File
329 lines
12 KiB
C
Executable File
/**
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PLL Configuration module header
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PLL Configuration module header file.
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@file pll.h
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@ingroup mIDrvSys_CG
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@note Nothing
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Copyright Novatek Microelectronics Corp. 2018. All rights reserved.
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*/
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#ifndef _PLL_H
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#define _PLL_H
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#include <kwrap/nvt_type.h>
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/**
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@addtogroup mIHALSysCG
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*/
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//@{
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/**
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Clock Enable ID
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This is for pll_enable_clock() and pll_disable_clock().
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*/
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typedef enum {
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DMA_CLK = 1, ///< DMA(SDRAM) clock
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SIE_MCLK, ///< SIE MCLK
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SIE_MCLK2, ///< SIE MCLK2
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SIE_CLK, ///< SIE clock
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SIE2_CLK, ///< SIE2 Clock
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TGE_CLK, ///< TGE clock
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IPE_CLK, ///< IPE clock
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DIS_CLK, ///< DIS clock
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IME_CLK, ///< IME clock
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SIE_MCLK3, ///< SIE MCLK3
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ISE_CLK, ///< ISE clock
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SP_CLK, ///< special clock
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IFE_CLK, ///< IFE clock
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DCE_CLK, ///< DCE clock
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IDE1_CLK = 16, ///< IDE clock
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SIE3_CLK, ///< SIE3 clock
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CRYPTO_CLK = 23, ///< Crypto clock
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VENC_CLK = 24, ///< VENC clock
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AFFINE_CLK = 25, ///< AFFINE clock
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JPG_CLK = 26, ///< JPEG clock
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GRAPH_CLK, ///< Graphic clock
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GRAPH2_CLK, ///< Graphic2 clock
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DAI_CLK, ///< DAI clock
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EAC_A_ADC_CLK, ///< EAC analog AD clock
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EAC_A_DAC_CLK, ///< EAC analog DA clock
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NAND_CLK = 32, ///< NAND clock
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SDIO_CLK = 34, ///< SDIO clock
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SDIO2_CLK, ///< SDIO2 clock
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I2C_CLK = 36, ///< I2C clock
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I2C2_CLK = 37, ///< I2C2 clock
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SPI_CLK, ///< SPI clock
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SPI2_CLK, ///< SPI2 clock
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SPI3_CLK, ///< SPI3 clock
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SIF_CLK, ///< SIF clock
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UART_CLK, ///< UART clock
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UART2_CLK, ///< UART2 clock
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REMOTE_CLK, ///< Remote clock
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ADC_CLK, ///< ADC clock
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SDIO3_CLK, ///< SDIO3 clock
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WDT_CLK = 49, ///< WDT clock
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TMR_CLK, ///< Timer clock
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EAC_D_CLKEN = 52, ///< EAC digital clock
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UVCP_CLKEN = 53, ///< UVCP clock
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UART3_CLK = 54, ///< UART3 clock
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EFUSE_CLK = 60, ///< EFUSE clock
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ETH_CLK, ///< ETH clock
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SP2_CLK, ///< SP2 clock
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I2C3_CLK = 63, ///< I2C3 clock
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MIPI_LVDS_CLK = 65, ///< MIPI/LVDS clock
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MIPI_LVDS2_CLK, ///< MIPI/LVDS2 clock
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MIPI_DSI_CLK, ///< MIPI DSI clock
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SIE_PXCLK, ///< SIE PX clock
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SIE2_PXCLK, ///< SIE2 PX clock
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SIE3_PXCLK, ///< SIE3 PX clock
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PWM_CCNT_CLK = 72, ///< PWM CCNT clock
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PWM_CCNT0_CLK = 72, ///< PWM CCNT0 clock
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PWM_CCNT1_CLK, ///< PWM CCNT1 clock
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PWM_CCNT2_CLK, ///< PWM CCNT2 clock
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TSE_CLK = 77, ///< TSE clock
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DRTC_CLK = 86, ///< DRTC clock
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ETHPHY_CLK = 88, ///< ETH PHY clock
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TRNG_CLK, ///< TRNG clock
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RSA_CLK, ///< RSA clock
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HASH_CLK, ///< HASH clock
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TRNG_RO_CLK, ///< TRNG clock
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MIPI_LVDS_PHYD4_CLK2 = 93,///< MIPI/LVDS PHY HS-clock/4
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MIPI_LVDS_PHYD4_CLK = 94,///< MIPI/LVDS PHY HS-clock/4
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MIPI_LVDS2_PHYD4_CLK = 95,///< MIPI/LVDS2 PHY HS-clock/4
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PWM0_CLK = 96, ///< PWM0 clock
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PWM1_CLK, ///< PWM1 clock
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PWM2_CLK, ///< PWM2 clock
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PWM3_CLK, ///< PWM3 clock
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PWM4_CLK, ///< PWM4 clock
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PWM5_CLK, ///< PWM5 clock
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PWM6_CLK, ///< PWM6 clock
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PWM7_CLK, ///< PWM7 clock
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PWM8_CLK, ///< PWM8 clock
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PWM9_CLK, ///< PWM9 clock
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PWM10_CLK, ///< PWM10 clock
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PWM11_CLK, ///< PWM11 clock
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SDP_CLK = 112, ///< SDP clock
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NUE2_CLK = 117, ///< NUE2 clock
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MDBC_CLK, ///< MDBC clock
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CNN_CLK, ///< CNN clock
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IVE_CLK = 121, ///< IVE clock
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IP_ACLK_CLK = 127, ///< IP_ACLK clock
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ENUM_DUMMY4WORD(CG_EN)
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} CG_EN;
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/**
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APB Clock Gating Select ID
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This is for pll_set_pclk_auto_gating() / pll_clear_pclk_auto_gating() / pll_get_pclk_auto_gating().
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*/
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typedef enum {
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SIE_GCLK, /*0*/ ///< Gating SIE APB clock
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CNN_GCLK, /*1*/ ///< Gating CNN APB clock
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IPE_GCLK, /*2*/ ///< Gating IPE APB clock
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IME_GCLK, /*3*/ ///< Gating IME APB clock
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DIS_GCLK, /*4*/ ///< Gating DIS APB clock
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DCE_GCLK = 6, ///< Gating DCE APB clock
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IFE_GCLK, /*7*/ ///< Gating IFE APB clock
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GRA_GCLK, /*8*/ ///< Gating Graphic APB clock
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GRA2_GCLK, /*9*/ ///< Gating Graphic2 APB clock
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IDE_GCLK, /*10*/ ///< Gating IDE APB clock
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NUE2_GCLK = 12, ///< Gating NUE2 APB clock
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MDBC_GCLK, /*13*/ ///< Gating MDBC APB clock
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JPG_GCLK = 15, ///< Gating JPEG APB clock
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VENC_GCLK = 16, ///< Gating VENC APB clock
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DAI_GCLK, /*17*/ ///< Gating DAI APB clock
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EAC_GCLK, /*18*/ ///< Gating EAC APB clock
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NAND_GCLK, /*19*/ ///< Gating xD/Nand APB clock
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SDIO_GCLK, /*20*/ ///< Gating SDIO APB clock
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SDIO2_GCLK, /*21*/ ///< Gating SDIO2 APB clock
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I2C_GCLK, /*22*/ ///< Gating I2C APB clock
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I2C2_GCLK, /*23*/ ///< Gating I2C2 APB clock
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SPI_GCLK, /*24*/ ///< Gating SPI APB clock
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SPI2_GCLK, /*25*/ ///< Gating SPI2 APB clock
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SPI3_GCLK, /*26*/ ///< Gating SPI3 APB clock
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SIF_GCLK, /*27*/ ///< Gating SIF APB clock
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UART_GCLK, /*28*/ ///< Gating UART APB clock
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UART2_GCLK, /*29*/ ///< Gating UART2 APB clock
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RM_GCLK, /*30*/ ///< Gating Remote APB clock
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ADC_GCLK, /*31*/ ///< Gating ADC APB clock
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TMR_GCLK, /*32*/ ///< Gating TMR APB clock
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WDT_GCLK, /*33*/ ///< Gating Watchdog APB clock
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SDE_GCLK, /*34*/ ///< Gating SDE APB clock
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MIPI_LVDS_GCLK = 35, ///< Gating MIPI/LVDS APB clock
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MIPI_LVDS2_GCLK, /*36*/ ///< Gating MIPI/LVDS2 APB clock
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MIPI_DSI_GCLK = 38, ///< Gating MIPI DSI APB clock
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ISE_GCLK = 40, ///< Gating ISE APB clock
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SIE2_GCLK, /*41*/ ///< Gating SIE2 APB clock
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SIE3_GCLK, /*42*/ ///< Gating SIE3 APB clock
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PWM_GCLK, /*43*/ ///< Gating PWM APB clock
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SDIO3_GCLK = 47, ///< Gating SDIO3 APB clock
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UART3_GCLK, /*48*/ ///< Gating UART3 APB clock
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TGE_GCLK = 52, ///< Gating TGE APB clock
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I2C3_GCLK = 56, ///< Gating I2C3 APB clock
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TSE_GCLK, /*57*/ ///< Gating TSE APB clock
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AFFINE_GCLK, /*58*/ ///< Gating AFFINE APB clock
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IVE_GCLK = 60, ///< Gating IVE APB clock
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SENPHY_GCLK = 61, ///< Gating SENPHY APB clock
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UVCP_GCLK = 62, ///< Gating UVCP APB clock
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GPIO_GCLK = 64, ///< Gating GPIO APB clock
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INTC_GCLK, /*65*/ ///< Gating INTC APB clock
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DMA_GCLK = 67, ///< Gating DMAC APB clock
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PCLKGAT_MAXNUM,
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ENUM_DUMMY4WORD(GATECLK)
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} GATECLK;
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/**
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Module Clock Gating Select ID
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This is for pll_set_clk_auto_gating() / pll_clear_clk_auto_gating() / pll_get_clk_auto_gating().
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*/
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typedef enum {
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M_GCLK_BASE = PCLKGAT_MAXNUM,
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CNN_M_GCLK, /*1*/ ///< Gating CNN Module clock
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IPE_M_GCLK, /*2*/ ///< Gating IPE Module clock
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IME_M_GCLK, /*3*/ ///< Gating IME Module clock
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DIS_M_GCLK, /*4*/ ///< Gating DIS Module clock
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DCE_M_GCLK = 6+M_GCLK_BASE, ///< Gating DCE Module clock
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IFE_M_GCLK, /*7*/ ///< Gating IFE Module clock
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GRA_M_GCLK, /*8*/ ///< Gating Graphic Module clock
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GRA2_M_GCLK, /*9*/ ///< Gating Graphic2 Module clock
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NUE2_M_GCLK = 12+M_GCLK_BASE, ///< Gating NUE2 Module clock
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MDBC_M_GCLK, /*13*/ ///< Gating MDBC Module clock
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JPG_M_GCLK = 15+M_GCLK_BASE, ///< Gating JPEG Module clock
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VENC_M_GCLK = 16+M_GCLK_BASE, ///< Gating VENC Module clock
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NAND_M_GCLK = 19+M_GCLK_BASE, ///< Gating xD/Nand Module clock
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SDIO_M_GCLK, /*20*/ ///< Gating SDIO Module clock
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SDIO2_M_GCLK, /*21*/ ///< Gating SDIO2 Module clock
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SPI_M_GCLK = 24+M_GCLK_BASE, ///< Gating SPI Module clock
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SPI2_M_GCLK, /*25*/ ///< Gating SPI2 Module clock
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SPI3_M_GCLK, /*26*/ ///< Gating SPI3 Module clock
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SIF_M_GCLK, /*27*/ ///< Gating SIF Module clock
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ISE_M_GCLK = 40+M_GCLK_BASE, ///< Gating ISE Module clock
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PWM_M_GCLK = 43+M_GCLK_BASE, ///< Gating PWM Module clock
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SDIO3_M_GCLK = 47+M_GCLK_BASE, ///< Gating SDIO3 Module clock
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TSE_M_GCLK = 57+M_GCLK_BASE, ///< Gating TSE Module clock
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AFFINE_M_GCLK = 58+M_GCLK_BASE, ///< Gating AFFINE Module clock
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ETH_M_GCLK = 59+M_GCLK_BASE, ///< Gating ETH Module clock
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IVE_M_GCLK = 60+M_GCLK_BASE, ///< Gating IVE Module clock
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MCLKGAT_MAXNUM,
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ENUM_DUMMY4WORD(M_GATECLK)
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} M_GATECLK;
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/*
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@name Default Gating Clock Select definition
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This is for pll_config_clk_auto_gating() & pll_config_pclk_auto_gating().
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*/
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//@{
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#define PLL_CLKSEL_DEFAULT_CLKGATE1 0x00000000
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#define PLL_CLKSEL_DEFAULT_CLKGATE2 0x00000000
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#define PLL_CLKSEL_DEFAULT_PCLKGATE1 0x00000000
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#define PLL_CLKSEL_DEFAULT_PCLKGATE2 0x00000000
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#define PLL_CLKSEL_DEFAULT_PCLKGATE3 0x00000000
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//@}
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/**
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PLL ID
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*/
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typedef enum {
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PLL_ID_1 = 1, ///< PLL1 (internal 480 MHz)
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PLL_ID_3 = 3, ///< PLL3 (for DMA)
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PLL_ID_4 = 4, ///< PLL4 (N/A:dummy)
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PLL_ID_5 = 5, ///< PLL5 (for sensor1)
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PLL_ID_6 = 6, ///< PLL6 (for IDE/eth)
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PLL_ID_7 = 7, ///< PLL7 (for audio)
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PLL_ID_8 = 8, ///< PLL8 (for CPU)
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PLL_ID_9 = 9, ///< PLL9 (for IDE/eth backup)
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PLL_ID_10 = 10, ///< PLL10 (N/A:dummy)
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PLL_ID_11 = 11, ///< PLL11 (for DSI)
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PLL_ID_12 = 12, ///< PLL12 (for sensor2)
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PLL_ID_13 = 13, ///< PLL13 (N/A:dummy)
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PLL_ID_14 = 14, ///< PLL14 (N/A:dummy)
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PLL_ID_15 = 15, ///< PLL15 (N/A:dummy)
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PLL_ID_16 = 16, ///< PLL16 (N/A:dummy)
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PLL_ID_17 = 17, ///< PLL17 (N/A:dummy)
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PLL_ID_18 = 18, ///< PLL18 (N/A:dummy)
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PLL_ID_FIXED320 = 24, ///< Fixed 320MHz PLL
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PLL_ID_MAX,
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ENUM_DUMMY4WORD(PLL_ID)
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} PLL_ID;
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#define PLL_ID_2 PLL_ID_MAX ///< Backward compatible
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extern ER pll_set_pll(PLL_ID id, UINT32 ui_setting);
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extern BOOL pll_get_pll_enable(PLL_ID id);
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extern ER pll_set_pll_enable(PLL_ID id, BOOL b_enable);
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extern ER pll_set_pll_freq(PLL_ID id, UINT32 ui_frequency);
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extern UINT32 pll_get_pll_freq(PLL_ID id);
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extern ER pll_set_pll_spread_spectrum(PLL_ID id, UINT32 lower_frequency, UINT32 upper_frequency);
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extern ER pll_get_pll_spread_spectrum(PLL_ID id, UINT32 *pui_lower_freq, UINT32 *pui_upper_freq);
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extern void pll_set_pwm_clock_rate(UINT32 pwm_number, UINT32 ui_divider);
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extern BOOL pll_is_clock_enabled(CG_EN num);
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extern void pll_set_clk_auto_gating(M_GATECLK clock_select);
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extern void pll_clear_clk_auto_gating(M_GATECLK clock_select);
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extern BOOL pll_get_clk_auto_gating(M_GATECLK clock_select);
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extern void pll_set_pclk_auto_gating(GATECLK clock_select);
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extern void pll_clear_pclk_auto_gating(GATECLK clock_select);
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extern BOOL pll_get_pclk_auto_gating(GATECLK clock_select);
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extern void pll_set_trng_ro_sel(UINT32 trng_ro_select, UINT32 ui_divider);
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extern void pll_get_trng_ro_sel(UINT32 *pui_trng_ro_sel, UINT32 *pui_divider);
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extern ER pll_init(void);
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extern UINT32 pll_get_apb_freq(void);
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#define pll_setPLL pll_set_pll
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#define pll_getPLLEn pll_get_pll_enable
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#define pll_setPLLEn pll_set_pll_enable
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#define pll_getPLLFreq pll_get_pll_freq
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#define pll_setPLLSpreadSpectrum pll_set_pll_spread_spectrum
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#define pll_getPLLSpreadSpectrum pll_get_pll_spread_spectrum
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#define pll_isClockEnabled pll_is_clock_enabled
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#define pll_setClkAutoGating pll_set_clk_auto_gating
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#define pll_clearClkAutoGating pll_clear_clk_auto_gating
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#define pll_getClkAutoGating pll_get_clk_auto_gating
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#define pll_setPclkAutoGating pll_set_pclk_auto_gating
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#define pll_clearPclkAutoGating pll_clear_pclk_auto_gating
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#define pll_getPclkAutoGating pll_get_pclk_auto_gating
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//@}
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#endif
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