265 lines
9.8 KiB
Plaintext
265 lines
9.8 KiB
Plaintext
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
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It can work in two mode: standalone mode and PCIe endpoint mode.
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T2080 SoC Overview
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------------------
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The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
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Architecture processor cores with high-performance datapath acceleration
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logic and network and peripheral bus interfaces required for networking,
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telecom/datacom, wireless infrastructure, and mil/aerospace applications.
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T2080 includes the following functions and features:
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- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
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- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
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- Hierarchical interconnect fabric
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- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration
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- 16 SerDes lanes up to 10.3125 GHz
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- 8 Ethernet interfaces, supporting combinations of the following:
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- Up to four 10 Gbps Ethernet MACs
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- Up to eight 1 Gbps Ethernet MACs
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- Up to four 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
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- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
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- Additional peripheral interfaces
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- Two serial ATA (SATA 2.0) controllers
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- Two high-speed USB 2.0 controllers with integrated PHY
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- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
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- Enhanced serial peripheral interface (eSPI)
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- Four I2C controllers
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- Four 2-pin UARTs or two 4-pin UARTs
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- Integrated Flash Controller supporting NAND and NOR flash
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- Three eight-channel DMA engines
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ Platform's Trust Architecture 2.0
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Differences between T2080 and T2081
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-----------------------------------
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Feature T2080 T2081
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1G Ethernet numbers: 8 6
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10G Ethernet numbers: 4 2
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SerDes lanes: 16 8
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Serial RapidIO,RMan: 2 no
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SATA Controller: 2 no
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Aurora: yes no
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SoC Package: 896-pins 780-pins
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T2080PCIe-RDB board Overview
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----------------------------
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- SERDES Configuration
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- SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
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- SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
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- SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
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- SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
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- SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
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- SerDes-2 Lane G-H: to SATA1 & SATA2
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- Ethernet
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- Two on-board 10M/100M/1G RGMII ethernet ports
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- Two on-board 10Gbps XFI fiber ports
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- Two on-board 10Gbps Base-T copper ports
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- DDR Memory
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- Supports 72bit 4GB DDR3-LP SODIMM
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- PCIe
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- One PCIe x4 gold-finger
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- One PCIe x4 connector
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- One PCIe x2 end-point device (C293 Crypto co-processor)
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- IFC/Local Bus
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- NOR: 128MB 16-bit NOR Flash
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- NAND: 1GB 8-bit NAND flash
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- CPLD: for system controlling with programable header on-board
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- SATA
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- Two SATA 2.0 onnectors on-board
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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- Two type A ports with 5V@1.5A per port.
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- SDHC
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- one TF-card connector on-board
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- SPI
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- On-board 64MB SPI flash
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- Other
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- Two Serial ports
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- Four I2C ports
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System Memory map
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-----------------
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
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0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
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0x0_0000_0000 0x0_ffff_ffff DDR 4GB
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128M NOR Flash memory Map
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-------------------------
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Start Address End Address Definition Max size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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T2080PCIe-RDB Ethernet Port Map
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-------------------------------
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Label In Uboot In Linux FMan Address Comments PHY
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ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
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ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
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ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
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ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
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ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
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ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
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T2080PCIe-RDB Default DIP-Switch setting
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----------------------------------------
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SW1[1:8] = '00010011'
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SW2[1:8] = '10111111'
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SW3[1:8] = '11100001'
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Software configurations and board settings
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------------------------------------------
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1. NOR boot:
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a. build NOR boot image
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$ make T2080RDB_config
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$ make
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b. program u-boot.bin image to NOR flash
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=> tftp 1000000 u-boot.bin
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=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
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set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
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Switching between default bank and alternate bank on NOR flash
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To change boot source to vbank4:
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via software: run command 'cpld reset altbank' in U-Boot.
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via DIP-switch: set SW3[5:7] = '100'
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To change boot source to vbank0:
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via software: run command 'cpld reset' in U-Boot.
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via DIP-Switch: set SW3[5:7] = '000'
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2. NAND Boot:
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a. build PBL image for NAND boot
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$ make T2080RDB_NAND_config
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$ make
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b. program u-boot-with-spl-pbl.bin to NAND flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 d0000
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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$ make T2080RDB_SPIFLASH_config
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$ make
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b. program u-boot-with-spl-pbl.bin to SPI flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> sf probe 0
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=> sf erase 0 d0000
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=> sf write 1000000 0 $filesize
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set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
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4. SD Boot:
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a. build PBL image for SD boot
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$ make T2080RDB_SDCARD_config
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$ make
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b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x800
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
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SPL further initializes DDR using SPD and environment variables
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and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
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Finally SPL transers control to U-Boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (50KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-Boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T2080RDB
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--------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
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0x100000 0x17FFFF U-Boot env 512KB (1 block)
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0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
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0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
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Micro SD Card memory Map on T2080RDB
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 U-Boot img 1MB
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0x800 0016 U-Boot env 8KB
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0x820 0128 FMAN ucode 64KB
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0x8a0 0512 CS4315 ucode 256KB
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SPI Flash memory Map on T2080RDB
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF U-Boot img 1MB
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0x100000 0x101FFF U-Boot env 8KB
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0x110000 0x11FFFF FMAN ucode 64KB
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0x120000 0x15FFFF CS4315 ucode 256KB
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How to update the ucode of Cortina CS4315/CS4340 10G PHY
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--------------------------------------------------------
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=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
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=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
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How to update the ucode of Freescale FMAN
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-----------------------------------------
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=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
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=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
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For more details, please refer to T2080PCIe-RDB User Guide and access
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website www.freescale.com and Freescale QorIQ SDK Infocenter document.
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