268 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			268 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *   Copyright (C) 2007 Advanced Micro Devices, Inc.
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|  *   Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
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|  *
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|  *   This program is free software; you can redistribute it and/or modify it
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|  *   under the terms of the GNU General Public License as published by the
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|  *   Free Software Foundation; either version 2 of the License, or (at your
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|  *   option) any later version.
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|  */
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| #include <linux/fb.h>
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| #include <asm/io.h>
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| #include <asm/msr.h>
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| #include <linux/cs5535.h>
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| #include <asm/delay.h>
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| 
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| #include "gxfb.h"
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| 
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| #ifdef CONFIG_PM
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| 
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| static void gx_save_regs(struct gxfb_par *par)
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| {
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| 	int i;
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| 
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| 	/* wait for the BLT engine to stop being busy */
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| 	do {
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| 		i = read_gp(par, GP_BLT_STATUS);
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| 	} while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
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| 
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| 	/* save MSRs */
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| 	rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
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| 	rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
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| 
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| 	write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
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| 
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| 	/* save registers */
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| 	memcpy(par->gp, par->gp_regs, sizeof(par->gp));
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| 	memcpy(par->dc, par->dc_regs, sizeof(par->dc));
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| 	memcpy(par->vp, par->vid_regs, sizeof(par->vp));
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| 	memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp));
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| 
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| 	/* save the palette */
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| 	write_dc(par, DC_PAL_ADDRESS, 0);
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| 	for (i = 0; i < ARRAY_SIZE(par->pal); i++)
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| 		par->pal[i] = read_dc(par, DC_PAL_DATA);
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| }
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| 
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| static void gx_set_dotpll(uint32_t dotpll_hi)
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| {
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| 	uint32_t dotpll_lo;
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| 	int i;
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| 
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| 	rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
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| 	dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
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| 	dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS;
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| 	wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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| 
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| 	/* wait for the PLL to lock */
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| 	for (i = 0; i < 200; i++) {
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| 		rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
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| 		if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
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| 			break;
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| 		udelay(1);
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| 	}
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| 
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| 	/* PLL set, unlock */
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| 	dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
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| 	wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
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| }
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| 
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| static void gx_restore_gfx_proc(struct gxfb_par *par)
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| {
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| 	int i;
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| 
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| 	for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
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| 		switch (i) {
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| 		case GP_VECTOR_MODE:
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| 		case GP_BLT_MODE:
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| 		case GP_BLT_STATUS:
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| 		case GP_HST_SRC:
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| 			/* don't restore these registers */
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| 			break;
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| 		default:
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| 			write_gp(par, i, par->gp[i]);
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| 		}
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| 	}
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| }
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| 
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| static void gx_restore_display_ctlr(struct gxfb_par *par)
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| {
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| 	int i;
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| 
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| 	for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
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| 		switch (i) {
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| 		case DC_UNLOCK:
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| 			/* unlock the DC; runs first */
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| 			write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
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| 			break;
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| 
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| 		case DC_GENERAL_CFG:
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| 			/* write without the enables */
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| 			write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
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| 					DC_GENERAL_CFG_ICNE |
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| 					DC_GENERAL_CFG_CURE |
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| 					DC_GENERAL_CFG_DFLE));
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| 			break;
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| 
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| 		case DC_DISPLAY_CFG:
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| 			/* write without the enables */
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| 			write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
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| 					DC_DISPLAY_CFG_GDEN |
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| 					DC_DISPLAY_CFG_TGEN));
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| 			break;
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| 
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| 		case DC_RSVD_0:
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| 		case DC_RSVD_1:
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| 		case DC_RSVD_2:
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| 		case DC_RSVD_3:
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| 		case DC_RSVD_4:
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| 		case DC_LINE_CNT:
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| 		case DC_PAL_ADDRESS:
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| 		case DC_PAL_DATA:
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| 		case DC_DFIFO_DIAG:
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| 		case DC_CFIFO_DIAG:
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| 		case DC_RSVD_5:
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| 			/* don't restore these registers */
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| 			break;
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| 		default:
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| 			write_dc(par, i, par->dc[i]);
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| 		}
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| 	}
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| 
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| 	/* restore the palette */
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| 	write_dc(par, DC_PAL_ADDRESS, 0);
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| 	for (i = 0; i < ARRAY_SIZE(par->pal); i++)
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| 		write_dc(par, DC_PAL_DATA, par->pal[i]);
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| }
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| 
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| static void gx_restore_video_proc(struct gxfb_par *par)
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| {
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| 	int i;
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| 
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| 	wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
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| 
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| 	for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
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| 		switch (i) {
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| 		case VP_VCFG:
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| 			/* don't enable video yet */
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| 			write_vp(par, i, par->vp[i] & ~VP_VCFG_VID_EN);
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| 			break;
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| 
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| 		case VP_DCFG:
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| 			/* don't enable CRT yet */
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| 			write_vp(par, i, par->vp[i] &
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| 					~(VP_DCFG_DAC_BL_EN | VP_DCFG_VSYNC_EN |
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| 					VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
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| 			break;
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| 
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| 		case VP_GAR:
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| 		case VP_GDR:
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| 		case VP_RSVD_0:
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| 		case VP_RSVD_1:
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| 		case VP_RSVD_2:
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| 		case VP_RSVD_3:
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| 		case VP_CRC32:
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| 		case VP_AWT:
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| 		case VP_VTM:
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| 			/* don't restore these registers */
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| 			break;
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| 		default:
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| 			write_vp(par, i, par->vp[i]);
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| 		}
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| 	}
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| }
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| 
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| static void gx_restore_regs(struct gxfb_par *par)
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| {
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| 	int i;
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| 
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| 	gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32));
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| 	gx_restore_gfx_proc(par);
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| 	gx_restore_display_ctlr(par);
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| 	gx_restore_video_proc(par);
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| 
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| 	/* Flat Panel */
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| 	for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
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| 		if (i != FP_PM && i != FP_RSVD_0)
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| 			write_fp(par, i, par->fp[i]);
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| 	}
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| }
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| 
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| static void gx_disable_graphics(struct gxfb_par *par)
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| {
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| 	/* shut down the engine */
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| 	write_vp(par, VP_VCFG, par->vp[VP_VCFG] & ~VP_VCFG_VID_EN);
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| 	write_vp(par, VP_DCFG, par->vp[VP_DCFG] & ~(VP_DCFG_DAC_BL_EN |
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| 			VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
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| 
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| 	/* turn off the flat panel */
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| 	write_fp(par, FP_PM, par->fp[FP_PM] & ~FP_PM_P);
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| 
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| 
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| 	/* turn off display */
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| 	write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
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| 	write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
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| 			~(DC_GENERAL_CFG_VIDE | DC_GENERAL_CFG_ICNE |
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| 			DC_GENERAL_CFG_CURE | DC_GENERAL_CFG_DFLE));
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| 	write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
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| 			~(DC_DISPLAY_CFG_VDEN | DC_DISPLAY_CFG_GDEN |
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| 			DC_DISPLAY_CFG_TGEN));
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| 	write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
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| }
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| 
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| static void gx_enable_graphics(struct gxfb_par *par)
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| {
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| 	uint32_t fp;
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| 
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| 	fp = read_fp(par, FP_PM);
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| 	if (par->fp[FP_PM] & FP_PM_P) {
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| 		/* power on the panel if not already power{ed,ing} on */
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| 		if (!(fp & (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
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| 			write_fp(par, FP_PM, par->fp[FP_PM]);
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| 	} else {
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| 		/* power down the panel if not already power{ed,ing} down */
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| 		if (!(fp & (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
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| 			write_fp(par, FP_PM, par->fp[FP_PM]);
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| 	}
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| 
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| 	/* turn everything on */
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| 	write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
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| 	write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
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| 	write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
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| 	/* do this last; it will enable the FIFO load */
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| 	write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
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| 
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| 	/* lock the door behind us */
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| 	write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
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| }
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| 
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| int gx_powerdown(struct fb_info *info)
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| {
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| 	struct gxfb_par *par = info->par;
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| 
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| 	if (par->powered_down)
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| 		return 0;
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| 
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| 	gx_save_regs(par);
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| 	gx_disable_graphics(par);
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| 
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| 	par->powered_down = 1;
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| 	return 0;
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| }
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| 
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| int gx_powerup(struct fb_info *info)
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| {
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| 	struct gxfb_par *par = info->par;
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| 
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| 	if (!par->powered_down)
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| 		return 0;
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| 
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| 	gx_restore_regs(par);
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| 	gx_enable_graphics(par);
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| 
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| 	par->powered_down  = 0;
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| 	return 0;
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| }
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| 
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| #endif
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