215 lines
5.8 KiB
C
215 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2001, 2002, 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Keith Outwater, keith_outwater@mvis.com`
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* Steven Scholz, steven.scholz@imc-berlin.de
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*/
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/*
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* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
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* DS1374 Real Time Clock (RTC).
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*
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* based on ds1337.c
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*/
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#include <common.h>
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#include <command.h>
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#include <rtc.h>
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#include <i2c.h>
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/*---------------------------------------------------------------------*/
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#undef DEBUG_RTC
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#define DEBUG_RTC
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#ifdef DEBUG_RTC
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#define DEBUGR(fmt,args...) printf(fmt ,##args)
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#else
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#define DEBUGR(fmt,args...)
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#endif
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/*---------------------------------------------------------------------*/
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#ifndef CONFIG_SYS_I2C_RTC_ADDR
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# define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#endif
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#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
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# error The DS1374 is specified up to 400kHz in fast mode!
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#endif
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/*
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* RTC register addresses
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*/
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#define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
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#define RTC_TOD_CNT_BYTE1_ADDR 0x01
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#define RTC_TOD_CNT_BYTE2_ADDR 0x02
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#define RTC_TOD_CNT_BYTE3_ADDR 0x03
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#define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
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#define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
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#define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
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#define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
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#define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
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#define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
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#define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
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#define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
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#define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
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#define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
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#define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
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#define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
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#define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
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#define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
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#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
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#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
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const char RtcTodAddr[] = {
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RTC_TOD_CNT_BYTE0_ADDR,
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RTC_TOD_CNT_BYTE1_ADDR,
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RTC_TOD_CNT_BYTE2_ADDR,
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RTC_TOD_CNT_BYTE3_ADDR
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};
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static uchar rtc_read (uchar reg);
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static void rtc_write(uchar reg, uchar val, bool set);
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static void rtc_write_raw (uchar reg, uchar val);
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/*
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* Get the current time from the RTC
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*/
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int rtc_get (struct rtc_time *tm){
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int rel = 0;
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unsigned long time1, time2;
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unsigned int limit;
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unsigned char tmp;
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unsigned int i;
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/*
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* Since the reads are being performed one byte at a time,
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* there is a chance that a carry will occur during the read.
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* To detect this, 2 reads are performed and compared.
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*/
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limit = 10;
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do {
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i = 4;
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time1 = 0;
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while (i--) {
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tmp = rtc_read(RtcTodAddr[i]);
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time1 = (time1 << 8) | (tmp & 0xff);
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}
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i = 4;
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time2 = 0;
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while (i--) {
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tmp = rtc_read(RtcTodAddr[i]);
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time2 = (time2 << 8) | (tmp & 0xff);
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}
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} while ((time1 != time2) && limit--);
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if (time1 != time2) {
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printf("can't get consistent time from rtc chip\n");
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rel = -1;
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}
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DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
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rtc_to_tm(time1, tm); /* To Gregorian Date */
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if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
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printf ("### Warning: RTC oscillator has stopped\n");
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rel = -1;
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}
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DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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return rel;
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}
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/*
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* Set the RTC
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*/
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int rtc_set (struct rtc_time *tmp){
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unsigned long time;
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unsigned i;
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DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
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printf("WARNING: year should be between 1970 and 2069!\n");
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time = rtc_mktime(tmp);
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DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
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/* write to RTC_TOD_CNT_BYTEn_ADDR */
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for (i = 0; i <= 3; i++) {
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rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
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time = time >> 8;
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}
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/* Start clock */
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rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
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return 0;
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}
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/*
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* Reset the RTC. We setting the date back to 1970-01-01.
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* We also enable the oscillator output on the SQW/OUT pin and program
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* it for 32,768 Hz output. Note that according to the datasheet, turning
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* on the square wave output increases the current drain on the backup
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* battery to something between 480nA and 800nA.
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*/
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void rtc_reset (void){
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/* clear status flags */
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rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
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/* Initialise DS1374 oriented to MPC8349E-ADS */
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rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
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|RTC_CTL_BIT_WACE
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|RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
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- set to 0 */
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rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
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|RTC_CTL_BIT_WDSTR
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|RTC_CTL_BIT_RS1
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|RTC_CTL_BIT_RS2
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|RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
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set BBSQW and SQW to 32k
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- set to 1 */
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rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
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rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
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rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
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}
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/*
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* Helper functions
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*/
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static uchar rtc_read (uchar reg)
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{
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return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
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}
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static void rtc_write(uchar reg, uchar val, bool set)
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{
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if (set == true) {
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val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
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i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
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} else {
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val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
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i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
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}
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}
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static void rtc_write_raw (uchar reg, uchar val)
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{
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i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
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}
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