462 lines
11 KiB
C
462 lines
11 KiB
C
/*
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* Shared support code for AMD K8 northbridges and derivates.
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* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/spinlock.h>
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#include <asm/amd_nb.h>
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#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
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#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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/* Protect the PCI config register pairs used for SMN and DF indirect access. */
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static DEFINE_MUTEX(smn_mutex);
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static u32 *flush_words;
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static const struct pci_device_id amd_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
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{}
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};
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#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
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const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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{}
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};
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EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
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static const struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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{ 0xfe, 0x00, 0x20 },
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{ }
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};
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static struct amd_northbridge_info amd_northbridges;
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u16 amd_nb_num(void)
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{
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return amd_northbridges.num;
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}
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EXPORT_SYMBOL_GPL(amd_nb_num);
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bool amd_nb_has_feature(unsigned int feature)
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{
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return ((amd_northbridges.flags & feature) == feature);
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}
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EXPORT_SYMBOL_GPL(amd_nb_has_feature);
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struct amd_northbridge *node_to_amd_nb(int node)
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{
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return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
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}
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EXPORT_SYMBOL_GPL(node_to_amd_nb);
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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const struct pci_device_id *ids)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(ids, dev));
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return dev;
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}
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static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
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{
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struct pci_dev *root;
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int err = -ENODEV;
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if (node >= amd_northbridges.num)
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goto out;
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root = node_to_amd_nb(node)->root;
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if (!root)
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goto out;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(root, 0x60, address);
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if (err) {
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pr_warn("Error programming SMN address 0x%x.\n", address);
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goto out_unlock;
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}
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err = (write ? pci_write_config_dword(root, 0x64, *value)
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: pci_read_config_dword(root, 0x64, value));
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if (err)
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pr_warn("Error %s SMN address 0x%x.\n",
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(write ? "writing to" : "reading from"), address);
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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int amd_smn_read(u16 node, u32 address, u32 *value)
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{
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return __amd_smn_rw(node, address, value, false);
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}
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EXPORT_SYMBOL_GPL(amd_smn_read);
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int amd_smn_write(u16 node, u32 address, u32 value)
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{
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return __amd_smn_rw(node, address, &value, true);
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}
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EXPORT_SYMBOL_GPL(amd_smn_write);
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/*
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* Data Fabric Indirect Access uses FICAA/FICAD.
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*
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* Fabric Indirect Configuration Access Address (FICAA): Constructed based
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* on the device's Instance Id and the PCI function and register offset of
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* the desired register.
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*
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* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
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* and FICAD HI registers but so far we only need the LO register.
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*/
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int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
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{
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struct pci_dev *F4;
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u32 ficaa;
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int err = -ENODEV;
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if (node >= amd_northbridges.num)
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goto out;
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F4 = node_to_amd_nb(node)->link;
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if (!F4)
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goto out;
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ficaa = 1;
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ficaa |= reg & 0x3FC;
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ficaa |= (func & 0x7) << 11;
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ficaa |= instance_id << 16;
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mutex_lock(&smn_mutex);
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err = pci_write_config_dword(F4, 0x5C, ficaa);
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if (err) {
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pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
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goto out_unlock;
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}
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err = pci_read_config_dword(F4, 0x98, lo);
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if (err)
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pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
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out_unlock:
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mutex_unlock(&smn_mutex);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(amd_df_indirect_read);
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int amd_cache_northbridges(void)
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{
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u16 i = 0;
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struct amd_northbridge *nb;
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struct pci_dev *root, *misc, *link;
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if (amd_northbridges.num)
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return 0;
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misc = NULL;
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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i++;
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if (!i)
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return -ENODEV;
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nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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return -ENOMEM;
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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link = misc = root = NULL;
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for (i = 0; i != amd_northbridges.num; i++) {
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node_to_amd_nb(i)->root = root =
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next_northbridge(root, amd_root_ids);
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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}
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if (amd_gart_present())
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amd_northbridges.flags |= AMD_NB_GART;
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/*
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* Check for L3 cache presence.
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*/
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if (!cpuid_edx(0x80000006))
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return 0;
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/*
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* Some CPU families support L3 Cache Index Disable. There are some
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* limitations because of E382 and E388 on family 0x10.
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*/
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model >= 0x8 &&
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(boot_cpu_data.x86_model > 0x9 ||
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boot_cpu_data.x86_stepping >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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/* L3 cache partitioning is supported on family 0x15 */
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
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return 0;
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}
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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/*
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* Ignores subdevice/subvendor but as far as I can figure out
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* they're useless anyways
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*/
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bool __init early_is_amd_nb(u32 device)
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{
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const struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = amd_nb_misc_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return true;
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return false;
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}
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struct resource *amd_get_mmconfig_range(struct resource *res)
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{
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u32 address;
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u64 base, msr;
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unsigned int segn_busn_bits;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return NULL;
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/* assume all cpus from fam10h have mmconfig */
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if (boot_cpu_data.x86 < 0x10)
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return NULL;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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rdmsrl(address, msr);
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/* mmconfig is not enabled */
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if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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return NULL;
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base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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res->flags = IORESOURCE_MEM;
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res->start = base;
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res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
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return res;
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}
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int amd_get_subcaches(int cpu)
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{
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struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
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unsigned int mask;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return 0;
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pci_read_config_dword(link, 0x1d4, &mask);
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return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
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}
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int amd_set_subcaches(int cpu, unsigned long mask)
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{
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static unsigned int reset, ban;
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struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
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unsigned int reg;
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int cuid;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
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return -EINVAL;
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/* if necessary, collect reset state of L3 partitioning and BAN mode */
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if (reset == 0) {
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pci_read_config_dword(nb->link, 0x1d4, &reset);
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pci_read_config_dword(nb->misc, 0x1b8, &ban);
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ban &= 0x180000;
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}
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/* deactivate BAN mode if any subcaches are to be disabled */
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if (mask != 0xf) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
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}
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cuid = cpu_data(cpu).cpu_core_id;
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mask <<= 4 * cuid;
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mask |= (0xf ^ (1 << cuid)) << 26;
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pci_write_config_dword(nb->link, 0x1d4, mask);
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/* reset BAN mode if L3 partitioning returned to reset state */
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pci_read_config_dword(nb->link, 0x1d4, ®);
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if (reg == reset) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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reg &= ~0x180000;
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pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
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}
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return 0;
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}
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static void amd_cache_gart(void)
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{
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u16 i;
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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amd_northbridges.flags &= ~AMD_NB_GART;
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pr_notice("Cannot initialize GART flush words, GART support disabled\n");
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return;
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}
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for (i = 0; i != amd_northbridges.num; i++)
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pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
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}
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void amd_flush_garts(void)
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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if (!amd_nb_has_feature(AMD_NB_GART))
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return;
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/*
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* Avoid races between AGP and IOMMU. In theory it's not needed
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* but I'm not sure if the hardware won't lose flush requests
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* when another is pending. This whole thing is so expensive anyways
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* that it doesn't matter to serialize more. -AK
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*/
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < amd_northbridges.num; i++) {
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pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
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flush_words[i] | 1);
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flushed++;
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}
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for (i = 0; i < amd_northbridges.num; i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(node_to_amd_nb(i)->misc,
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0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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spin_unlock_irqrestore(&gart_lock, flags);
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if (!flushed)
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pr_notice("nothing to flush?\n");
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}
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EXPORT_SYMBOL_GPL(amd_flush_garts);
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static void __fix_erratum_688(void *info)
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{
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#define MSR_AMD64_IC_CFG 0xC0011021
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msr_set_bit(MSR_AMD64_IC_CFG, 3);
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msr_set_bit(MSR_AMD64_IC_CFG, 14);
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}
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/* Apply erratum 688 fix so machines without a BIOS fix work. */
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static __init void fix_erratum_688(void)
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{
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struct pci_dev *F4;
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u32 val;
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if (boot_cpu_data.x86 != 0x14)
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return;
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if (!amd_northbridges.num)
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return;
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F4 = node_to_amd_nb(0)->link;
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if (!F4)
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return;
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if (pci_read_config_dword(F4, 0x164, &val))
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return;
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if (val & BIT(2))
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return;
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on_each_cpu(__fix_erratum_688, NULL, 0);
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pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
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}
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static __init int init_amd_nbs(void)
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{
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amd_cache_northbridges();
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amd_cache_gart();
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fix_erratum_688();
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return 0;
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}
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/* This has to go after the PCI subsystem */
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fs_initcall(init_amd_nbs);
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