1303 lines
		
	
	
		
			34 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			1303 lines
		
	
	
		
			34 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
 | |
| /*
 | |
|  * This dts file supports Dalmore A04.
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|  * Other board revisions are not supported
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|  */
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| 
 | |
| /dts-v1/;
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| 
 | |
| #include <dt-bindings/input/input.h>
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| #include "tegra114.dtsi"
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| 
 | |
| / {
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| 	model = "NVIDIA Tegra114 Dalmore evaluation board";
 | |
| 	compatible = "nvidia,dalmore", "nvidia,tegra114";
 | |
| 
 | |
| 	aliases {
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| 		rtc0 = "/i2c@7000d000/tps65913@58";
 | |
| 		rtc1 = "/rtc@7000e000";
 | |
| 		serial0 = &uartd;
 | |
| 	};
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| 
 | |
| 	chosen {
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| 		stdout-path = "serial0:115200n8";
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| 	};
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| 
 | |
| 	memory@80000000 {
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| 		reg = <0x80000000 0x40000000>;
 | |
| 	};
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| 
 | |
| 	host1x@50000000 {
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| 		hdmi@54280000 {
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| 			status = "okay";
 | |
| 
 | |
| 			hdmi-supply = <&vdd_5v0_hdmi>;
 | |
| 			vdd-supply = <&vdd_hdmi_reg>;
 | |
| 			pll-supply = <&palmas_smps3_reg>;
 | |
| 
 | |
| 			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
 | |
| 			nvidia,hpd-gpio =
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| 				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
 | |
| 		};
 | |
| 
 | |
| 		dsi@54300000 {
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| 			status = "okay";
 | |
| 
 | |
| 			avdd-dsi-csi-supply = <&avdd_1v2_reg>;
 | |
| 
 | |
| 			panel@0 {
 | |
| 				compatible = "panasonic,vvx10f004b00",
 | |
| 					     "simple-panel";
 | |
| 				reg = <0>;
 | |
| 
 | |
| 				power-supply = <&avdd_lcd_reg>;
 | |
| 				backlight = <&backlight>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	pinmux@70000868 {
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| 		pinctrl-names = "default";
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| 		pinctrl-0 = <&state_default>;
 | |
| 
 | |
| 		state_default: pinmux {
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| 			clk1_out_pw4 {
 | |
| 				nvidia,pins = "clk1_out_pw4";
 | |
| 				nvidia,function = "extperiph1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap1_din_pn1 {
 | |
| 				nvidia,pins = "dap1_din_pn1";
 | |
| 				nvidia,function = "i2s0";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap1_dout_pn2 {
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| 				nvidia,pins = "dap1_dout_pn2",
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| 						"dap1_fs_pn0",
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| 						"dap1_sclk_pn3";
 | |
| 				nvidia,function = "i2s0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap2_din_pa4 {
 | |
| 				nvidia,pins = "dap2_din_pa4";
 | |
| 				nvidia,function = "i2s1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap2_dout_pa5 {
 | |
| 				nvidia,pins = "dap2_dout_pa5",
 | |
| 						"dap2_fs_pa2",
 | |
| 						"dap2_sclk_pa3";
 | |
| 				nvidia,function = "i2s1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap4_din_pp5 {
 | |
| 				nvidia,pins = "dap4_din_pp5",
 | |
| 						"dap4_dout_pp6",
 | |
| 						"dap4_fs_pp4",
 | |
| 						"dap4_sclk_pp7";
 | |
| 				nvidia,function = "i2s3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dvfs_pwm_px0 {
 | |
| 				nvidia,pins = "dvfs_pwm_px0",
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| 						"dvfs_clk_px2";
 | |
| 				nvidia,function = "cldvfs";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_clk_py0 {
 | |
| 				nvidia,pins = "ulpi_clk_py0",
 | |
| 						"ulpi_data0_po1",
 | |
| 						"ulpi_data1_po2",
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| 						"ulpi_data2_po3",
 | |
| 						"ulpi_data3_po4",
 | |
| 						"ulpi_data4_po5",
 | |
| 						"ulpi_data5_po6",
 | |
| 						"ulpi_data6_po7",
 | |
| 						"ulpi_data7_po0";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			ulpi_dir_py1 {
 | |
| 				nvidia,pins = "ulpi_dir_py1",
 | |
| 						"ulpi_nxt_py2";
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| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			ulpi_stp_py3 {
 | |
| 				nvidia,pins = "ulpi_stp_py3";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cam_i2c_scl_pbb1 {
 | |
| 				nvidia,pins = "cam_i2c_scl_pbb1",
 | |
| 						"cam_i2c_sda_pbb2";
 | |
| 				nvidia,function = "i2c3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cam_mclk_pcc0 {
 | |
| 				nvidia,pins = "cam_mclk_pcc0",
 | |
| 						"pbb0";
 | |
| 				nvidia,function = "vi_alt3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gen2_i2c_scl_pt5 {
 | |
| 				nvidia,pins = "gen2_i2c_scl_pt5",
 | |
| 						"gen2_i2c_sda_pt6";
 | |
| 				nvidia,function = "i2c2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gmi_a16_pj7 {
 | |
| 				nvidia,pins = "gmi_a16_pj7";
 | |
| 				nvidia,function = "uartd";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gmi_a17_pb0 {
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| 				nvidia,pins = "gmi_a17_pb0",
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| 						"gmi_a18_pb1";
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| 				nvidia,function = "uartd";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			gmi_a19_pk7 {
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| 				nvidia,pins = "gmi_a19_pk7";
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| 				nvidia,function = "uartd";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
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| 			gmi_ad5_pg5 {
 | |
| 				nvidia,pins = "gmi_ad5_pg5",
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| 						"gmi_cs6_n_pi3",
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| 						"gmi_wr_n_pi0";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			gmi_ad6_pg6 {
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| 				nvidia,pins = "gmi_ad6_pg6",
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| 						"gmi_ad7_pg7";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			gmi_ad12_ph4 {
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| 				nvidia,pins = "gmi_ad12_ph4";
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| 				nvidia,function = "rsvd4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			gmi_ad9_ph1 {
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| 				nvidia,pins = "gmi_ad9_ph1";
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| 				nvidia,function = "pwm1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			gmi_cs1_n_pj2 {
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| 				nvidia,pins = "gmi_cs1_n_pj2",
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| 						"gmi_oe_n_pi1";
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| 				nvidia,function = "soc";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			clk2_out_pw5 {
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| 				nvidia,pins = "clk2_out_pw5";
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| 				nvidia,function = "extperiph2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc1_clk_pz0 {
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| 				nvidia,pins = "sdmmc1_clk_pz0";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_cmd_pz1 {
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| 				nvidia,pins = "sdmmc1_cmd_pz1",
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| 						"sdmmc1_dat0_py7",
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| 						"sdmmc1_dat1_py6",
 | |
| 						"sdmmc1_dat2_py5",
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| 						"sdmmc1_dat3_py4";
 | |
| 				nvidia,function = "sdmmc1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_wp_n_pv3 {
 | |
| 				nvidia,pins = "sdmmc1_wp_n_pv3";
 | |
| 				nvidia,function = "spi4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc3_clk_pa6 {
 | |
| 				nvidia,pins = "sdmmc3_clk_pa6";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc3_cmd_pa7 {
 | |
| 				nvidia,pins = "sdmmc3_cmd_pa7",
 | |
| 						"sdmmc3_dat0_pb7",
 | |
| 						"sdmmc3_dat1_pb6",
 | |
| 						"sdmmc3_dat2_pb5",
 | |
| 						"sdmmc3_dat3_pb4",
 | |
| 						"kb_col4_pq4",
 | |
| 						"sdmmc3_clk_lb_out_pee4",
 | |
| 						"sdmmc3_clk_lb_in_pee5";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_clk_pcc4 {
 | |
| 				nvidia,pins = "sdmmc4_clk_pcc4";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_cmd_pt7 {
 | |
| 				nvidia,pins = "sdmmc4_cmd_pt7",
 | |
| 						"sdmmc4_dat0_paa0",
 | |
| 						"sdmmc4_dat1_paa1",
 | |
| 						"sdmmc4_dat2_paa2",
 | |
| 						"sdmmc4_dat3_paa3",
 | |
| 						"sdmmc4_dat4_paa4",
 | |
| 						"sdmmc4_dat5_paa5",
 | |
| 						"sdmmc4_dat6_paa6",
 | |
| 						"sdmmc4_dat7_paa7";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			clk_32k_out_pa0 {
 | |
| 				nvidia,pins = "clk_32k_out_pa0";
 | |
| 				nvidia,function = "blink";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col0_pq0 {
 | |
| 				nvidia,pins = "kb_col0_pq0",
 | |
| 						"kb_col1_pq1",
 | |
| 						"kb_col2_pq2",
 | |
| 						"kb_row0_pr0",
 | |
| 						"kb_row1_pr1",
 | |
| 						"kb_row2_pr2";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap3_din_pp1 {
 | |
| 				nvidia,pins = "dap3_din_pp1",
 | |
| 						"dap3_sclk_pp3";
 | |
| 				nvidia,function = "displayb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pv0 {
 | |
| 				nvidia,pins = "pv0";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row7_pr7 {
 | |
| 				nvidia,pins = "kb_row7_pr7";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row10_ps2 {
 | |
| 				nvidia,pins = "kb_row10_ps2";
 | |
| 				nvidia,function = "uarta";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row9_ps1 {
 | |
| 				nvidia,pins = "kb_row9_ps1";
 | |
| 				nvidia,function = "uarta";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pwr_i2c_scl_pz6 {
 | |
| 				nvidia,pins = "pwr_i2c_scl_pz6",
 | |
| 						"pwr_i2c_sda_pz7";
 | |
| 				nvidia,function = "i2cpwr";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sys_clk_req_pz5 {
 | |
| 				nvidia,pins = "sys_clk_req_pz5";
 | |
| 				nvidia,function = "sysclk";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			core_pwr_req {
 | |
| 				nvidia,pins = "core_pwr_req";
 | |
| 				nvidia,function = "pwron";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cpu_pwr_req {
 | |
| 				nvidia,pins = "cpu_pwr_req";
 | |
| 				nvidia,function = "cpu";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pwr_int_n {
 | |
| 				nvidia,pins = "pwr_int_n";
 | |
| 				nvidia,function = "pmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			reset_out_n {
 | |
| 				nvidia,pins = "reset_out_n";
 | |
| 				nvidia,function = "reset_out_n";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk3_out_pee0 {
 | |
| 				nvidia,pins = "clk3_out_pee0";
 | |
| 				nvidia,function = "extperiph3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gen1_i2c_scl_pc4 {
 | |
| 				nvidia,pins = "gen1_i2c_scl_pc4",
 | |
| 						"gen1_i2c_sda_pc5";
 | |
| 				nvidia,function = "i2c1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart2_cts_n_pj5 {
 | |
| 				nvidia,pins = "uart2_cts_n_pj5";
 | |
| 				nvidia,function = "uartb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			uart2_rts_n_pj6 {
 | |
| 				nvidia,pins = "uart2_rts_n_pj6";
 | |
| 				nvidia,function = "uartb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart2_rxd_pc3 {
 | |
| 				nvidia,pins = "uart2_rxd_pc3";
 | |
| 				nvidia,function = "irda";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			uart2_txd_pc2 {
 | |
| 				nvidia,pins = "uart2_txd_pc2";
 | |
| 				nvidia,function = "irda";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart3_cts_n_pa1 {
 | |
| 				nvidia,pins = "uart3_cts_n_pa1",
 | |
| 						"uart3_rxd_pw7";
 | |
| 				nvidia,function = "uartc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			uart3_rts_n_pc0 {
 | |
| 				nvidia,pins = "uart3_rts_n_pc0",
 | |
| 						"uart3_txd_pw6";
 | |
| 				nvidia,function = "uartc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			owr {
 | |
| 				nvidia,pins = "owr";
 | |
| 				nvidia,function = "owr";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			hdmi_cec_pee3 {
 | |
| 				nvidia,pins = "hdmi_cec_pee3";
 | |
| 				nvidia,function = "cec";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ddc_scl_pv4 {
 | |
| 				nvidia,pins = "ddc_scl_pv4",
 | |
| 						"ddc_sda_pv5";
 | |
| 				nvidia,function = "i2c4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			spdif_in_pk6 {
 | |
| 				nvidia,pins = "spdif_in_pk6";
 | |
| 				nvidia,function = "usb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			usb_vbus_en0_pn4 {
 | |
| 				nvidia,pins = "usb_vbus_en0_pn4";
 | |
| 				nvidia,function = "usb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,lock = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_x6_aud_px6 {
 | |
| 				nvidia,pins = "gpio_x6_aud_px6";
 | |
| 				nvidia,function = "spi6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_x4_aud_px4 {
 | |
| 				nvidia,pins = "gpio_x4_aud_px4",
 | |
| 						"gpio_x7_aud_px7";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x5_aud_px5 {
 | |
| 				nvidia,pins = "gpio_x5_aud_px5";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_w2_aud_pw2 {
 | |
| 				nvidia,pins = "gpio_w2_aud_pw2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_w3_aud_pw3 {
 | |
| 				nvidia,pins = "gpio_w3_aud_pw3";
 | |
| 				nvidia,function = "spi6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_x1_aud_px1 {
 | |
| 				nvidia,pins = "gpio_x1_aud_px1";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_x3_aud_px3 {
 | |
| 				nvidia,pins = "gpio_x3_aud_px3";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap3_fs_pp0 {
 | |
| 				nvidia,pins = "dap3_fs_pp0";
 | |
| 				nvidia,function = "i2s2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap3_dout_pp2 {
 | |
| 				nvidia,pins = "dap3_dout_pp2";
 | |
| 				nvidia,function = "i2s2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pv1 {
 | |
| 				nvidia,pins = "pv1";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pbb3 {
 | |
| 				nvidia,pins = "pbb3",
 | |
| 						"pbb5",
 | |
| 						"pbb6",
 | |
| 						"pbb7";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pcc1 {
 | |
| 				nvidia,pins = "pcc1",
 | |
| 						"pcc2";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gmi_ad0_pg0 {
 | |
| 				nvidia,pins = "gmi_ad0_pg0",
 | |
| 						"gmi_ad1_pg1";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gmi_ad10_ph2 {
 | |
| 				nvidia,pins = "gmi_ad10_ph2",
 | |
| 						"gmi_ad11_ph3",
 | |
| 						"gmi_ad13_ph5",
 | |
| 						"gmi_ad8_ph0",
 | |
| 						"gmi_clk_pk1";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gmi_ad2_pg2 {
 | |
| 				nvidia,pins = "gmi_ad2_pg2",
 | |
| 						"gmi_ad3_pg3";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gmi_adv_n_pk0 {
 | |
| 				nvidia,pins = "gmi_adv_n_pk0",
 | |
| 						"gmi_cs0_n_pj0",
 | |
| 						"gmi_cs2_n_pk3",
 | |
| 						"gmi_cs4_n_pk2",
 | |
| 						"gmi_cs7_n_pi6",
 | |
| 						"gmi_dqs_p_pj3",
 | |
| 						"gmi_iordy_pi5",
 | |
| 						"gmi_wp_n_pc7";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gmi_cs3_n_pk4 {
 | |
| 				nvidia,pins = "gmi_cs3_n_pk4";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk2_req_pcc5 {
 | |
| 				nvidia,pins = "clk2_req_pcc5";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col3_pq3 {
 | |
| 				nvidia,pins = "kb_col3_pq3",
 | |
| 						"kb_col6_pq6",
 | |
| 						"kb_col7_pq7";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col5_pq5 {
 | |
| 				nvidia,pins = "kb_col5_pq5";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row3_pr3 {
 | |
| 				nvidia,pins = "kb_row3_pr3",
 | |
| 						"kb_row4_pr4",
 | |
| 						"kb_row6_pr6",
 | |
| 						"kb_row8_ps0";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			clk3_req_pee1 {
 | |
| 				nvidia,pins = "clk3_req_pee1";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu4 {
 | |
| 				nvidia,pins = "pu4";
 | |
| 				nvidia,function = "displayb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu5 {
 | |
| 				nvidia,pins = "pu5",
 | |
| 						"pu6";
 | |
| 				nvidia,function = "displayb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			hdmi_int_pn7 {
 | |
| 				nvidia,pins = "hdmi_int_pn7";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			clk1_req_pee2 {
 | |
| 				nvidia,pins = "clk1_req_pee2",
 | |
| 						"usb_vbus_en1_pn5";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 
 | |
| 			drive_sdio1 {
 | |
| 				nvidia,pins = "drive_sdio1";
 | |
| 				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,pull-down-strength = <36>;
 | |
| 				nvidia,pull-up-strength = <20>;
 | |
| 				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
 | |
| 				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
 | |
| 			};
 | |
| 			drive_sdio3 {
 | |
| 				nvidia,pins = "drive_sdio3";
 | |
| 				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,pull-down-strength = <22>;
 | |
| 				nvidia,pull-up-strength = <36>;
 | |
| 				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 | |
| 				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 | |
| 			};
 | |
| 			drive_gma {
 | |
| 				nvidia,pins = "drive_gma";
 | |
| 				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,pull-down-strength = <2>;
 | |
| 				nvidia,pull-up-strength = <1>;
 | |
| 				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 | |
| 				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	serial@70006300 {
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	pwm@7000a000 {
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	i2c@7000c000 {
 | |
| 		status = "okay";
 | |
| 		clock-frequency = <100000>;
 | |
| 
 | |
| 		battery: smart-battery@b {
 | |
| 			compatible = "ti,bq20z45", "sbs,sbs-battery";
 | |
| 			reg = <0xb>;
 | |
| 			battery-name = "battery";
 | |
| 			sbs,i2c-retry-count = <2>;
 | |
| 			sbs,poll-retry-count = <100>;
 | |
| 			power-supplies = <&charger>;
 | |
| 		};
 | |
| 
 | |
| 		rt5640: rt5640@1c {
 | |
| 			compatible = "realtek,rt5640";
 | |
| 			reg = <0x1c>;
 | |
| 			interrupt-parent = <&gpio>;
 | |
| 			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
 | |
| 			realtek,ldo1-en-gpios =
 | |
| 				<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
 | |
| 		};
 | |
| 
 | |
| 		temperature-sensor@4c {
 | |
| 			compatible = "onnn,nct1008";
 | |
| 			reg = <0x4c>;
 | |
| 			vcc-supply = <&palmas_ldo6_reg>;
 | |
| 			interrupt-parent = <&gpio>;
 | |
| 			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	hdmi_ddc: i2c@7000c700 {
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	i2c@7000d000 {
 | |
| 		status = "okay";
 | |
| 		clock-frequency = <400000>;
 | |
| 
 | |
| 		tps51632@43 {
 | |
| 			compatible = "ti,tps51632";
 | |
| 			reg = <0x43>;
 | |
| 			regulator-name = "vdd-cpu";
 | |
| 			regulator-min-microvolt = <500000>;
 | |
| 			regulator-max-microvolt = <1520000>;
 | |
| 			regulator-boot-on;
 | |
| 			regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		tps65090@48 {
 | |
| 			compatible = "ti,tps65090";
 | |
| 			reg = <0x48>;
 | |
| 			interrupt-parent = <&gpio>;
 | |
| 			interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
 | |
| 
 | |
| 			vsys1-supply = <&vdd_ac_bat_reg>;
 | |
| 			vsys2-supply = <&vdd_ac_bat_reg>;
 | |
| 			vsys3-supply = <&vdd_ac_bat_reg>;
 | |
| 			infet1-supply = <&vdd_ac_bat_reg>;
 | |
| 			infet2-supply = <&vdd_ac_bat_reg>;
 | |
| 			infet3-supply = <&tps65090_dcdc2_reg>;
 | |
| 			infet4-supply = <&tps65090_dcdc2_reg>;
 | |
| 			infet5-supply = <&tps65090_dcdc2_reg>;
 | |
| 			infet6-supply = <&tps65090_dcdc2_reg>;
 | |
| 			infet7-supply = <&tps65090_dcdc2_reg>;
 | |
| 			vsys-l1-supply = <&vdd_ac_bat_reg>;
 | |
| 			vsys-l2-supply = <&vdd_ac_bat_reg>;
 | |
| 
 | |
| 			charger: charger {
 | |
| 				compatible = "ti,tps65090-charger";
 | |
| 				ti,enable-low-current-chrg;
 | |
| 			};
 | |
| 
 | |
| 			regulators {
 | |
| 				tps65090_dcdc1_reg: dcdc1 {
 | |
| 					regulator-name = "vdd-sys-5v0";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 
 | |
| 				tps65090_dcdc2_reg: dcdc2 {
 | |
| 					regulator-name = "vdd-sys-3v3";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 
 | |
| 				tps65090_dcdc3_reg: dcdc3 {
 | |
| 					regulator-name = "vdd-ao";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 
 | |
| 				vdd_bl_reg: fet1 {
 | |
| 					regulator-name = "vdd-lcd-bl";
 | |
| 				};
 | |
| 
 | |
| 				fet3 {
 | |
| 					regulator-name = "vdd-modem-3v3";
 | |
| 				};
 | |
| 
 | |
| 				avdd_lcd_reg: fet4 {
 | |
| 					regulator-name = "avdd-lcd";
 | |
| 				};
 | |
| 
 | |
| 				fet5 {
 | |
| 					regulator-name = "vdd-lvds";
 | |
| 				};
 | |
| 
 | |
| 				fet6 {
 | |
| 					regulator-name = "vdd-sd-slot";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 
 | |
| 				fet7 {
 | |
| 					regulator-name = "vdd-com-3v3";
 | |
| 				};
 | |
| 
 | |
| 				ldo1 {
 | |
| 					regulator-name = "vdd-sby-5v0";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 
 | |
| 				ldo2 {
 | |
| 					regulator-name = "vdd-sby-3v3";
 | |
| 					regulator-always-on;
 | |
| 					regulator-boot-on;
 | |
| 				};
 | |
| 			};
 | |
| 		};
 | |
| 
 | |
| 		palmas: tps65913@58 {
 | |
| 			compatible = "ti,palmas";
 | |
| 			reg = <0x58>;
 | |
| 			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 | |
| 
 | |
| 			#interrupt-cells = <2>;
 | |
| 			interrupt-controller;
 | |
| 
 | |
| 			ti,system-power-controller;
 | |
| 
 | |
| 			palmas_gpio: gpio {
 | |
| 				compatible = "ti,palmas-gpio";
 | |
| 				gpio-controller;
 | |
| 				#gpio-cells = <2>;
 | |
| 			};
 | |
| 
 | |
| 			pmic {
 | |
| 				compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
 | |
| 				smps1-in-supply = <&tps65090_dcdc3_reg>;
 | |
| 				smps3-in-supply = <&tps65090_dcdc3_reg>;
 | |
| 				smps4-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				smps7-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				smps8-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				smps9-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo1-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo2-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo3-in-supply = <&palmas_smps3_reg>;
 | |
| 				ldo4-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo5-in-supply = <&vdd_ac_bat_reg>;
 | |
| 				ldo6-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo7-in-supply = <&tps65090_dcdc2_reg>;
 | |
| 				ldo8-in-supply = <&tps65090_dcdc3_reg>;
 | |
| 				ldo9-in-supply = <&palmas_smps9_reg>;
 | |
| 				ldoln-in-supply = <&tps65090_dcdc1_reg>;
 | |
| 				ldousb-in-supply = <&tps65090_dcdc1_reg>;
 | |
| 
 | |
| 				regulators {
 | |
| 					smps12 {
 | |
| 						regulator-name = "vddio-ddr";
 | |
| 						regulator-min-microvolt = <1350000>;
 | |
| 						regulator-max-microvolt = <1350000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					palmas_smps3_reg: smps3 {
 | |
| 						regulator-name = "vddio-1v8";
 | |
| 						regulator-min-microvolt = <1800000>;
 | |
| 						regulator-max-microvolt = <1800000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					smps45 {
 | |
| 						regulator-name = "vdd-core";
 | |
| 						regulator-min-microvolt = <900000>;
 | |
| 						regulator-max-microvolt = <1400000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					smps457 {
 | |
| 						regulator-name = "vdd-core";
 | |
| 						regulator-min-microvolt = <900000>;
 | |
| 						regulator-max-microvolt = <1400000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					smps8 {
 | |
| 						regulator-name = "avdd-pll";
 | |
| 						regulator-min-microvolt = <1050000>;
 | |
| 						regulator-max-microvolt = <1050000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					palmas_smps9_reg: smps9 {
 | |
| 						regulator-name = "sdhci-vdd-sd-slot";
 | |
| 						regulator-min-microvolt = <2800000>;
 | |
| 						regulator-max-microvolt = <2800000>;
 | |
| 						regulator-always-on;
 | |
| 					};
 | |
| 
 | |
| 					ldo1 {
 | |
| 						regulator-name = "avdd-cam1";
 | |
| 						regulator-min-microvolt = <2800000>;
 | |
| 						regulator-max-microvolt = <2800000>;
 | |
| 					};
 | |
| 
 | |
| 					ldo2 {
 | |
| 						regulator-name = "avdd-cam2";
 | |
| 						regulator-min-microvolt = <2800000>;
 | |
| 						regulator-max-microvolt = <2800000>;
 | |
| 					};
 | |
| 
 | |
| 					avdd_1v2_reg: ldo3 {
 | |
| 						regulator-name = "avdd-dsi-csi";
 | |
| 						regulator-min-microvolt = <1200000>;
 | |
| 						regulator-max-microvolt = <1200000>;
 | |
| 					};
 | |
| 
 | |
| 					ldo4 {
 | |
| 						regulator-name = "vpp-fuse";
 | |
| 						regulator-min-microvolt = <1800000>;
 | |
| 						regulator-max-microvolt = <1800000>;
 | |
| 					};
 | |
| 
 | |
| 					palmas_ldo6_reg: ldo6 {
 | |
| 						regulator-name = "vdd-sensor-2v85";
 | |
| 						regulator-min-microvolt = <2850000>;
 | |
| 						regulator-max-microvolt = <2850000>;
 | |
| 					};
 | |
| 
 | |
| 					ldo7 {
 | |
| 						regulator-name = "vdd-af-cam1";
 | |
| 						regulator-min-microvolt = <2800000>;
 | |
| 						regulator-max-microvolt = <2800000>;
 | |
| 					};
 | |
| 
 | |
| 					ldo8 {
 | |
| 						regulator-name = "vdd-rtc";
 | |
| 						regulator-min-microvolt = <900000>;
 | |
| 						regulator-max-microvolt = <900000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 						ti,enable-ldo8-tracking;
 | |
| 					};
 | |
| 
 | |
| 					ldo9 {
 | |
| 						regulator-name = "vddio-sdmmc-2";
 | |
| 						regulator-min-microvolt = <1800000>;
 | |
| 						regulator-max-microvolt = <3300000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					ldoln {
 | |
| 						regulator-name = "hvdd-usb";
 | |
| 						regulator-min-microvolt = <3300000>;
 | |
| 						regulator-max-microvolt = <3300000>;
 | |
| 					};
 | |
| 
 | |
| 					ldousb {
 | |
| 						regulator-name = "avdd-usb";
 | |
| 						regulator-min-microvolt = <3300000>;
 | |
| 						regulator-max-microvolt = <3300000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					regen1 {
 | |
| 						regulator-name = "rail-3v3";
 | |
| 						regulator-max-microvolt = <3300000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 
 | |
| 					regen2 {
 | |
| 						regulator-name = "rail-5v0";
 | |
| 						regulator-max-microvolt = <5000000>;
 | |
| 						regulator-always-on;
 | |
| 						regulator-boot-on;
 | |
| 					};
 | |
| 				};
 | |
| 			};
 | |
| 
 | |
| 			rtc {
 | |
| 				compatible = "ti,palmas-rtc";
 | |
| 				interrupt-parent = <&palmas>;
 | |
| 				interrupts = <8 0>;
 | |
| 			};
 | |
| 
 | |
| 			pinmux {
 | |
| 				compatible = "ti,tps65913-pinctrl";
 | |
| 				pinctrl-names = "default";
 | |
| 				pinctrl-0 = <&palmas_default>;
 | |
| 
 | |
| 				palmas_default: pinmux {
 | |
| 					pin_gpio6 {
 | |
| 						pins = "gpio6";
 | |
| 						function = "gpio";
 | |
| 					};
 | |
| 				};
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	spi@7000da00 {
 | |
| 		status = "okay";
 | |
| 		spi-max-frequency = <25000000>;
 | |
| 		spi-flash@0 {
 | |
| 			compatible = "winbond,w25q32dw";
 | |
| 			reg = <0>;
 | |
| 			spi-max-frequency = <20000000>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	pmc@7000e400 {
 | |
| 		nvidia,invert-interrupt;
 | |
| 		nvidia,suspend-mode = <1>;
 | |
| 		nvidia,cpu-pwr-good-time = <500>;
 | |
| 		nvidia,cpu-pwr-off-time = <300>;
 | |
| 		nvidia,core-pwr-good-time = <641 3845>;
 | |
| 		nvidia,core-pwr-off-time = <61036>;
 | |
| 		nvidia,core-power-req-active-high;
 | |
| 		nvidia,sys-clock-req-active-high;
 | |
| 	};
 | |
| 
 | |
| 	ahub@70080000 {
 | |
| 		i2s@70080400 {
 | |
| 			status = "okay";
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	sdhci@78000400 {
 | |
| 		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 | |
| 		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
 | |
| 		bus-width = <4>;
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	sdhci@78000600 {
 | |
| 		bus-width = <8>;
 | |
| 		status = "okay";
 | |
| 		non-removable;
 | |
| 	};
 | |
| 
 | |
| 	usb@7d000000 {
 | |
| 		compatible = "nvidia,tegra114-udc";
 | |
| 		status = "okay";
 | |
| 		dr_mode = "peripheral";
 | |
| 	};
 | |
| 
 | |
| 	usb-phy@7d000000 {
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	usb@7d008000 {
 | |
| 		status = "okay";
 | |
| 	};
 | |
| 
 | |
| 	usb-phy@7d008000 {
 | |
| 		status = "okay";
 | |
| 		vbus-supply = <&usb3_vbus_reg>;
 | |
| 	};
 | |
| 
 | |
| 	backlight: backlight {
 | |
| 		compatible = "pwm-backlight";
 | |
| 
 | |
| 		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 | |
| 		power-supply = <&vdd_bl_reg>;
 | |
| 		pwms = <&pwm 1 1000000>;
 | |
| 
 | |
| 		brightness-levels = <0 4 8 16 32 64 128 255>;
 | |
| 		default-brightness-level = <6>;
 | |
| 	};
 | |
| 
 | |
| 	clocks {
 | |
| 		compatible = "simple-bus";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 
 | |
| 		clk32k_in: clock@0 {
 | |
| 			compatible = "fixed-clock";
 | |
| 			reg = <0>;
 | |
| 			#clock-cells = <0>;
 | |
| 			clock-frequency = <32768>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	gpio-keys {
 | |
| 		compatible = "gpio-keys";
 | |
| 
 | |
| 		home {
 | |
| 			label = "Home";
 | |
| 			gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
 | |
| 			linux,code = <KEY_HOME>;
 | |
| 		};
 | |
| 
 | |
| 		power {
 | |
| 			label = "Power";
 | |
| 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 | |
| 			linux,code = <KEY_POWER>;
 | |
| 			wakeup-source;
 | |
| 		};
 | |
| 
 | |
| 		volume_down {
 | |
| 			label = "Volume Down";
 | |
| 			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
 | |
| 			linux,code = <KEY_VOLUMEDOWN>;
 | |
| 		};
 | |
| 
 | |
| 		volume_up {
 | |
| 			label = "Volume Up";
 | |
| 			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
 | |
| 			linux,code = <KEY_VOLUMEUP>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	regulators {
 | |
| 		compatible = "simple-bus";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 
 | |
| 		vdd_ac_bat_reg: regulator@0 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <0>;
 | |
| 			regulator-name = "vdd_ac_bat";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			regulator-always-on;
 | |
| 		};
 | |
| 
 | |
| 		dvdd_ts_reg: regulator@1 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <1>;
 | |
| 			regulator-name = "dvdd_ts";
 | |
| 			regulator-min-microvolt = <1800000>;
 | |
| 			regulator-max-microvolt = <1800000>;
 | |
| 			enable-active-high;
 | |
| 			gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
 | |
| 		};
 | |
| 
 | |
| 		usb1_vbus_reg: regulator@3 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <3>;
 | |
| 			regulator-name = "usb1_vbus";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			enable-active-high;
 | |
| 			gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 | |
| 			gpio-open-drain;
 | |
| 			vin-supply = <&tps65090_dcdc1_reg>;
 | |
| 		};
 | |
| 
 | |
| 		usb3_vbus_reg: regulator@4 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <4>;
 | |
| 			regulator-name = "usb2_vbus";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			enable-active-high;
 | |
| 			gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
 | |
| 			gpio-open-drain;
 | |
| 			vin-supply = <&tps65090_dcdc1_reg>;
 | |
| 		};
 | |
| 
 | |
| 		vdd_hdmi_reg: regulator@5 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <5>;
 | |
| 			regulator-name = "vdd_hdmi_5v0";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			vin-supply = <&tps65090_dcdc1_reg>;
 | |
| 		};
 | |
| 
 | |
| 		vdd_cam_1v8_reg: regulator@6 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <6>;
 | |
| 			regulator-name = "vdd_cam_1v8_reg";
 | |
| 			regulator-min-microvolt = <1800000>;
 | |
| 			regulator-max-microvolt = <1800000>;
 | |
| 			enable-active-high;
 | |
| 			gpio = <&palmas_gpio 6 0>;
 | |
| 		};
 | |
| 
 | |
| 		vdd_5v0_hdmi: regulator@7 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <7>;
 | |
| 			regulator-name = "VDD_5V0_HDMI_CON";
 | |
| 			regulator-min-microvolt = <5000000>;
 | |
| 			regulator-max-microvolt = <5000000>;
 | |
| 			gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
 | |
| 			enable-active-high;
 | |
| 			vin-supply = <&tps65090_dcdc1_reg>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	sound {
 | |
| 		compatible = "nvidia,tegra-audio-rt5640-dalmore",
 | |
| 			     "nvidia,tegra-audio-rt5640";
 | |
| 		nvidia,model = "NVIDIA Tegra Dalmore";
 | |
| 
 | |
| 		nvidia,audio-routing =
 | |
| 			"Headphones", "HPOR",
 | |
| 			"Headphones", "HPOL",
 | |
| 			"Speakers", "SPORP",
 | |
| 			"Speakers", "SPORN",
 | |
| 			"Speakers", "SPOLP",
 | |
| 			"Speakers", "SPOLN",
 | |
| 			"Mic Jack", "MICBIAS1",
 | |
| 			"IN2P", "Mic Jack";
 | |
| 
 | |
| 		nvidia,i2s-controller = <&tegra_i2s1>;
 | |
| 		nvidia,audio-codec = <&rt5640>;
 | |
| 
 | |
| 		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
 | |
| 
 | |
| 		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
 | |
| 			 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
 | |
| 			 <&tegra_car TEGRA114_CLK_EXTERN1>;
 | |
| 		clock-names = "pll_a", "pll_a_out0", "mclk";
 | |
| 	};
 | |
| };
 | 
