239 lines
5.7 KiB
C
239 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SPL data and initialization for CompuLab CL-SOM-AM57x board
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*
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* (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
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*
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
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*/
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#include <asm/emif.h>
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#include <asm/omap_common.h>
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#include <asm/arch/sys_proto.h>
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static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
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.dmm_lisa_map_3 = 0x80740300,
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.is_ma_present = 0x1
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};
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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/* Disable SDRAM controller EMIF2 for single core SOC */
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*dmm_lisa_regs = &cl_som_am57x_lisa_regs;
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if (omap_revision() == DRA722_ES1_0) {
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((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
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0x80640100;
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}
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}
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static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61852332,
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.sdram_config = 0x61852332,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x000040f1,
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.ref_ctrl_final = 0x00001040,
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.sdram_tim1 = 0xeeef36f3,
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.sdram_tim2 = 0x348f7fda,
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.sdram_tim3 = 0x027f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x1007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0034400b,
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.emif_ddr_phy_ctlr_1 = 0x0e34400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
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.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
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.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
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.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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/* Ext phy ctrl regs 1-35 */
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static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
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0x10040100,
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0x00740074,
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0x00780078,
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0x007c007c,
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0x007b007b,
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0x00800080,
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0x00360036,
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0x00340034,
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0x00360036,
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0x00350035,
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0x00350035,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x00430043,
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0x003e003e,
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0x004a004a,
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0x00470047,
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0x00400040,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61852332,
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.sdram_config = 0x61852332,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x000040f1,
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.ref_ctrl_final = 0x00001040,
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.sdram_tim1 = 0xeeef36f3,
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.sdram_tim2 = 0x348f7fda,
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.sdram_tim3 = 0x027f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x1007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0034400b,
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.emif_ddr_phy_ctlr_1 = 0x0e34400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
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.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
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.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
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.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
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0x10040100,
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0x00820082,
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0x008b008b,
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0x00800080,
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0x007e007e,
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0x00800080,
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0x00370037,
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0x00390039,
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0x00360036,
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0x00370037,
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0x00350035,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x00540054,
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0x00540054,
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0x004e004e,
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0x004c004c,
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0x00400040,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0
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};
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static struct vcores_data cl_som_am57x_volts = {
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.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
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.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
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.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.mpu.addr = TPS659038_REG_ADDR_SMPS12,
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.mpu.pmic = &tps659038,
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.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
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.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
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.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
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.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
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.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
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.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
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.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.eve.addr = TPS659038_REG_ADDR_SMPS45,
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.eve.pmic = &tps659038,
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.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
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.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
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.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
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.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
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.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
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.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
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.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.gpu.addr = TPS659038_REG_ADDR_SMPS6,
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.gpu.pmic = &tps659038,
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.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
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.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
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.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.core.addr = TPS659038_REG_ADDR_SMPS7,
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.core.pmic = &tps659038,
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.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
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.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
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.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
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.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
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.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
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.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
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.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
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.iva.addr = TPS659038_REG_ADDR_SMPS8,
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.iva.pmic = &tps659038,
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};
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void hw_data_init(void)
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{
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*prcm = &dra7xx_prcm;
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*dplls_data = &dra7xx_dplls;
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*omap_vcores = &cl_som_am57x_volts;
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*ctrl = &dra7xx_ctrl;
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}
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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switch (emif_nr) {
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case 1:
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*regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
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break;
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case 2:
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*regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
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break;
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}
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}
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void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
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{
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switch (emif_nr) {
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case 1:
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*regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
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*size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
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break;
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case 2:
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*regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
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*size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
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break;
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}
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}
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