516 lines
12 KiB
C
516 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2012,2015 Stephen Warren
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*/
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#ifndef _BCM2835_MBOX_H
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#define _BCM2835_MBOX_H
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#include <linux/compiler.h>
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/*
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* The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
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* and the ARM CPU. The ARM CPU is often thought of as the main CPU.
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* However, the VideoCore actually controls the initial SoC boot, and hides
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* much of the hardware behind a protocol. This protocol is transported
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* using the SoC's mailbox hardware module.
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*
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* The mailbox hardware supports passing 32-bit values back and forth.
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* Presumably by software convention of the firmware, the bottom 4 bits of the
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* value are used to indicate a logical channel, and the upper 28 bits are the
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* actual payload. Various channels exist using these simple raw messages. See
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* https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
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* example, the messages on the power management channel are a bitmask of
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* devices whose power should be enabled.
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*
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* The property mailbox channel passes messages that contain the (16-byte
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* aligned) ARM physical address of a memory buffer. This buffer is passed to
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* the VC for processing, is modified in-place by the VC, and the address then
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* passed back to the ARM CPU as the response mailbox message to indicate
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* request completion. The buffers have a generic and extensible format; each
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* buffer contains a standard header, a list of "tags", and a terminating zero
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* entry. Each tag contains an ID indicating its type, and length fields for
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* generic parsing. With some limitations, an arbitrary set of tags may be
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* combined together into a single message buffer. This file defines structs
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* representing the header and many individual tag layouts and IDs.
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*/
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/* Raw mailbox HW */
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#ifndef CONFIG_BCM2835
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#define BCM2835_MBOX_PHYSADDR 0x3f00b880
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#else
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#define BCM2835_MBOX_PHYSADDR 0x2000b880
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#endif
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struct bcm2835_mbox_regs {
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u32 read;
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u32 rsvd0[5];
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u32 status;
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u32 config;
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u32 write;
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};
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#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
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#define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
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/* Lower 4-bits are channel ID */
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#define BCM2835_CHAN_MASK 0xf
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#define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \
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(chan & BCM2835_CHAN_MASK))
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#define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK)
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#define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK))
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/* Property mailbox buffer structures */
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#define BCM2835_MBOX_PROP_CHAN 8
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/* All message buffers must start with this header */
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struct bcm2835_mbox_hdr {
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u32 buf_size;
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u32 code;
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};
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#define BCM2835_MBOX_REQ_CODE 0
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#define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
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#define BCM2835_MBOX_INIT_HDR(_m_) { \
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memset((_m_), 0, sizeof(*(_m_))); \
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(_m_)->hdr.buf_size = sizeof(*(_m_)); \
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(_m_)->hdr.code = 0; \
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(_m_)->end_tag = 0; \
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}
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/*
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* A message buffer contains a list of tags. Each tag must also start with
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* a standardized header.
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*/
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struct bcm2835_mbox_tag_hdr {
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u32 tag;
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u32 val_buf_size;
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u32 val_len;
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};
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#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
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(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
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(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
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(_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
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}
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#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
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(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
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(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
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(_t_)->tag_hdr.val_len = 0; \
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}
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/* When responding, the VC sets this bit in val_len to indicate a response */
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#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
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/*
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* Below we define the ID and struct for many possible tags. This header only
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* defines individual tag structs, not entire message structs, since in
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* general an arbitrary set of tags may be combined into a single message.
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* Clients of the mbox API are expected to define their own overall message
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* structures by combining the header, a set of tags, and a terminating
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* entry. For example,
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*
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* struct msg {
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* struct bcm2835_mbox_hdr hdr;
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* struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
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* ... perhaps other tags here ...
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* u32 end_tag;
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* };
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*/
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#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
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struct bcm2835_mbox_tag_get_board_rev {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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u32 rev;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003
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struct bcm2835_mbox_tag_get_mac_address {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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u8 mac[6];
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u8 pad[2];
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004
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struct bcm2835_mbox_tag_get_board_serial {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct __packed {
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u64 serial;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
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struct bcm2835_mbox_tag_get_arm_mem {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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u32 mem_base;
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u32 mem_size;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_POWER_DEVID_SDHCI 0
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#define BCM2835_MBOX_POWER_DEVID_UART0 1
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#define BCM2835_MBOX_POWER_DEVID_UART1 2
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#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3
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#define BCM2835_MBOX_POWER_DEVID_I2C0 4
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#define BCM2835_MBOX_POWER_DEVID_I2C1 5
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#define BCM2835_MBOX_POWER_DEVID_I2C2 6
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#define BCM2835_MBOX_POWER_DEVID_SPI 7
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#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
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#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
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/* Device doesn't exist */
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#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
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#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001
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struct bcm2835_mbox_tag_get_power_state {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 device_id;
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} req;
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struct {
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u32 device_id;
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u32 state;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001
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#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0)
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#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1)
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struct bcm2835_mbox_tag_set_power_state {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 device_id;
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u32 state;
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} req;
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struct {
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u32 device_id;
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u32 state;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
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#define BCM2835_MBOX_CLOCK_ID_EMMC 1
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#define BCM2835_MBOX_CLOCK_ID_UART 2
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#define BCM2835_MBOX_CLOCK_ID_ARM 3
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#define BCM2835_MBOX_CLOCK_ID_CORE 4
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#define BCM2835_MBOX_CLOCK_ID_V3D 5
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#define BCM2835_MBOX_CLOCK_ID_H264 6
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#define BCM2835_MBOX_CLOCK_ID_ISP 7
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#define BCM2835_MBOX_CLOCK_ID_SDRAM 8
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#define BCM2835_MBOX_CLOCK_ID_PIXEL 9
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#define BCM2835_MBOX_CLOCK_ID_PWM 10
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struct bcm2835_mbox_tag_get_clock_rate {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 clock_id;
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} req;
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struct {
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u32 clock_id;
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u32 rate_hz;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001
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struct bcm2835_mbox_tag_allocate_buffer {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 alignment;
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} req;
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struct {
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u32 fb_address;
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u32 fb_size;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001
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struct bcm2835_mbox_tag_release_buffer {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002
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struct bcm2835_mbox_tag_blank_screen {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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/* bit 0 means on, other bots reserved */
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u32 state;
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} req;
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struct {
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u32 state;
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} resp;
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} body;
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};
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/* Physical means output signal */
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#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003
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#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003
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#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003
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struct bcm2835_mbox_tag_physical_w_h {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 width;
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u32 height;
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} req;
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struct {
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u32 width;
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u32 height;
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} resp;
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} body;
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};
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/* Virtual means display buffer */
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#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004
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#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004
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#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004
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struct bcm2835_mbox_tag_virtual_w_h {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 width;
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u32 height;
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} req;
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struct {
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u32 width;
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u32 height;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005
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#define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005
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#define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005
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struct bcm2835_mbox_tag_depth {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 bpp;
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} req;
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struct {
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u32 bpp;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
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#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005
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#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
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#define BCM2835_MBOX_PIXEL_ORDER_BGR 0
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#define BCM2835_MBOX_PIXEL_ORDER_RGB 1
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struct bcm2835_mbox_tag_pixel_order {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 order;
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} req;
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struct {
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u32 order;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007
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#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007
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#define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007
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#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0
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#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1
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#define BCM2835_MBOX_ALPHA_MODE_IGNORED 2
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struct bcm2835_mbox_tag_alpha_mode {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 alpha;
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} req;
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struct {
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u32 alpha;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_PITCH 0x00040008
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struct bcm2835_mbox_tag_pitch {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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u32 pitch;
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} resp;
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} body;
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};
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/* Offset of display window within buffer */
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#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009
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#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009
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#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009
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struct bcm2835_mbox_tag_virtual_offset {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 x;
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u32 y;
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} req;
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struct {
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u32 x;
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u32 y;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a
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#define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a
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#define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a
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struct bcm2835_mbox_tag_overscan {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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/* req not used for get */
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struct {
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u32 top;
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u32 bottom;
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u32 left;
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u32 right;
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} req;
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struct {
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u32 top;
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u32 bottom;
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u32 left;
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u32 right;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b
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struct bcm2835_mbox_tag_get_palette {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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} req;
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struct {
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u32 data[1024];
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b
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struct bcm2835_mbox_tag_test_palette {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 offset;
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u32 num_entries;
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u32 data[256];
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} req;
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struct {
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u32 is_invalid;
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} resp;
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} body;
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};
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#define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b
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struct bcm2835_mbox_tag_set_palette {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 offset;
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u32 num_entries;
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u32 data[256];
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} req;
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struct {
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u32 is_invalid;
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} resp;
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} body;
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};
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/*
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* Pass a raw u32 message to the VC, and receive a raw u32 back.
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*
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* Returns 0 for success, any other value for error.
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*/
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int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
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/*
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* Pass a complete property-style buffer to the VC, and wait until it has
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* been processed.
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*
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* This function expects a pointer to the mbox_hdr structure in an attempt
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* to ensure some degree of type safety. However, some number of tags and
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* a termination value are expected to immediately follow the header in
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* memory, as required by the property protocol.
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*
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* Each struct bcm2835_mbox_hdr passed must be allocated with
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* ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate.
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*
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* Returns 0 for success, any other value for error.
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*/
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int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
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#endif
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