109 lines
1.7 KiB
C
109 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 Google, Inc
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*
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* Copyright 2014 Rockchip Inc.
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*/
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#ifndef _ASM_ARCH_RK3288_SDRAM_H__
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#define _ASM_ARCH_RK3288_SDRAM_H__
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enum {
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DDR3 = 3,
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LPDDR3 = 6,
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UNUSED = 0xFF,
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};
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struct rk3288_sdram_channel {
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/*
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* bit width in address, eg:
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* 8 banks using 3 bit to address,
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* 2 cs using 1 bit to address.
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*/
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u8 rank;
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u8 col;
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u8 bk;
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u8 bw;
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u8 dbw;
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u8 row_3_4;
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u8 cs0_row;
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u8 cs1_row;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/*
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* For of-platdata, which would otherwise convert this into two
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* byte-swapped integers. With a size of 9 bytes, this struct will
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* appear in of-platdata as a byte array.
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*
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* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
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*/
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u8 dummy;
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#endif
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};
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struct rk3288_sdram_pctl_timing {
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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};
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check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
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struct rk3288_sdram_phy_timing {
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u32 dtpr0;
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u32 dtpr1;
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u32 dtpr2;
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u32 mr[4];
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};
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struct rk3288_base_params {
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u32 noc_timing;
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u32 noc_activate;
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u32 ddrconfig;
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u32 ddr_freq;
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u32 dramtype;
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/*
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* DDR Stride is address mapping for DRAM space
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* Stride Ch 0 range Ch1 range Total
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* 0x00 0-256MB 256MB-512MB 512MB
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* 0x05 0-1GB 0-1GB 1GB
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* 0x09 0-2GB 0-2GB 2GB
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* 0x0d 0-4GB 0-4GB 4GB
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* 0x17 N/A 0-4GB 4GB
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* 0x1a 0-4GB 4GB-8GB 8GB
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*/
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u32 stride;
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u32 odt;
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};
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#endif
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