181 lines
2.8 KiB
Plaintext
181 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright (C) 2015, Freescale Semiconductor
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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/include/ "fsl-ls1043a.dtsi"
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/ {
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model = "LS1043A QDS Board";
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aliases {
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spi0 = &qspi;
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spi1 = &dspi0;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <1000000>; /* input clock */
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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dflash1: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3500000>;
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spi-cpol;
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spi-cpha;
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reg = <1>;
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};
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dflash2: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3500000>;
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spi-cpol;
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spi-cpha;
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reg = <2>;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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pca9547@77 {
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compatible = "philips,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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/* IRQ10_B */
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interrupts = <0 150 0x4>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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eeprom@56 {
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compatible = "at24,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "at24,24c512";
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reg = <0x57>;
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};
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adt7461a@4c {
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compatible = "adt7461a";
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reg = <0x4c>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x1 0x0 0x0 0x7e800000 0x00010000
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0x2 0x0 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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fpga: board-control@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x2 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 2 0 0x100>;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&lpuart0 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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