103 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			103 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Copyright (c) 2016, NVIDIA CORPORATION.
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|  */
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| 
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| #include <common.h>
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| #include <clk-uclass.h>
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| #include <dm.h>
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| #include <asm/arch/clock.h>
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| #include <asm/arch-tegra/clk_rst.h>
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| 
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| static int tegra_car_clk_request(struct clk *clk)
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| {
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| 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
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| 	      clk->id);
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| 
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| 	/*
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| 	 * Note that the first PERIPH_ID_COUNT clock IDs (where the value
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| 	 * varies per SoC) are the peripheral clocks, which use a numbering
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| 	 * scheme that matches HW registers 1:1. There are other clock IDs
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| 	 * beyond this that are assigned arbitrarily by the Tegra CAR DT
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| 	 * binding. Due to the implementation of this driver, it currently
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| 	 * only supports the peripheral IDs.
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| 	 */
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| 	if (clk->id >= PERIPH_ID_COUNT)
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| 		return -EINVAL;
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| 
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| 	return 0;
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| }
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| 
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| static int tegra_car_clk_free(struct clk *clk)
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| {
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| 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
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| 	      clk->id);
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| 
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| 	return 0;
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| }
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| 
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| static ulong tegra_car_clk_get_rate(struct clk *clk)
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| {
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| 	enum clock_id parent;
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| 
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| 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
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| 	      clk->id);
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| 
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| 	parent = clock_get_periph_parent(clk->id);
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| 	return clock_get_periph_rate(clk->id, parent);
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| }
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| 
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| static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
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| {
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| 	enum clock_id parent;
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| 
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| 	debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
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| 	      clk->dev, clk->id);
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| 
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| 	parent = clock_get_periph_parent(clk->id);
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| 	return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
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| }
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| 
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| static int tegra_car_clk_enable(struct clk *clk)
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| {
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| 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
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| 	      clk->id);
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| 
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| 	clock_enable(clk->id);
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| 
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| 	return 0;
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| }
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| 
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| static int tegra_car_clk_disable(struct clk *clk)
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| {
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| 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
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| 	      clk->id);
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| 
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| 	clock_disable(clk->id);
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| 
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| 	return 0;
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| }
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| 
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| static struct clk_ops tegra_car_clk_ops = {
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| 	.request = tegra_car_clk_request,
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| 	.free = tegra_car_clk_free,
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| 	.get_rate = tegra_car_clk_get_rate,
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| 	.set_rate = tegra_car_clk_set_rate,
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| 	.enable = tegra_car_clk_enable,
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| 	.disable = tegra_car_clk_disable,
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| };
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| 
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| static int tegra_car_clk_probe(struct udevice *dev)
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| {
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| 	debug("%s(dev=%p)\n", __func__, dev);
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| 
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| 	return 0;
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| }
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| 
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| U_BOOT_DRIVER(tegra_car_clk) = {
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| 	.name = "tegra_car_clk",
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| 	.id = UCLASS_CLK,
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| 	.probe = tegra_car_clk_probe,
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| 	.ops = &tegra_car_clk_ops,
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| };
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