570 lines
16 KiB
C
570 lines
16 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../wifi.h"
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#include "../pci.h"
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#include "../ps.h"
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#include "../core.h"
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#include "reg.h"
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#include "def.h"
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#include "hw.h"
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#include "phy.h"
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#include "../rtl8192c/phy_common.h"
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#include "rf.h"
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#include "dm.h"
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#include "../rtl8192c/dm_common.h"
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#include "../rtl8192c/fw_common.h"
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#include "table.h"
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static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
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u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
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enum radio_path rfpath, u32 regaddr, u32 bitmask)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 original_value, readback_value, bitshift;
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
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regaddr, rfpath, bitmask);
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spin_lock(&rtlpriv->locks.rf_lock);
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if (rtlphy->rf_mode != RF_OP_BY_FW) {
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original_value = _rtl92c_phy_rf_serial_read(hw,
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rfpath, regaddr);
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} else {
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original_value = _rtl92c_phy_fw_rf_serial_read(hw,
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rfpath, regaddr);
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}
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bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
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readback_value = (original_value & bitmask) >> bitshift;
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spin_unlock(&rtlpriv->locks.rf_lock);
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
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regaddr, rfpath, bitmask, original_value);
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return readback_value;
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}
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bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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bool is92c = IS_92C_SERIAL(rtlhal->version);
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bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
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if (is92c)
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rtl_write_byte(rtlpriv, 0x14, 0x71);
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else
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rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
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return rtstatus;
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}
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bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
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{
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bool rtstatus = true;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u16 regval;
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u32 regvaldw;
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u8 reg_hwparafile = 1;
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_rtl92c_phy_init_bb_rf_register_definition(hw);
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regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
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rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
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regval | BIT(13) | BIT(0) | BIT(1));
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rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
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rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
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rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
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rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
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FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
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FEN_BB_GLB_RSTn | FEN_BBRSTB);
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rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
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regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
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rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
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if (reg_hwparafile == 1)
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rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
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return rtstatus;
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}
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void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
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enum radio_path rfpath,
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u32 regaddr, u32 bitmask, u32 data)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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u32 original_value, bitshift;
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
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regaddr, bitmask, data, rfpath);
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spin_lock(&rtlpriv->locks.rf_lock);
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if (rtlphy->rf_mode != RF_OP_BY_FW) {
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if (bitmask != RFREG_OFFSET_MASK) {
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original_value = _rtl92c_phy_rf_serial_read(hw,
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rfpath,
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regaddr);
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bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
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data =
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((original_value & (~bitmask)) |
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(data << bitshift));
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}
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_rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
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} else {
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if (bitmask != RFREG_OFFSET_MASK) {
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original_value = _rtl92c_phy_fw_rf_serial_read(hw,
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rfpath,
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regaddr);
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bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
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data =
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((original_value & (~bitmask)) |
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(data << bitshift));
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}
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_rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
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}
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spin_unlock(&rtlpriv->locks.rf_lock);
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RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
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"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
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regaddr, bitmask, data, rfpath);
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}
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static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 i;
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u32 arraylength;
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u32 *ptrarray;
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
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arraylength = MAC_2T_ARRAYLENGTH;
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ptrarray = RTL8192CEMAC_2T_ARRAY;
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
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for (i = 0; i < arraylength; i = i + 2)
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rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
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return true;
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}
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bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
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u8 configtype)
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{
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int i;
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u32 *phy_regarray_table;
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u32 *agctab_array_table;
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u16 phy_reg_arraylen, agctab_arraylen;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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if (IS_92C_SERIAL(rtlhal->version)) {
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agctab_arraylen = AGCTAB_2TARRAYLENGTH;
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agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
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phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
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phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
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} else {
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agctab_arraylen = AGCTAB_1TARRAYLENGTH;
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agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
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phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
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phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
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}
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if (configtype == BASEBAND_CONFIG_PHY_REG) {
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for (i = 0; i < phy_reg_arraylen; i = i + 2) {
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rtl_addr_delay(phy_regarray_table[i]);
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rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
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phy_regarray_table[i + 1]);
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udelay(1);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
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phy_regarray_table[i],
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phy_regarray_table[i + 1]);
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}
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} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
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for (i = 0; i < agctab_arraylen; i = i + 2) {
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rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
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agctab_array_table[i + 1]);
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udelay(1);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
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agctab_array_table[i],
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agctab_array_table[i + 1]);
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}
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}
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return true;
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}
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bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
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u8 configtype)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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int i;
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u32 *phy_regarray_table_pg;
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u16 phy_regarray_pg_len;
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phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
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phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
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if (configtype == BASEBAND_CONFIG_PHY_REG) {
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for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
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rtl_addr_delay(phy_regarray_table_pg[i]);
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_rtl92c_store_pwrIndex_diffrate_offset(hw,
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phy_regarray_table_pg[i],
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phy_regarray_table_pg[i + 1],
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phy_regarray_table_pg[i + 2]);
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}
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} else {
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RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
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"configtype != BaseBand_Config_PHY_REG\n");
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}
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return true;
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}
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bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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enum radio_path rfpath)
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{
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int i;
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u32 *radioa_array_table;
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u32 *radiob_array_table;
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u16 radioa_arraylen, radiob_arraylen;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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if (IS_92C_SERIAL(rtlhal->version)) {
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radioa_arraylen = RADIOA_2TARRAYLENGTH;
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radioa_array_table = RTL8192CERADIOA_2TARRAY;
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radiob_arraylen = RADIOB_2TARRAYLENGTH;
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radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Radio_A:RTL8192CERADIOA_2TARRAY\n");
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
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} else {
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radioa_arraylen = RADIOA_1TARRAYLENGTH;
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radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
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radiob_arraylen = RADIOB_1TARRAYLENGTH;
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radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
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}
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
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switch (rfpath) {
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case RF90_PATH_A:
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for (i = 0; i < radioa_arraylen; i = i + 2) {
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rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
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RFREG_OFFSET_MASK,
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radioa_array_table[i + 1]);
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}
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break;
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case RF90_PATH_B:
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for (i = 0; i < radiob_arraylen; i = i + 2) {
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rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
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RFREG_OFFSET_MASK,
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radiob_array_table[i + 1]);
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}
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break;
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case RF90_PATH_C:
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case RF90_PATH_D:
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pr_info("Incorrect rfpath %#x\n", rfpath);
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break;
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default:
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pr_info("switch case %#x not processed\n", rfpath);
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break;
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}
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return true;
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}
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void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
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u8 reg_bw_opmode;
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u8 reg_prsr_rsc;
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RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
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rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
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"20MHz" : "40MHz");
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if (is_hal_stop(rtlhal)) {
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rtlphy->set_bwmode_inprogress = false;
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return;
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}
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reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
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reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
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switch (rtlphy->current_chan_bw) {
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case HT_CHANNEL_WIDTH_20:
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reg_bw_opmode |= BW_OPMODE_20MHZ;
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rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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reg_bw_opmode &= ~BW_OPMODE_20MHZ;
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rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
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reg_prsr_rsc =
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(reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
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rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
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break;
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default:
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pr_info("unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
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break;
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}
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switch (rtlphy->current_chan_bw) {
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case HT_CHANNEL_WIDTH_20:
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rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
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rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
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rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
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break;
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case HT_CHANNEL_WIDTH_20_40:
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rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
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rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
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rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
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(mac->cur_40_prime_sc >> 1));
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rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
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rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
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rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
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(mac->cur_40_prime_sc ==
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HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
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break;
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default:
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pr_err("unknown bandwidth: %#X\n",
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rtlphy->current_chan_bw);
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break;
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}
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rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
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rtlphy->set_bwmode_inprogress = false;
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RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
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}
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void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
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{
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u8 tmpreg;
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u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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tmpreg = rtl_read_byte(rtlpriv, 0xd03);
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if ((tmpreg & 0x70) != 0)
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rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
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else
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rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
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if ((tmpreg & 0x70) != 0) {
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rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
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if (is2t)
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rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
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MASK12BITS);
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rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
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(rf_a_mode & 0x8FFFF) | 0x10000);
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if (is2t)
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rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
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(rf_b_mode & 0x8FFFF) | 0x10000);
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}
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lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
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rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
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mdelay(100);
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if ((tmpreg & 0x70) != 0) {
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rtl_write_byte(rtlpriv, 0xd03, tmpreg);
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rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
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if (is2t)
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rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
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rf_b_mode);
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} else {
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rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
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}
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}
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static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
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{
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u32 u4b_tmp;
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u8 delay = 5;
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
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rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
|
|
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
|
|
u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
|
|
while (u4b_tmp != 0 && delay > 0) {
|
|
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
|
|
rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
|
|
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
|
|
u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
|
|
delay--;
|
|
}
|
|
if (delay == 0) {
|
|
rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
|
|
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
|
|
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
|
|
rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
|
|
RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
|
|
"Switch RF timeout !!!\n");
|
|
return;
|
|
}
|
|
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
|
|
rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
|
|
}
|
|
|
|
static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
|
|
enum rf_pwrstate rfpwr_state)
|
|
{
|
|
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
|
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
|
|
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
|
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
|
bool bresult = true;
|
|
u8 i, queue_id;
|
|
struct rtl8192_tx_ring *ring = NULL;
|
|
|
|
switch (rfpwr_state) {
|
|
case ERFON:{
|
|
if ((ppsc->rfpwr_state == ERFOFF) &&
|
|
RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
|
|
bool rtstatus;
|
|
u32 InitializeCount = 0;
|
|
do {
|
|
InitializeCount++;
|
|
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
|
|
"IPS Set eRf nic enable\n");
|
|
rtstatus = rtl_ps_enable_nic(hw);
|
|
} while (!rtstatus && (InitializeCount < 10));
|
|
RT_CLEAR_PS_LEVEL(ppsc,
|
|
RT_RF_OFF_LEVL_HALT_NIC);
|
|
} else {
|
|
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
|
|
"Set ERFON sleeped:%d ms\n",
|
|
jiffies_to_msecs(jiffies -
|
|
ppsc->
|
|
last_sleep_jiffies));
|
|
ppsc->last_awake_jiffies = jiffies;
|
|
rtl92ce_phy_set_rf_on(hw);
|
|
}
|
|
if (mac->link_state == MAC80211_LINKED) {
|
|
rtlpriv->cfg->ops->led_control(hw,
|
|
LED_CTL_LINK);
|
|
} else {
|
|
rtlpriv->cfg->ops->led_control(hw,
|
|
LED_CTL_NO_LINK);
|
|
}
|
|
break;
|
|
}
|
|
case ERFOFF:{
|
|
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
|
|
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
|
|
"IPS Set eRf nic disable\n");
|
|
rtl_ps_disable_nic(hw);
|
|
RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
|
|
} else {
|
|
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
|
|
rtlpriv->cfg->ops->led_control(hw,
|
|
LED_CTL_NO_LINK);
|
|
} else {
|
|
rtlpriv->cfg->ops->led_control(hw,
|
|
LED_CTL_POWER_OFF);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case ERFSLEEP:{
|
|
if (ppsc->rfpwr_state == ERFOFF)
|
|
break;
|
|
for (queue_id = 0, i = 0;
|
|
queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
|
|
ring = &pcipriv->dev.tx_ring[queue_id];
|
|
if (queue_id == BEACON_QUEUE ||
|
|
skb_queue_len(&ring->queue) == 0) {
|
|
queue_id++;
|
|
continue;
|
|
} else {
|
|
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
|
|
"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
|
|
i + 1, queue_id,
|
|
skb_queue_len(&ring->queue));
|
|
|
|
udelay(10);
|
|
i++;
|
|
}
|
|
if (i >= MAX_DOZE_WAITING_TIMES_9x) {
|
|
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
|
|
"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
|
|
MAX_DOZE_WAITING_TIMES_9x,
|
|
queue_id,
|
|
skb_queue_len(&ring->queue));
|
|
break;
|
|
}
|
|
}
|
|
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
|
|
"Set ERFSLEEP awaked:%d ms\n",
|
|
jiffies_to_msecs(jiffies -
|
|
ppsc->last_awake_jiffies));
|
|
ppsc->last_sleep_jiffies = jiffies;
|
|
_rtl92ce_phy_set_rf_sleep(hw);
|
|
break;
|
|
}
|
|
default:
|
|
pr_err("switch case %#x not processed\n",
|
|
rfpwr_state);
|
|
bresult = false;
|
|
break;
|
|
}
|
|
if (bresult)
|
|
ppsc->rfpwr_state = rfpwr_state;
|
|
return bresult;
|
|
}
|
|
|
|
bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
|
|
enum rf_pwrstate rfpwr_state)
|
|
{
|
|
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
|
|
|
bool bresult = false;
|
|
|
|
if (rfpwr_state == ppsc->rfpwr_state)
|
|
return bresult;
|
|
bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
|
|
return bresult;
|
|
}
|