334 lines
11 KiB
C
334 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The math for calculating PLL:
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* NFRAC * 2^8
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* NINT + -------------
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* XTAL [MHz] 2^(18 - 1)
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* PLL [MHz] = ------------ * ----------------------
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* REFDIV 2^OUTDIV
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*
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* Unfortunatelly, there is no way to reliably compute the variables.
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* The vendor U-Boot port contains macros for various combinations of
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* CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
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* in those numbers.
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*/
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struct ar934x_pll_config {
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u8 range;
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u8 refdiv;
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u8 outdiv;
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/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
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u8 nint[2];
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};
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struct ar934x_clock_config {
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u16 cpu_freq;
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u16 ddr_freq;
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u16 ahb_freq;
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struct ar934x_pll_config cpu_pll;
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struct ar934x_pll_config ddr_pll;
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};
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static const struct ar934x_clock_config ar934x_clock_config[] = {
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{ 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
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{ 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
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{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
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{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
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{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
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{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
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{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
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{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
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{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
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{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
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{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
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{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
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{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
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{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
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{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
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{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
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{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
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{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
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{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
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{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
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{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
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{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
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{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
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{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
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{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
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{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
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{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
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{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
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};
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static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
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{
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u32 reg;
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do {
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writel(0x10810f00, pll_reg_base + 0x4);
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writel(srif_val, pll_reg_base + 0x0);
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writel(0xd0810f00, pll_reg_base + 0x4);
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writel(0x03000000, pll_reg_base + 0x8);
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writel(0xd0800f00, pll_reg_base + 0x4);
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clrbits_be32(pll_reg_base + 0x8, BIT(30));
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udelay(5);
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setbits_be32(pll_reg_base + 0x8, BIT(30));
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udelay(5);
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wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
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clrbits_be32(pll_reg_base + 0x8, BIT(30));
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udelay(5);
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/* Check if CPU SRIF PLL locked. */
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reg = readl(pll_reg_base + 0x8);
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reg = (reg & 0x7ffff8) >> 3;
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} while (reg >= 0x40000);
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}
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void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
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{
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void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
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AR934X_SRIF_SIZE, MAP_NOCACHE);
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void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
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AR71XX_PLL_SIZE, MAP_NOCACHE);
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const struct ar934x_pll_config *pll_cfg;
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int i, pll_nint, pll_refdiv, xtal_40 = 0;
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u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
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/* Configure SRIF PLL with initial values. */
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writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
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writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
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writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
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writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
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writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
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/* Test for 40MHz XTAL */
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reg = ath79_get_bootstrap();
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if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
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xtal_40 = 1;
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cpu_srif = 0x41c00000;
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ddr_srif = 0x41680000;
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} else {
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xtal_40 = 0;
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cpu_srif = 0x29c00000;
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ddr_srif = 0x29680000;
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}
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/* Locate CPU/DDR PLL configuration */
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for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
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if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
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continue;
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if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
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continue;
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if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
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continue;
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/* Entry found */
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pll_cfg = &ar934x_clock_config[i].cpu_pll;
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pll_nint = pll_cfg->nint[xtal_40];
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pll_refdiv = pll_cfg->refdiv;
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cpu_pll =
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(pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
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(pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
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(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
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(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
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pll_cfg = &ar934x_clock_config[i].ddr_pll;
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pll_nint = pll_cfg->nint[xtal_40];
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pll_refdiv = pll_cfg->refdiv;
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ddr_pll =
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(pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
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(pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
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(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
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(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
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break;
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}
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/* PLL configuration not found, hang. */
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if (i == ARRAY_SIZE(ar934x_clock_config))
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hang();
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/* Set PLL Bypass */
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
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setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
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/* Configure CPU PLL */
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writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
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pll_regs + AR934X_PLL_CPU_CONFIG_REG);
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/* Configure DDR PLL */
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writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
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pll_regs + AR934X_PLL_DDR_CONFIG_REG);
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/* Configure PLL routing */
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writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
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(0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
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(0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
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(1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
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AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
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AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
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AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
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pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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/* Configure SRIF PLLs, which is completely undocumented :-) */
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ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
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ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
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/* Unset PLL Bypass */
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
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clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
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AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
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/* Enable PLL dithering */
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writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
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(0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
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pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
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writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
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pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
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}
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static u32 ar934x_get_xtal(void)
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{
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u32 val;
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val = ath79_get_bootstrap();
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if (val & AR934X_BOOTSTRAP_REF_CLK_40)
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return 40000000;
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else
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return 25000000;
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}
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int get_serial_clock(void)
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{
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return ar934x_get_xtal();
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}
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static u32 ar934x_cpupll_to_hz(const u32 regval)
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{
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const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NINT_MASK;
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const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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const u32 xtal = ar934x_get_xtal();
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return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
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}
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static u32 ar934x_ddrpll_to_hz(const u32 regval)
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{
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const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NINT_MASK;
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const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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const u32 xtal = ar934x_get_xtal();
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return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
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}
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static void ar934x_update_clock(void)
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{
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void __iomem *regs;
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u32 ctrl, cpu, cpupll, ddr, ddrpll;
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u32 cpudiv, ddrdiv, busdiv;
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u32 cpuclk, ddrclk, busclk;
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regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
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ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
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ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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cpupll = ar934x_cpupll_to_hz(cpu);
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ddrpll = ar934x_ddrpll_to_hz(ddr);
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if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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cpuclk = ar934x_get_xtal();
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else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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cpuclk = cpupll;
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else
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cpuclk = ddrpll;
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if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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ddrclk = ar934x_get_xtal();
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else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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ddrclk = ddrpll;
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else
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ddrclk = cpupll;
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if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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busclk = ar934x_get_xtal();
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else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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busclk = ddrpll;
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else
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busclk = cpupll;
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cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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gd->cpu_clk = cpuclk / (cpudiv + 1);
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gd->mem_clk = ddrclk / (ddrdiv + 1);
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gd->bus_clk = busclk / (busdiv + 1);
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}
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ulong get_bus_freq(ulong dummy)
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{
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ar934x_update_clock();
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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ar934x_update_clock();
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return gd->mem_clk;
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}
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int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ar934x_update_clock();
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printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
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printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
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printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
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"display clocks",
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""
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);
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