289 lines
7.0 KiB
Plaintext
289 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
/*
|
|
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/sun50i-h6-ccu.h>
|
|
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
|
|
#include <dt-bindings/reset/sun50i-h6-ccu.h>
|
|
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
|
|
|
|
/ {
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
iosc: internal-osc-clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <16000000>;
|
|
clock-accuracy = <300000000>;
|
|
clock-output-names = "iosc";
|
|
};
|
|
|
|
osc24M: osc24M_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "osc24M";
|
|
};
|
|
|
|
osc32k: osc32k_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "osc32k";
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
ccu: clock@3001000 {
|
|
compatible = "allwinner,sun50i-h6-ccu";
|
|
reg = <0x03001000 0x1000>;
|
|
clocks = <&osc24M>, <&osc32k>, <&iosc>;
|
|
clock-names = "hosc", "losc", "iosc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@3021000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x03021000 0x1000>,
|
|
<0x03022000 0x2000>,
|
|
<0x03024000 0x2000>,
|
|
<0x03026000 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
pio: pinctrl@300b000 {
|
|
compatible = "allwinner,sun50i-h6-pinctrl";
|
|
reg = <0x0300b000 0x400>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
mmc0_pins: mmc0-pins {
|
|
pins = "PF0", "PF1", "PF2", "PF3",
|
|
"PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc2_pins: mmc2-pins {
|
|
pins = "PC1", "PC4", "PC5", "PC6",
|
|
"PC7", "PC8", "PC9", "PC10",
|
|
"PC11", "PC12", "PC13", "PC14";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
uart0_ph_pins: uart0-ph {
|
|
pins = "PH0", "PH1";
|
|
function = "uart0";
|
|
};
|
|
};
|
|
|
|
mmc0: mmc@4020000 {
|
|
compatible = "allwinner,sun50i-h6-mmc",
|
|
"allwinner,sun50i-a64-mmc";
|
|
reg = <0x04020000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC0>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@4021000 {
|
|
compatible = "allwinner,sun50i-h6-mmc",
|
|
"allwinner,sun50i-a64-mmc";
|
|
reg = <0x04021000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC1>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@4022000 {
|
|
compatible = "allwinner,sun50i-h6-emmc",
|
|
"allwinner,sun50i-a64-emmc";
|
|
reg = <0x04022000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
clock-names = "ahb", "mmc";
|
|
resets = <&ccu RST_BUS_MMC2>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@5000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@5000400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@5000800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@5000c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_ccu: clock@7010000 {
|
|
compatible = "allwinner,sun50i-h6-r-ccu";
|
|
reg = <0x07010000 0x400>;
|
|
clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
|
<&ccu CLK_PLL_PERIPH0>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
r_intc: interrupt-controller@7021000 {
|
|
compatible = "allwinner,sun50i-h6-r-intc",
|
|
"allwinner,sun6i-a31-r-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x07021000 0x400>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_pio: pinctrl@7022000 {
|
|
compatible = "allwinner,sun50i-h6-r-pinctrl";
|
|
reg = <0x07022000 0x400>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
r_i2c_pins: r-i2c {
|
|
pins = "PL0", "PL1";
|
|
function = "s_i2c";
|
|
};
|
|
};
|
|
|
|
r_i2c: i2c@7081400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07081400 0x400>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB2_I2C>;
|
|
resets = <&r_ccu RST_R_APB2_I2C>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_i2c_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|