63 lines
1.2 KiB
Plaintext
63 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
|
|
*
|
|
* Copyright 2013 Freescale Semiconductor Inc.
|
|
* Copyright 2018 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/include/ "e6500_power_isa.dtsi"
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: PowerPC,e6500@0 {
|
|
device_type = "cpu";
|
|
reg = <0 1>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
cpu1: PowerPC,e6500@2 {
|
|
device_type = "cpu";
|
|
reg = <2 3>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
cpu2: PowerPC,e6500@4 {
|
|
device_type = "cpu";
|
|
reg = <4 5>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
cpu3: PowerPC,e6500@6 {
|
|
device_type = "cpu";
|
|
reg = <6 7>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
};
|
|
|
|
soc: soc@ffe000000 {
|
|
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
|
reg = <0xf 0xfe000000 0 0x00001000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "simple-bus";
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <4>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "fsl,mpic";
|
|
device_type = "open-pic";
|
|
clock-frequency = <0x0>;
|
|
};
|
|
};
|
|
};
|