229 lines
5.4 KiB
Plaintext
229 lines
5.4 KiB
Plaintext
STMicroelectronics STM32MP1 clock tree initialization
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=====================================================
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The STM32MP clock tree initialization is based on device tree information
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for RCC IP and on fixed clocks.
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-------------------------------
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RCC CLOCK = st,stm32mp1-rcc-clk
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-------------------------------
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The RCC IP is both a reset and a clock controller but this documentation only
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describes the fields added for clock tree initialization which are not present
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in Linux binding.
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Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
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with Linux.
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Required properties:
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- compatible: Should be "st,stm32mp1-rcc-clk"
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- st,clksrc : The clock source in this order
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for STM32MP15x: 9 clock sources are requested
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MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
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with value equals to RCC clock specifier as defined in
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dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
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- st,clkdiv : The div parameters in this order
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for STM32MP15x: 11 dividers value are requested
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MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
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with DIV coding defined in RCC associated register RCC_xxxDIVR
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most the case, it is:
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0x0: not divided
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0x1: division by 2
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0x2: division by 4
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0x3: division by 8
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...
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but for RTC MCO1 MCO2, the coding is different:
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0x0: not divided
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0x1: division by 2
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0x2: division by 3
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0x3: division by 4
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...
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Optional Properties:
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- st,pll
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PLL children node for PLL1 to PLL4 : (see ref manual for details)
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with associated index 0 to 3 (st,pll@0 to st,pll@4)
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PLLx is off when the associated node is absent
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- Sub-nodes:
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- cfg: The parameters for PLL configuration in this order:
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DIVM DIVN DIVP DIVQ DIVR Output
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with DIV value as defined in RCC spec:
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0x0: bypass (division by 1)
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0x1: division by 2
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0x2: division by 3
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0x3: division by 4
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...
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and Output = bitfield for each output value = 1:ON/0:OFF
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BIT(0) => output P : DIVPEN
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BIT(1) => output Q : DIVQEN
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BIT(2) => output R : DIVREN
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NB : macro PQR(p,q,r) can be used to build this value
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with p,p,r = 0 or 1
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- frac : Fractional part of the multiplication factor
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(optional, PLL is in integer mode when absent)
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- csg : Clock Spreading Generator (optional)
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with parameters in this order:
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MOD_PER INC_STEP SSCG_MODE
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* MOD_PER: Modulation Period Adjustment
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* INC_STEP: Modulation Depth Adjustment
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* SSCG_MODE: Spread spectrum clock generator mode
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you can use associated defines from stm32mp1-clksrc.h
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* SSCG_MODE_CENTER_SPREAD = 0
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* SSCG_MODE_DOWN_SPREAD = 1
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- st,pkcs : used to configure the peripherals kernel clock selection
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containing a list of peripheral kernel clock source identifier as defined
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in the file dt-bindings/clock/stm32mp1-clksrc.h
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Example:
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rcc: rcc@50000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x50000000 0x1000>;
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rcc_clk: rcc-clk@50000000 {
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#clock-cells = <1>;
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compatible = "st,stm32mp1-rcc-clk";
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st,clksrc = < CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_HSI
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_HSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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5 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pll@0 {
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cfg = < 1 53 0 0 0 1 >;
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frac = < 0x810 >;
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};
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st,pll@1 {
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cfg = < 1 43 1 0 0 PQR(0,1,1) >;
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csg = < 10 20 1 >;
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};
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st,pll@2 {
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cfg = < 2 85 3 13 3 0 >;
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csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
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};
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st,pll@3 {
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cfg = < 2 78 4 7 9 3 >;
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};
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st,pkcs = <
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CLK_STGEN_HSE
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CLK_CKPER_HSI
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CLK_USBPHY_PLL2P
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CLK_DSI_PLL2Q
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>;
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};
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};
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--------------------------
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other clocks = fixed-clock
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--------------------------
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The clock tree is also based on 5 fixed-clock in clocks node
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used to define the state of associated ST32MP1 oscillators:
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- clk-lsi
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- clk-lse
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- clk-hsi
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- clk-hse
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- clk-csi
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At boot the clock tree initialization will
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- enable the oscillator present in device tree
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- disable HSI oscillator if the node is absent (always activated by bootrom)
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Optional properties :
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a) for external oscillator: "clk-lse", "clk-hse"
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4 optional fields are managed
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- "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
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- "st,digbypass" Configure the bypass mode as full-swing digital signal
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(DIGBYP)
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- "st,css" Activate the clock security system (HSECSSON, LSECSSON)
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- "st,drive" (only for LSE) value of the drive for the oscillator
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(see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
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Example board file:
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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st,bypass;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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st,css;
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st,drive = <LSEDRV_LOWEST>;
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};
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};
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b) for internal oscillator: "clk-hsi"
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internally HSI clock is fixed to 64MHz for STM32MP157 soc
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in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
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So this clock frequency is used to compute the expected HSI_DIV
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for the clock tree initialisation
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ex: for HSIDIV = /1
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/ {
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clocks {
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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};
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ex: for HSIDIV = /2
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/ {
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clocks {
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000000>;
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};
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};
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