446 lines
13 KiB
C
446 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_srio.h>
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#include <linux/errno.h>
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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#define SRIO_PORT_ACCEPT_ALL 0x10000001
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#define SRIO_IB_ATMU_AR 0x80f55000
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#define SRIO_OB_ATMU_AR_MAINT 0x80077000
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#define SRIO_OB_ATMU_AR_RW 0x80045000
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#define SRIO_LCSBA1CSR_OFFSET 0x5c
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#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
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#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
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#define SRIO_LCSBA1CSR 0x60000000
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#endif
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#if defined(CONFIG_FSL_CORENET)
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
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#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
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#else
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#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
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#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
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#endif
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#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC85xx)
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#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
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#elif defined(CONFIG_MPC86xx)
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#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
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#define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
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#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
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(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
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#else
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#error "No defines for DEVDISR_SRIO"
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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/*
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* Erratum A-004034
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* Affects: SRIO
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* Description: During port initialization, the SRIO port performs
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* lane synchronization (detecting valid symbols on a lane) and
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* lane alignment (coordinating multiple lanes to receive valid data
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* across lanes). Internal errors in lane synchronization and lane
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* alignment may cause failure to achieve link initialization at
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* the configured port width.
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* An SRIO port configured as a 4x port may see one of these scenarios:
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* 1. One or more lanes fails to achieve lane synchronization. Depending
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* on which lanes fail, this may result in downtraining from 4x to 1x
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* on lane 0, 4x to 1x on lane R (redundant lane).
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* 2. The link may fail to achieve lane alignment as a 4x, even though
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* all 4 lanes achieve lane synchronization, and downtrain to a 1x.
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* An SRIO port configured as a 1x port may fail to complete port
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* initialization (PnESCSR[PU] never deasserts) because of scenario 1.
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* Impact: SRIO port may downtrain to 1x, or may fail to complete
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* link initialization. Once a port completes link initialization
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* successfully, it will operate normally.
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*/
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static int srio_erratum_a004034(u8 port)
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{
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serdes_corenet_t *srds_regs;
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u32 conf_lane;
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u32 init_lane;
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int idx, first, last;
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u32 i;
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unsigned long long end_tick;
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struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
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conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
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>> (12 - port * 4)) & 0x3;
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init_lane = (in_be32((void *)&srio_regs->lp_serial
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.port[port].pccsr) >> 27) & 0x7;
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/*
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* Start a counter set to ~2 ms after the SERDES reset is
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* complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
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* corresponding to the SERDES bank/PLL for the SRIO port).
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*/
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if (in_be32((void *)&srds_regs->bank[0].rstctl)
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& SRDS_RSTCTL_RSTDONE) {
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/*
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* Poll the port uninitialized status (SRIO PnESCSR[PO]) until
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* PO=1 or the counter expires. If the counter expires, the
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* port has failed initialization: go to recover steps. If PO=1
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* and the desired port width is 1x, go to normal steps. If
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* PO = 1 and the desired port width is 4x, go to recover steps.
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*/
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end_tick = usec2ticks(2000) + get_ticks();
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do {
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if (in_be32((void *)&srio_regs->lp_serial
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.port[port].pescsr) & 0x2) {
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if (conf_lane == 0x1)
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goto host_ok;
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else {
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if (init_lane == 0x2)
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goto host_ok;
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else
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break;
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}
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}
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} while (end_tick > get_ticks());
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/* recover at most 3 times */
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for (i = 0; i < 3; i++) {
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/* Set SRIO PnCCSR[PD]=1 */
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setbits_be32((void *)&srio_regs->lp_serial
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.port[port].pccsr,
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0x800000);
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/*
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* Set SRIO PnPCR[OBDEN] on the host to
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* enable the discarding of any pending packets.
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*/
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setbits_be32((void *)&srio_regs->impl.port[port].pcr,
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0x04);
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/* Wait 50 us */
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udelay(50);
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/* Run sync command */
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isync();
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if (port)
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first = serdes_get_first_lane(SRIO2);
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else
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first = serdes_get_first_lane(SRIO1);
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if (unlikely(first < 0))
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return -ENODEV;
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if (conf_lane == 0x1)
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last = first;
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else
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last = first + 3;
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/*
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* Set SERDES BnGCRm0[RRST]=0 for each SRIO
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* bank n and lane m.
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*/
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for (idx = first; idx <= last; idx++)
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clrbits_be32(&srds_regs->lane[idx].gcr0,
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SRDS_GCR0_RRST);
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/*
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* Read SERDES BnGCRm0 for each SRIO
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* bank n and lane m
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*/
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for (idx = first; idx <= last; idx++)
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in_be32(&srds_regs->lane[idx].gcr0);
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/* Run sync command */
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isync();
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/* Wait >= 100 ns */
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udelay(1);
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/*
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* Set SERDES BnGCRm0[RRST]=1 for each SRIO
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* bank n and lane m.
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*/
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for (idx = first; idx <= last; idx++)
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setbits_be32(&srds_regs->lane[idx].gcr0,
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SRDS_GCR0_RRST);
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/*
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* Read SERDES BnGCRm0 for each SRIO
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* bank n and lane m
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*/
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for (idx = first; idx <= last; idx++)
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in_be32(&srds_regs->lane[idx].gcr0);
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/* Run sync command */
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isync();
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/* Wait >= 300 ns */
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udelay(1);
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/* Write 1 to clear all bits in SRIO PnSLCSR */
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out_be32((void *)&srio_regs->impl.port[port].slcsr,
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0xffffffff);
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/* Clear SRIO PnPCR[OBDEN] on the host */
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clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
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0x04);
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/* Set SRIO PnCCSR[PD]=0 */
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clrbits_be32((void *)&srio_regs->lp_serial
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.port[port].pccsr,
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0x800000);
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/* Wait >= 24 ms */
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udelay(24000);
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/* Poll the state of the port again */
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init_lane =
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(in_be32((void *)&srio_regs->lp_serial
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.port[port].pccsr) >> 27) & 0x7;
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if (in_be32((void *)&srio_regs->lp_serial
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.port[port].pescsr) & 0x2) {
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if (conf_lane == 0x1)
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goto host_ok;
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else {
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if (init_lane == 0x2)
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goto host_ok;
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}
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}
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if (i == 2)
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return -ENODEV;
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}
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} else
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return -ENODEV;
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host_ok:
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/* Poll PnESCSR[OES] on the host until it is clear */
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end_tick = usec2ticks(1000000) + get_ticks();
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do {
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if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
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& 0x10000)) {
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out_be32(((void *)&srio_regs->lp_serial
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.port[port].pescsr), 0xffffffff);
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out_be32(((void *)&srio_regs->phys_err
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.port[port].edcsr), 0);
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out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
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return 0;
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}
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} while (end_tick > get_ticks());
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return -ENODEV;
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}
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#endif
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void srio_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
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int srio1_used = 0, srio2_used = 0;
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u32 *devdisr;
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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devdisr = &gur->devdisr3;
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#else
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devdisr = &gur->devdisr;
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#endif
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if (is_serdes_configured(SRIO1)) {
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set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
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LAW_TRGT_IF_RIO_1);
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srio1_used = 1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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if (srio_erratum_a004034(0) < 0)
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printf("SRIO1: enabled but port error\n");
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else
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#endif
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printf("SRIO1: enabled\n");
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} else {
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printf("SRIO1: disabled\n");
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}
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#ifdef CONFIG_SRIO2
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if (is_serdes_configured(SRIO2)) {
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set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
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law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
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LAW_TRGT_IF_RIO_2);
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srio2_used = 1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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if (srio_erratum_a004034(1) < 0)
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printf("SRIO2: enabled but port error\n");
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else
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#endif
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printf("SRIO2: enabled\n");
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} else {
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printf("SRIO2: disabled\n");
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}
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#endif
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#ifdef CONFIG_FSL_CORENET
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/* On FSL_CORENET devices we can disable individual ports */
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if (!srio1_used)
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setbits_be32(devdisr, _DEVDISR_SRIO1);
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if (!srio2_used)
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setbits_be32(devdisr, _DEVDISR_SRIO2);
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#endif
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/* neither port is used - disable everything */
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if (!srio1_used && !srio2_used) {
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setbits_be32(devdisr, _DEVDISR_SRIO1);
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setbits_be32(devdisr, _DEVDISR_SRIO2);
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setbits_be32(devdisr, _DEVDISR_RMU);
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}
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}
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#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
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void srio_boot_master(int port)
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{
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struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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/* set port accept-all */
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out_be32((void *)&srio->impl.port[port - 1].ptaacr,
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SRIO_PORT_ACCEPT_ALL);
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debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
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/* configure inbound window for slave's u-boot image */
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debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
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(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
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/* configure inbound window for slave's u-boot image */
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debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
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(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
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CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
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/* configure inbound window for slave's ucode and ENV */
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debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
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"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
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(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
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(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
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CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
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CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
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CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
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out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
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SRIO_IB_ATMU_AR
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| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
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}
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void srio_boot_master_release_slave(int port)
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{
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struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
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u32 escsr;
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debug("SRIOBOOT - MASTER: "
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"Check the port status and release slave core ...\n");
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escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
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if (escsr & 0x2) {
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if (escsr & 0x10100) {
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debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
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port);
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} else {
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debug("SRIOBOOT - MASTER: "
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"Port [ %d ] is ready, now release slave's core ...\n",
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port);
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/*
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* configure outbound window
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* with maintenance attribute to set slave's LCSBA1CSR
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*/
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[1].rowtar, 0);
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[1].rowtear, 0);
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if (port - 1)
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[1].rowbar,
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CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
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else
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[1].rowbar,
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CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[1].rowar,
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SRIO_OB_ATMU_AR_MAINT
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| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
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/*
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* configure outbound window
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* with R/W attribute to set slave's BRR
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*/
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[2].rowtar,
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SRIO_LCSBA1CSR >> 9);
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[2].rowtear, 0);
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if (port - 1)
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[2].rowbar,
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(CONFIG_SYS_SRIO2_MEM_PHYS
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+ SRIO_MAINT_WIN_SIZE) >> 12);
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else
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[2].rowbar,
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(CONFIG_SYS_SRIO1_MEM_PHYS
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+ SRIO_MAINT_WIN_SIZE) >> 12);
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out_be32((void *)&srio->atmu.port[port - 1]
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.outbw[2].rowar,
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SRIO_OB_ATMU_AR_RW
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| atmu_size_mask(SRIO_RW_WIN_SIZE));
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/*
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* Set the LCSBA1CSR register in slave
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* by the maint-outbound window
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*/
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if (port - 1) {
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out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET,
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SRIO_LCSBA1CSR);
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while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_LCSBA1CSR_OFFSET)
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!= SRIO_LCSBA1CSR)
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;
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/*
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* And then set the BRR register
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* to release slave core
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*/
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out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
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+ SRIO_MAINT_WIN_SIZE
|
|
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
|
|
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
|
|
} else {
|
|
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
|
|
+ SRIO_LCSBA1CSR_OFFSET,
|
|
SRIO_LCSBA1CSR);
|
|
while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
|
|
+ SRIO_LCSBA1CSR_OFFSET)
|
|
!= SRIO_LCSBA1CSR)
|
|
;
|
|
/*
|
|
* And then set the BRR register
|
|
* to release slave core
|
|
*/
|
|
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
|
|
+ SRIO_MAINT_WIN_SIZE
|
|
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
|
|
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
|
|
}
|
|
debug("SRIOBOOT - MASTER: "
|
|
"Release slave successfully! Now the slave should start up!\n");
|
|
}
|
|
} else
|
|
debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
|
|
}
|
|
#endif
|