157 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			157 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2000, 2001 Broadcom Corporation
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * as published by the Free Software Foundation; either version 2
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|  * of the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
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|  */
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| #include <linux/clockchips.h>
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| #include <linux/interrupt.h>
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| #include <linux/irq.h>
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| #include <linux/percpu.h>
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| #include <linux/smp.h>
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| 
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| #include <asm/addrspace.h>
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| #include <asm/io.h>
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| #include <asm/time.h>
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| 
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| #include <asm/sibyte/sb1250.h>
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| #include <asm/sibyte/sb1250_regs.h>
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| #include <asm/sibyte/sb1250_int.h>
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| #include <asm/sibyte/sb1250_scd.h>
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| 
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| #define IMR_IP2_VAL	K_INT_MAP_I0
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| #define IMR_IP3_VAL	K_INT_MAP_I1
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| #define IMR_IP4_VAL	K_INT_MAP_I2
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| 
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| /*
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|  * The general purpose timer ticks at 1MHz independent if
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|  * the rest of the system
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|  */
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| 
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| static int sibyte_shutdown(struct clock_event_device *evt)
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| {
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| 	void __iomem *cfg;
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| 
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| 	cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG));
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| 
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| 	/* Stop the timer until we actually program a shot */
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| 	__raw_writeq(0, cfg);
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| 
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| 	return 0;
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| }
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| 
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| static int sibyte_set_periodic(struct clock_event_device *evt)
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| {
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| 	unsigned int cpu = smp_processor_id();
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| 	void __iomem *cfg, *init;
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| 
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| 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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| 	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
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| 
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| 	__raw_writeq(0, cfg);
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| 	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
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| 	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
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| 
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| 	return 0;
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| }
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| 
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| static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
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| {
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| 	unsigned int cpu = smp_processor_id();
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| 	void __iomem *cfg, *init;
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| 
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| 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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| 	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
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| 
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| 	__raw_writeq(0, cfg);
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| 	__raw_writeq(delta - 1, init);
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| 	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
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| 
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| 	return 0;
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| }
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| 
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| static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
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| {
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| 	unsigned int cpu = smp_processor_id();
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| 	struct clock_event_device *cd = dev_id;
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| 	void __iomem *cfg;
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| 	unsigned long tmode;
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| 
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| 	if (clockevent_state_periodic(cd))
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| 		tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
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| 	else
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| 		tmode = 0;
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| 
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| 	/* ACK interrupt */
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| 	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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| 	____raw_writeq(tmode, cfg);
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| 
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| 	cd->event_handler(cd);
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| 
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| 	return IRQ_HANDLED;
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| }
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| 
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| static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
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| static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
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| static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
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| 
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| void sb1250_clockevent_init(void)
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| {
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| 	unsigned int cpu = smp_processor_id();
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| 	unsigned int irq = K_INT_TIMER_0 + cpu;
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| 	struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
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| 	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
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| 	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
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| 
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| 	/* Only have 4 general purpose timers, and we use last one as hpt */
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| 	BUG_ON(cpu > 2);
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| 
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| 	sprintf(name, "sb1250-counter-%d", cpu);
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| 	cd->name		= name;
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| 	cd->features		= CLOCK_EVT_FEAT_PERIODIC |
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| 				  CLOCK_EVT_FEAT_ONESHOT;
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| 	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
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| 	cd->max_delta_ns	= clockevent_delta2ns(0x7fffff, cd);
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| 	cd->max_delta_ticks	= 0x7fffff;
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| 	cd->min_delta_ns	= clockevent_delta2ns(2, cd);
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| 	cd->min_delta_ticks	= 2;
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| 	cd->rating		= 200;
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| 	cd->irq			= irq;
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| 	cd->cpumask		= cpumask_of(cpu);
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| 	cd->set_next_event	= sibyte_next_event;
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| 	cd->set_state_shutdown	= sibyte_shutdown;
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| 	cd->set_state_periodic	= sibyte_set_periodic;
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| 	cd->set_state_oneshot	= sibyte_shutdown;
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| 	clockevents_register_device(cd);
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| 
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| 	sb1250_mask_irq(cpu, irq);
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| 
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| 	/*
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| 	 * Map the timer interrupt to IP[4] of this cpu
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| 	 */
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| 	__raw_writeq(IMR_IP4_VAL,
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| 		     IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
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| 			    (irq << 3)));
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| 
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| 	sb1250_unmask_irq(cpu, irq);
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| 
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| 	action->handler = sibyte_counter_handler;
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| 	action->flags	= IRQF_PERCPU | IRQF_TIMER;
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| 	action->name	= name;
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| 	action->dev_id	= cd;
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| 
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| 	irq_set_affinity(irq, cpumask_of(cpu));
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| 	setup_irq(irq, action);
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| }
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