566 lines
		
	
	
		
			12 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			566 lines
		
	
	
		
			12 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * This file is subject to the terms and conditions of the GNU General Public
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|  * License.  See the file "COPYING" in the main directory of this archive
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|  * for more details.
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|  *
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|  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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|  */
 | |
| 
 | |
| #include <linux/init.h>
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| #include <linux/export.h>
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| #include <linux/mutex.h>
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| #include <linux/err.h>
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| #include <linux/clk.h>
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| #include <linux/clkdev.h>
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| #include <linux/delay.h>
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| #include <bcm63xx_cpu.h>
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| #include <bcm63xx_io.h>
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| #include <bcm63xx_regs.h>
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| #include <bcm63xx_reset.h>
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| 
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| struct clk {
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| 	void		(*set)(struct clk *, int);
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| 	unsigned int	rate;
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| 	unsigned int	usage;
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| 	int		id;
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| };
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| 
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| static DEFINE_MUTEX(clocks_mutex);
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| 
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| 
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| static void clk_enable_unlocked(struct clk *clk)
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| {
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| 	if (clk->set && (clk->usage++) == 0)
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| 		clk->set(clk, 1);
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| }
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| 
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| static void clk_disable_unlocked(struct clk *clk)
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| {
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| 	if (clk->set && (--clk->usage) == 0)
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| 		clk->set(clk, 0);
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| }
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| 
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| static void bcm_hwclock_set(u32 mask, int enable)
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| {
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| 	u32 reg;
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| 
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| 	reg = bcm_perf_readl(PERF_CKCTL_REG);
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| 	if (enable)
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| 		reg |= mask;
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| 	else
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| 		reg &= ~mask;
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| 	bcm_perf_writel(reg, PERF_CKCTL_REG);
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| }
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| 
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| /*
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|  * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
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|  */
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| static void enet_misc_set(struct clk *clk, int enable)
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| {
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| 	u32 mask;
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| 
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| 	if (BCMCPU_IS_6338())
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| 		mask = CKCTL_6338_ENET_EN;
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| 	else if (BCMCPU_IS_6345())
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| 		mask = CKCTL_6345_ENET_EN;
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| 	else if (BCMCPU_IS_6348())
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| 		mask = CKCTL_6348_ENET_EN;
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| 	else
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| 		/* BCMCPU_IS_6358 */
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| 		mask = CKCTL_6358_EMUSB_EN;
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| 	bcm_hwclock_set(mask, enable);
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| }
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| 
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| static struct clk clk_enet_misc = {
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| 	.set	= enet_misc_set,
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| };
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| 
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| /*
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|  * Ethernet MAC clocks: only revelant on 6358, silently enable misc
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|  * clocks
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|  */
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| static void enetx_set(struct clk *clk, int enable)
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| {
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| 	if (enable)
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| 		clk_enable_unlocked(&clk_enet_misc);
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| 	else
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| 		clk_disable_unlocked(&clk_enet_misc);
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| 
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| 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
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| 		u32 mask;
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| 
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| 		if (clk->id == 0)
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| 			mask = CKCTL_6358_ENET0_EN;
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| 		else
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| 			mask = CKCTL_6358_ENET1_EN;
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| 		bcm_hwclock_set(mask, enable);
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| 	}
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| }
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| 
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| static struct clk clk_enet0 = {
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| 	.id	= 0,
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| 	.set	= enetx_set,
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| };
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| 
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| static struct clk clk_enet1 = {
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| 	.id	= 1,
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| 	.set	= enetx_set,
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| };
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| 
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| /*
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|  * Ethernet PHY clock
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|  */
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| static void ephy_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
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| 		bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
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| }
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| 
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| 
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| static struct clk clk_ephy = {
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| 	.set	= ephy_set,
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| };
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| 
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| /*
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|  * Ethernet switch SAR clock
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|  */
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| static void swpkt_sar_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6368())
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| 		bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN, enable);
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| 	else
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| 		return;
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| }
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| 
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| static struct clk clk_swpkt_sar = {
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| 	.set	= swpkt_sar_set,
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| };
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| 
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| /*
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|  * Ethernet switch USB clock
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|  */
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| static void swpkt_usb_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6368())
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| 		bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN, enable);
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| 	else
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| 		return;
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| }
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| 
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| static struct clk clk_swpkt_usb = {
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| 	.set	= swpkt_usb_set,
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| };
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| 
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| /*
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|  * Ethernet switch clock
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|  */
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| static void enetsw_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6328()) {
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| 		bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
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| 	} else if (BCMCPU_IS_6362()) {
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| 		bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
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| 	} else if (BCMCPU_IS_6368()) {
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| 		if (enable) {
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| 			clk_enable_unlocked(&clk_swpkt_sar);
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| 			clk_enable_unlocked(&clk_swpkt_usb);
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| 		} else {
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| 			clk_disable_unlocked(&clk_swpkt_usb);
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| 			clk_disable_unlocked(&clk_swpkt_sar);
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| 		}
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| 		bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);
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| 	} else {
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| 		return;
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| 	}
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| 
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| 	if (enable) {
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| 		/* reset switch core afer clock change */
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| 		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
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| 		msleep(10);
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| 		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
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| 		msleep(10);
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| 	}
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| }
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| 
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| static struct clk clk_enetsw = {
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| 	.set	= enetsw_set,
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| };
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| 
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| /*
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|  * PCM clock
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|  */
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| static void pcm_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_3368())
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| 		bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
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| 	if (BCMCPU_IS_6358())
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| 		bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
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| }
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| 
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| static struct clk clk_pcm = {
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| 	.set	= pcm_set,
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| };
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| 
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| /*
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|  * USB host clock
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|  */
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| static void usbh_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6328())
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| 		bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
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| 	else if (BCMCPU_IS_6348())
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| 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
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| 	else if (BCMCPU_IS_6362())
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| 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
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| 	else if (BCMCPU_IS_6368())
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| 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
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| }
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| 
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| static struct clk clk_usbh = {
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| 	.set	= usbh_set,
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| };
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| 
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| /*
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|  * USB device clock
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|  */
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| static void usbd_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6328())
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| 		bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
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| 	else if (BCMCPU_IS_6362())
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| 		bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
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| 	else if (BCMCPU_IS_6368())
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| 		bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
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| }
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| 
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| static struct clk clk_usbd = {
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| 	.set	= usbd_set,
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| };
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| 
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| /*
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|  * SPI clock
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|  */
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| static void spi_set(struct clk *clk, int enable)
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| {
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| 	u32 mask;
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| 
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| 	if (BCMCPU_IS_6338())
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| 		mask = CKCTL_6338_SPI_EN;
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| 	else if (BCMCPU_IS_6348())
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| 		mask = CKCTL_6348_SPI_EN;
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| 	else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
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| 		mask = CKCTL_6358_SPI_EN;
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| 	else if (BCMCPU_IS_6362())
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| 		mask = CKCTL_6362_SPI_EN;
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| 	else
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| 		/* BCMCPU_IS_6368 */
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| 		mask = CKCTL_6368_SPI_EN;
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| 	bcm_hwclock_set(mask, enable);
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| }
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| 
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| static struct clk clk_spi = {
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| 	.set	= spi_set,
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| };
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| 
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| /*
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|  * HSSPI clock
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|  */
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| static void hsspi_set(struct clk *clk, int enable)
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| {
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| 	u32 mask;
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| 
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| 	if (BCMCPU_IS_6328())
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| 		mask = CKCTL_6328_HSSPI_EN;
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| 	else if (BCMCPU_IS_6362())
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| 		mask = CKCTL_6362_HSSPI_EN;
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| 	else
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| 		return;
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| 
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| 	bcm_hwclock_set(mask, enable);
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| }
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| 
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| static struct clk clk_hsspi = {
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| 	.set	= hsspi_set,
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| };
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| 
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| /*
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|  * HSSPI PLL
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|  */
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| static struct clk clk_hsspi_pll;
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| 
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| /*
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|  * XTM clock
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|  */
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| static void xtm_set(struct clk *clk, int enable)
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| {
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| 	if (!BCMCPU_IS_6368())
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| 		return;
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| 
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| 	if (enable)
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| 		clk_enable_unlocked(&clk_swpkt_sar);
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| 	else
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| 		clk_disable_unlocked(&clk_swpkt_sar);
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| 
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| 	bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);
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| 
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| 	if (enable) {
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| 		/* reset sar core afer clock change */
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| 		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
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| 		mdelay(1);
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| 		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
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| 		mdelay(1);
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| 	}
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| }
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| 
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| 
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| static struct clk clk_xtm = {
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| 	.set	= xtm_set,
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| };
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| 
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| /*
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|  * IPsec clock
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|  */
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| static void ipsec_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6362())
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| 		bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
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| 	else if (BCMCPU_IS_6368())
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| 		bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
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| }
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| 
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| static struct clk clk_ipsec = {
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| 	.set	= ipsec_set,
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| };
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| 
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| /*
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|  * PCIe clock
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|  */
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| 
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| static void pcie_set(struct clk *clk, int enable)
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| {
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| 	if (BCMCPU_IS_6328())
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| 		bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
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| 	else if (BCMCPU_IS_6362())
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| 		bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
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| }
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| 
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| static struct clk clk_pcie = {
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| 	.set	= pcie_set,
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| };
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| 
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| /*
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|  * Internal peripheral clock
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|  */
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| static struct clk clk_periph = {
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| 	.rate	= (50 * 1000 * 1000),
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| };
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| 
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| 
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| /*
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|  * Linux clock API implementation
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|  */
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| int clk_enable(struct clk *clk)
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| {
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| 	mutex_lock(&clocks_mutex);
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| 	clk_enable_unlocked(clk);
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| 	mutex_unlock(&clocks_mutex);
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| 	return 0;
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| }
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| 
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| EXPORT_SYMBOL(clk_enable);
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| 
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| void clk_disable(struct clk *clk)
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| {
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| 	if (!clk)
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| 		return;
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| 
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| 	mutex_lock(&clocks_mutex);
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| 	clk_disable_unlocked(clk);
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| 	mutex_unlock(&clocks_mutex);
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| }
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| 
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| EXPORT_SYMBOL(clk_disable);
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| 
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| unsigned long clk_get_rate(struct clk *clk)
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| {
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| 	if (!clk)
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| 		return 0;
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| 
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| 	return clk->rate;
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| }
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| 
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| EXPORT_SYMBOL(clk_get_rate);
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| 
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| int clk_set_rate(struct clk *clk, unsigned long rate)
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| {
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| 	return 0;
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| }
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| EXPORT_SYMBOL_GPL(clk_set_rate);
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| 
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| long clk_round_rate(struct clk *clk, unsigned long rate)
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| {
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| 	return 0;
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| }
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| EXPORT_SYMBOL_GPL(clk_round_rate);
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| 
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| static struct clk_lookup bcm3368_clks[] = {
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| 	/* fixed rate clocks */
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| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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| 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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| 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
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| 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
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| 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
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| 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
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| };
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| 
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| static struct clk_lookup bcm6328_clks[] = {
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| 	/* fixed rate clocks */
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| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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| 	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
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| 	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
 | |
| };
 | |
| 
 | |
| static struct clk_lookup bcm6338_clks[] = {
 | |
| 	/* fixed rate clocks */
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| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
 | |
| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
 | |
| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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| 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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| 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
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| 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
 | |
| };
 | |
| 
 | |
| static struct clk_lookup bcm6345_clks[] = {
 | |
| 	/* fixed rate clocks */
 | |
| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
 | |
| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
 | |
| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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| 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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| 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
 | |
| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
 | |
| 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
 | |
| };
 | |
| 
 | |
| static struct clk_lookup bcm6348_clks[] = {
 | |
| 	/* fixed rate clocks */
 | |
| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
 | |
| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
 | |
| 	/* gated clocks */
 | |
| 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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| 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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| 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
 | |
| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
 | |
| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
 | |
| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
 | |
| 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
 | |
| 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
 | |
| };
 | |
| 
 | |
| static struct clk_lookup bcm6358_clks[] = {
 | |
| 	/* fixed rate clocks */
 | |
| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
 | |
| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
 | |
| 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
 | |
| 	/* gated clocks */
 | |
| 	CLKDEV_INIT(NULL, "enet0", &clk_enet0),
 | |
| 	CLKDEV_INIT(NULL, "enet1", &clk_enet1),
 | |
| 	CLKDEV_INIT(NULL, "ephy", &clk_ephy),
 | |
| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
 | |
| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
 | |
| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
 | |
| 	CLKDEV_INIT(NULL, "pcm", &clk_pcm),
 | |
| 	CLKDEV_INIT(NULL, "swpkt_sar", &clk_swpkt_sar),
 | |
| 	CLKDEV_INIT(NULL, "swpkt_usb", &clk_swpkt_usb),
 | |
| 	CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
 | |
| 	CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
 | |
| };
 | |
| 
 | |
| static struct clk_lookup bcm6362_clks[] = {
 | |
| 	/* fixed rate clocks */
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| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
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| 	CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
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| 	CLKDEV_INIT(NULL, "pcie", &clk_pcie),
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| 	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
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| };
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| 
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| static struct clk_lookup bcm6368_clks[] = {
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| 	/* fixed rate clocks */
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| 	CLKDEV_INIT(NULL, "periph", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
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| 	CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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| 	/* gated clocks */
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| 	CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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| 	CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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| 	CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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| 	CLKDEV_INIT(NULL, "spi", &clk_spi),
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| 	CLKDEV_INIT(NULL, "xtm", &clk_xtm),
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| 	CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
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| };
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| 
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| #define HSSPI_PLL_HZ_6328	133333333
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| #define HSSPI_PLL_HZ_6362	400000000
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| 
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| static int __init bcm63xx_clk_init(void)
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| {
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| 	switch (bcm63xx_get_cpu_id()) {
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| 	case BCM3368_CPU_ID:
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| 		clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
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| 		break;
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| 	case BCM6328_CPU_ID:
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| 		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;
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| 		clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
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| 		break;
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| 	case BCM6338_CPU_ID:
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| 		clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
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| 		break;
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| 	case BCM6345_CPU_ID:
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| 		clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
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| 		break;
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| 	case BCM6348_CPU_ID:
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| 		clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
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| 		break;
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| 	case BCM6358_CPU_ID:
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| 		clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
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| 		break;
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| 	case BCM6362_CPU_ID:
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| 		clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;
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| 		clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
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| 		break;
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| 	case BCM6368_CPU_ID:
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| 		clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
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| 		break;
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| 	}
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| 
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| 	return 0;
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| }
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| arch_initcall(bcm63xx_clk_init);
 | 
